Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-03 10:15:19 +00:00
Code Issues Packages Projects Releases Wiki Activity

Removed int/integer from parameters)

Browse Source
This commit is contained in:
David Harris 2023-01-27 14:27:04 -08:00
parent 44c7102026
commit 717cb4e6c5
12 changed files with 128 additions and 150 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
pipelined/src/ebu/ahbcacheinterface.sv
View File

@ -30,10 +30,10 @@
`include "wally-config.vh" `include "wally-config.vh"
module ahbcacheinterface #( module ahbcacheinterface #(
parameter integer BEATSPERLINE, // Number of AHBW words (beats) in cacheline parameter BEATSPERLINE, // Number of AHBW words (beats) in cacheline
parameter integer AHBWLOGBWPL, // Log2 of ^ parameter AHBWLOGBWPL, // Log2 of ^
parameter integer LINELEN, // Number of bits in cacheline parameter LINELEN, // Number of bits in cacheline
parameter integer LLENPOVERAHBW // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation) parameter LLENPOVERAHBW // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
)( )(
input logic HCLK, HRESETn, input logic HCLK, HRESETn,
// bus interface controls // bus interface controls

4
pipelined/src/ebu/buscachefsm.sv
View File

@ -32,8 +32,8 @@
// HCLK and clk must be the same clock! // HCLK and clk must be the same clock!
module buscachefsm #( module buscachefsm #(
parameter integer BeatCountThreshold, // Largest beat index parameter BeatCountThreshold, // Largest beat index
parameter integer AHBWLOGBWPL // Log2 of BEATSPERLINE parameter AHBWLOGBWPL // Log2 of BEATSPERLINE
)( )(
input logic HCLK, input logic HCLK,
input logic HRESETn, input logic HRESETn,

24
pipelined/src/ifu/bpred/RAsPredictor.sv
View File

@ -28,19 +28,17 @@
`include "wally-config.vh" `include "wally-config.vh"
module RASPredictor module RASPredictor #(parameter StackSize = 16) (
#(parameter int StackSize = 16 input logic clk,
) input logic reset,
(input logic clk, input logic PopF,
input logic reset, output logic [`XLEN-1:0] RASPCF,
input logic PopF, input logic [3:0] WrongPredInstrClassD,
output logic [`XLEN-1:0] RASPCF, input logic [3:0] InstrClassD,
input logic [3:0] WrongPredInstrClassD, input logic PushE,
input logic [3:0] InstrClassD, input logic incr,
input logic PushE, input logic [`XLEN-1:0] PCLinkE
input logic incr, );
input logic [`XLEN-1:0] PCLinkE
);
// *** need to update so it either doesn't push until the memory stage // *** need to update so it either doesn't push until the memory stage
// or need to repair flushed push. // or need to repair flushed push.

32
pipelined/src/ifu/bpred/btb.sv
View File

@ -30,23 +30,21 @@
`include "wally-config.vh" `include "wally-config.vh"
module btb module btb #(parameter Depth = 10) (
#(parameter int Depth = 10 input logic clk,
) input logic reset,
(input logic clk, input logic StallF, StallE,
input logic reset, input logic [`XLEN-1:0] PCNextF,
input logic StallF, StallE, output logic [`XLEN-1:0] BTBPredPCF,
input logic [`XLEN-1:0] PCNextF, output logic [3:0] InstrClass,
output logic [`XLEN-1:0] BTBPredPCF, output logic Valid,
output logic [3:0] InstrClass, // update
output logic Valid, input logic UpdateEN,
// update input logic [`XLEN-1:0] PCE,
input logic UpdateEN, input logic [`XLEN-1:0] IEUAdrE,
input logic [`XLEN-1:0] PCE, input logic [3:0] InstrClassE,
input logic [`XLEN-1:0] IEUAdrE, input logic UpdateInvalid
input logic [3:0] InstrClassE, );
input logic UpdateInvalid
);
localparam TotalDepth = 2 ** Depth; localparam TotalDepth = 2 ** Depth;
logic [TotalDepth-1:0] ValidBits; logic [TotalDepth-1:0] ValidBits;

27
pipelined/src/ifu/bpred/foldedgshare.sv
View File

@ -28,22 +28,19 @@
`include "wally-config.vh" `include "wally-config.vh"
module foldedgshare module foldedgshare #(parameter k = 16, depth = 10) (
#(parameter int k = 16, input logic clk,
parameter int depth = 10 input logic reset,
) input logic StallF, StallD, StallE, StallM, StallW,
(input logic clk, input logic FlushD, FlushE, FlushM, FlushW,
input logic reset,
input logic StallF, StallD, StallE, StallM, StallW,
input logic FlushD, FlushE, FlushM, FlushW,
// input logic [`XLEN-1:0] LookUpPC, // input logic [`XLEN-1:0] LookUpPC,
output logic [1:0] DirPredictionF, output logic [1:0] DirPredictionF,
output logic DirPredictionWrongE, output logic DirPredictionWrongE,
// update // update
input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW,
input logic PCSrcE input logic PCSrcE
); );
logic MatchF, MatchD, MatchE, MatchM, MatchW; logic MatchF, MatchD, MatchE, MatchM, MatchW;
logic MatchNextX, MatchXF; logic MatchNextX, MatchXF;

26
pipelined/src/ifu/bpred/globalhistory.sv
View File

@ -28,20 +28,18 @@
`include "wally-config.vh" `include "wally-config.vh"
module globalhistory module globalhistory #(parameter k = 10) (
#(parameter int k = 10 input logic clk,
) input logic reset,
(input logic clk, input logic StallF, StallD, StallE, StallM,
input logic reset, input logic FlushD, FlushE, FlushM,
input logic StallF, StallD, StallE, StallM, // input logic [`XLEN-1:0] LookUpPC,
input logic FlushD, FlushE, FlushM, output logic [1:0] DirPredictionF,
// input logic [`XLEN-1:0] LookUpPC, output logic DirPredictionWrongE,
output logic [1:0] DirPredictionF, // update
output logic DirPredictionWrongE, input logic [`XLEN-1:0] PCNextF, PCM,
// update input logic BranchInstrE, BranchInstrM, PCSrcE
input logic [`XLEN-1:0] PCNextF, PCM, );
input logic BranchInstrE, BranchInstrM, PCSrcE
);
logic [1:0] DirPredictionD, DirPredictionE; logic [1:0] DirPredictionD, DirPredictionE;
logic [1:0] NewDirPredictionE, NewDirPredictionM; logic [1:0] NewDirPredictionE, NewDirPredictionM;

24
pipelined/src/ifu/bpred/gshare.sv
View File

@ -28,20 +28,18 @@
`include "wally-config.vh" `include "wally-config.vh"
module gshare module gshare #(parameter k = 10) (
#(parameter int k = 10 input logic clk,
) input logic reset,
(input logic clk, input logic StallF, StallD, StallE, StallM,
input logic reset, input logic FlushD, FlushE, FlushM,
input logic StallF, StallD, StallE, StallM,
input logic FlushD, FlushE, FlushM,
// input logic [`XLEN-1:0] LookUpPC, // input logic [`XLEN-1:0] LookUpPC,
output logic [1:0] DirPredictionF, output logic [1:0] DirPredictionF,
output logic DirPredictionWrongE, output logic DirPredictionWrongE,
// update // update
input logic [`XLEN-1:0] PCNextF, PCM, input logic [`XLEN-1:0] PCNextF, PCM,
input logic BranchInstrE, BranchInstrM, PCSrcE input logic BranchInstrE, BranchInstrM, PCSrcE
); );
logic [k-1:0] IndexNextF, IndexM; logic [k-1:0] IndexNextF, IndexM;
logic [1:0] DirPredictionD, DirPredictionE; logic [1:0] DirPredictionD, DirPredictionE;

29
pipelined/src/ifu/bpred/localHistoryPredictor.sv
View File

@ -28,23 +28,20 @@
`include "wally-config.vh" `include "wally-config.vh"
module localHistoryPredictor module localHistoryPredictor #(parameter m = 6, // 2^m = number of local history branches
#( parameter int m = 6, // 2^m = number of local history branches k = 10) ( // number of past branches stored
parameter int k = 10 // number of past branches stored input logic clk,
) input logic reset,
(input logic clk, input logic StallF, StallE,
input logic reset, input logic [`XLEN-1:0] LookUpPC,
input logic StallF, StallE, output logic [1:0] Prediction,
input logic [`XLEN-1:0] LookUpPC, // update
output logic [1:0] Prediction, input logic [`XLEN-1:0] UpdatePC,
// update input logic UpdateEN, PCSrcE,
input logic [`XLEN-1:0] UpdatePC, input logic [1:0] UpdatePrediction
input logic UpdateEN, PCSrcE, );
input logic [1:0] UpdatePrediction
);
logic [2**m-1:0] [k-1:0] LHRNextF; logic [2**m-1:0][k-1:0] LHRNextF;
logic [k-1:0] LHRF, ForwardLHRNext, LHRFNext; logic [k-1:0] LHRF, ForwardLHRNext, LHRFNext;
logic [m-1:0] LookUpPCIndex, UpdatePCIndex; logic [m-1:0] LookUpPCIndex, UpdatePCIndex;
logic [1:0] PredictionMemory; logic [1:0] PredictionMemory;

26
pipelined/src/ifu/bpred/optgshare.sv
View File

@ -28,21 +28,19 @@
`include "wally-config.vh" `include "wally-config.vh"
module optgshare module optgshare #(parameter k = 10) (
#(parameter int k = 10 input logic clk,
) input logic reset,
(input logic clk, input logic StallF, StallD, StallE, StallM, StallW,
input logic reset, input logic FlushD, FlushE, FlushM, FlushW,
input logic StallF, StallD, StallE, StallM, StallW,
input logic FlushD, FlushE, FlushM, FlushW,
// input logic [`XLEN-1:0] LookUpPC, // input logic [`XLEN-1:0] LookUpPC,
output logic [1:0] DirPredictionF, output logic [1:0] DirPredictionF,
output logic DirPredictionWrongE, output logic DirPredictionWrongE,
// update // update
input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW,
input logic PCSrcE input logic PCSrcE
); );
logic MatchF, MatchD, MatchE, MatchM, MatchW; logic MatchF, MatchD, MatchE, MatchM, MatchW;
logic MatchNextX, MatchXF; logic MatchNextX, MatchXF;

26
pipelined/src/ifu/bpred/speculativeglobalhistory.sv
View File

@ -28,21 +28,19 @@
`include "wally-config.vh" `include "wally-config.vh"
module speculativeglobalhistory module speculativeglobalhistory #(parameter k = 10) (
#(parameter int k = 10 input logic clk,
) input logic reset,
(input logic clk, input logic StallF, StallD, StallE, StallM, StallW,
input logic reset, input logic FlushD, FlushE, FlushM, FlushW,
input logic StallF, StallD, StallE, StallM, StallW,
input logic FlushD, FlushE, FlushM, FlushW,
// input logic [`XLEN-1:0] LookUpPC, // input logic [`XLEN-1:0] LookUpPC,
output logic [1:0] DirPredictionF, output logic [1:0] DirPredictionF,
output logic DirPredictionWrongE, output logic DirPredictionWrongE,
// update // update
input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW,
input logic PCSrcE input logic PCSrcE
); );
logic MatchF, MatchD, MatchE, MatchM, MatchW; logic MatchF, MatchD, MatchE, MatchM, MatchW;
logic MatchNextX, MatchXF; logic MatchNextX, MatchXF;

28
pipelined/src/ifu/bpred/speculativegshare.sv
View File

@ -28,22 +28,20 @@
`include "wally-config.vh" `include "wally-config.vh"
module speculativegshare module speculativegshare #(parameter k = 10) (
#(parameter int k = 10 input logic clk,
) input logic reset,
(input logic clk, input logic StallF, StallD, StallE, StallM, StallW,
input logic reset, input logic FlushD, FlushE, FlushM, FlushW,
input logic StallF, StallD, StallE, StallM, StallW,
input logic FlushD, FlushE, FlushM, FlushW,
// input logic [`XLEN-1:0] LookUpPC, // input logic [`XLEN-1:0] LookUpPC,
output logic [1:0] DirPredictionF, output logic [1:0] DirPredictionF,
output logic DirPredictionWrongE, output logic DirPredictionWrongE,
// update // update
input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW,
input logic [3:0] WrongPredInstrClassD, input logic [3:0] WrongPredInstrClassD,
input logic PCSrcE input logic PCSrcE
); );
logic MatchF, MatchD, MatchE, MatchM; logic MatchF, MatchD, MatchE, MatchM;
logic MatchNextX, MatchXF; logic MatchNextX, MatchXF;

24
pipelined/src/ifu/bpred/twoBitPredictor.sv
View File

@ -28,19 +28,17 @@
`include "wally-config.vh" `include "wally-config.vh"
module twoBitPredictor module twoBitPredictor #(parameter k = 10) (
#(parameter int k = 10 input logic clk,
) input logic reset,
(input logic clk, input logic StallF, StallD, StallE, StallM,
input logic reset, input logic FlushD, FlushE, FlushM,
input logic StallF, StallD, StallE, StallM, input logic [`XLEN-1:0] PCNextF, PCM,
input logic FlushD, FlushE, FlushM, output logic [1:0] DirPredictionF,
input logic [`XLEN-1:0] PCNextF, PCM, output logic DirPredictionWrongE,
output logic [1:0] DirPredictionF, input logic BranchInstrE, BranchInstrM,
output logic DirPredictionWrongE, input logic PCSrcE
input logic BranchInstrE, BranchInstrM, );
input logic PCSrcE
);
logic [k-1:0] IndexNextF, IndexM; logic [k-1:0] IndexNextF, IndexM;
logic [1:0] PredictionMemory; logic [1:0] PredictionMemory;