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Removed int/integer from parameters)

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This commit is contained in:
David Harris 2023-01-27 14:27:04 -08:00
parent 44c7102026
commit 717cb4e6c5
12 changed files with 128 additions and 150 deletions
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8
pipelined/src/ebu/ahbcacheinterface.sv
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@ -30,10 +30,10 @@
`include "wally-config.vh" `include "wally-config.vh"
module ahbcacheinterface #( module ahbcacheinterface #(
parameter integer BEATSPERLINE, // Number of AHBW words (beats) in cacheline parameter BEATSPERLINE, // Number of AHBW words (beats) in cacheline
parameter integer AHBWLOGBWPL, // Log2 of ^ parameter AHBWLOGBWPL, // Log2 of ^
parameter integer LINELEN, // Number of bits in cacheline parameter LINELEN, // Number of bits in cacheline
parameter integer LLENPOVERAHBW // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation) parameter LLENPOVERAHBW // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
)( )(
input logic HCLK, HRESETn, input logic HCLK, HRESETn,
// bus interface controls // bus interface controls

4
pipelined/src/ebu/buscachefsm.sv
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@ -32,8 +32,8 @@
// HCLK and clk must be the same clock! // HCLK and clk must be the same clock!
module buscachefsm #( module buscachefsm #(
parameter integer BeatCountThreshold, // Largest beat index parameter BeatCountThreshold, // Largest beat index
parameter integer AHBWLOGBWPL // Log2 of BEATSPERLINE parameter AHBWLOGBWPL // Log2 of BEATSPERLINE
)( )(
input logic HCLK, input logic HCLK,
input logic HRESETn, input logic HRESETn,

8
pipelined/src/ifu/bpred/RAsPredictor.sv
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@ -28,10 +28,8 @@
`include "wally-config.vh" `include "wally-config.vh"
module RASPredictor module RASPredictor #(parameter StackSize = 16) (
#(parameter int StackSize = 16 input logic clk,
)
(input logic clk,
input logic reset, input logic reset,
input logic PopF, input logic PopF,
output logic [`XLEN-1:0] RASPCF, output logic [`XLEN-1:0] RASPCF,
@ -40,7 +38,7 @@ module RASPredictor
input logic PushE, input logic PushE,
input logic incr, input logic incr,
input logic [`XLEN-1:0] PCLinkE input logic [`XLEN-1:0] PCLinkE
); );
// *** need to update so it either doesn't push until the memory stage // *** need to update so it either doesn't push until the memory stage
// or need to repair flushed push. // or need to repair flushed push.

8
pipelined/src/ifu/bpred/btb.sv
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@ -30,10 +30,8 @@
`include "wally-config.vh" `include "wally-config.vh"
module btb module btb #(parameter Depth = 10) (
#(parameter int Depth = 10 input logic clk,
)
(input logic clk,
input logic reset, input logic reset,
input logic StallF, StallE, input logic StallF, StallE,
input logic [`XLEN-1:0] PCNextF, input logic [`XLEN-1:0] PCNextF,
@ -46,7 +44,7 @@ module btb
input logic [`XLEN-1:0] IEUAdrE, input logic [`XLEN-1:0] IEUAdrE,
input logic [3:0] InstrClassE, input logic [3:0] InstrClassE,
input logic UpdateInvalid input logic UpdateInvalid
); );
localparam TotalDepth = 2 ** Depth; localparam TotalDepth = 2 ** Depth;
logic [TotalDepth-1:0] ValidBits; logic [TotalDepth-1:0] ValidBits;

9
pipelined/src/ifu/bpred/foldedgshare.sv
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@ -28,11 +28,8 @@
`include "wally-config.vh" `include "wally-config.vh"
module foldedgshare module foldedgshare #(parameter k = 16, depth = 10) (
#(parameter int k = 16, input logic clk,
parameter int depth = 10
)
(input logic clk,
input logic reset, input logic reset,
input logic StallF, StallD, StallE, StallM, StallW, input logic StallF, StallD, StallE, StallM, StallW,
input logic FlushD, FlushE, FlushM, FlushW, input logic FlushD, FlushE, FlushM, FlushW,
@ -43,7 +40,7 @@ module foldedgshare
input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW,
input logic PCSrcE input logic PCSrcE
); );
logic MatchF, MatchD, MatchE, MatchM, MatchW; logic MatchF, MatchD, MatchE, MatchM, MatchW;
logic MatchNextX, MatchXF; logic MatchNextX, MatchXF;

10
pipelined/src/ifu/bpred/globalhistory.sv
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@ -28,20 +28,18 @@
`include "wally-config.vh" `include "wally-config.vh"
module globalhistory module globalhistory #(parameter k = 10) (
#(parameter int k = 10 input logic clk,
)
(input logic clk,
input logic reset, input logic reset,
input logic StallF, StallD, StallE, StallM, input logic StallF, StallD, StallE, StallM,
input logic FlushD, FlushE, FlushM, input logic FlushD, FlushE, FlushM,
// input logic [`XLEN-1:0] LookUpPC, // input logic [`XLEN-1:0] LookUpPC,
output logic [1:0] DirPredictionF, output logic [1:0] DirPredictionF,
output logic DirPredictionWrongE, output logic DirPredictionWrongE,
// update // update
input logic [`XLEN-1:0] PCNextF, PCM, input logic [`XLEN-1:0] PCNextF, PCM,
input logic BranchInstrE, BranchInstrM, PCSrcE input logic BranchInstrE, BranchInstrM, PCSrcE
); );
logic [1:0] DirPredictionD, DirPredictionE; logic [1:0] DirPredictionD, DirPredictionE;
logic [1:0] NewDirPredictionE, NewDirPredictionM; logic [1:0] NewDirPredictionE, NewDirPredictionM;

8
pipelined/src/ifu/bpred/gshare.sv
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@ -28,10 +28,8 @@
`include "wally-config.vh" `include "wally-config.vh"
module gshare module gshare #(parameter k = 10) (
#(parameter int k = 10 input logic clk,
)
(input logic clk,
input logic reset, input logic reset,
input logic StallF, StallD, StallE, StallM, input logic StallF, StallD, StallE, StallM,
input logic FlushD, FlushE, FlushM, input logic FlushD, FlushE, FlushM,
@ -41,7 +39,7 @@ module gshare
// update // update
input logic [`XLEN-1:0] PCNextF, PCM, input logic [`XLEN-1:0] PCNextF, PCM,
input logic BranchInstrE, BranchInstrM, PCSrcE input logic BranchInstrE, BranchInstrM, PCSrcE
); );
logic [k-1:0] IndexNextF, IndexM; logic [k-1:0] IndexNextF, IndexM;
logic [1:0] DirPredictionD, DirPredictionE; logic [1:0] DirPredictionD, DirPredictionE;

13
pipelined/src/ifu/bpred/localHistoryPredictor.sv
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@ -28,11 +28,9 @@
`include "wally-config.vh" `include "wally-config.vh"
module localHistoryPredictor module localHistoryPredictor #(parameter m = 6, // 2^m = number of local history branches
#( parameter int m = 6, // 2^m = number of local history branches k = 10) ( // number of past branches stored
parameter int k = 10 // number of past branches stored input logic clk,
)
(input logic clk,
input logic reset, input logic reset,
input logic StallF, StallE, input logic StallF, StallE,
input logic [`XLEN-1:0] LookUpPC, input logic [`XLEN-1:0] LookUpPC,
@ -41,10 +39,9 @@ module localHistoryPredictor
input logic [`XLEN-1:0] UpdatePC, input logic [`XLEN-1:0] UpdatePC,
input logic UpdateEN, PCSrcE, input logic UpdateEN, PCSrcE,
input logic [1:0] UpdatePrediction input logic [1:0] UpdatePrediction
);
); logic [2**m-1:0][k-1:0] LHRNextF;
logic [2**m-1:0] [k-1:0] LHRNextF;
logic [k-1:0] LHRF, ForwardLHRNext, LHRFNext; logic [k-1:0] LHRF, ForwardLHRNext, LHRFNext;
logic [m-1:0] LookUpPCIndex, UpdatePCIndex; logic [m-1:0] LookUpPCIndex, UpdatePCIndex;
logic [1:0] PredictionMemory; logic [1:0] PredictionMemory;

8
pipelined/src/ifu/bpred/optgshare.sv
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@ -28,10 +28,8 @@
`include "wally-config.vh" `include "wally-config.vh"
module optgshare module optgshare #(parameter k = 10) (
#(parameter int k = 10 input logic clk,
)
(input logic clk,
input logic reset, input logic reset,
input logic StallF, StallD, StallE, StallM, StallW, input logic StallF, StallD, StallE, StallM, StallW,
input logic FlushD, FlushE, FlushM, FlushW, input logic FlushD, FlushE, FlushM, FlushW,
@ -42,7 +40,7 @@ module optgshare
input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW,
input logic PCSrcE input logic PCSrcE
); );
logic MatchF, MatchD, MatchE, MatchM, MatchW; logic MatchF, MatchD, MatchE, MatchM, MatchW;
logic MatchNextX, MatchXF; logic MatchNextX, MatchXF;

8
pipelined/src/ifu/bpred/speculativeglobalhistory.sv
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@ -28,10 +28,8 @@
`include "wally-config.vh" `include "wally-config.vh"
module speculativeglobalhistory module speculativeglobalhistory #(parameter k = 10) (
#(parameter int k = 10 input logic clk,
)
(input logic clk,
input logic reset, input logic reset,
input logic StallF, StallD, StallE, StallM, StallW, input logic StallF, StallD, StallE, StallM, StallW,
input logic FlushD, FlushE, FlushM, FlushW, input logic FlushD, FlushE, FlushM, FlushW,
@ -42,7 +40,7 @@ module speculativeglobalhistory
input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW,
input logic PCSrcE input logic PCSrcE
); );
logic MatchF, MatchD, MatchE, MatchM, MatchW; logic MatchF, MatchD, MatchE, MatchM, MatchW;
logic MatchNextX, MatchXF; logic MatchNextX, MatchXF;

8
pipelined/src/ifu/bpred/speculativegshare.sv
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@ -28,10 +28,8 @@
`include "wally-config.vh" `include "wally-config.vh"
module speculativegshare module speculativegshare #(parameter k = 10) (
#(parameter int k = 10 input logic clk,
)
(input logic clk,
input logic reset, input logic reset,
input logic StallF, StallD, StallE, StallM, StallW, input logic StallF, StallD, StallE, StallM, StallW,
input logic FlushD, FlushE, FlushM, FlushW, input logic FlushD, FlushE, FlushM, FlushW,
@ -43,7 +41,7 @@ module speculativegshare
input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW,
input logic [3:0] WrongPredInstrClassD, input logic [3:0] WrongPredInstrClassD,
input logic PCSrcE input logic PCSrcE
); );
logic MatchF, MatchD, MatchE, MatchM; logic MatchF, MatchD, MatchE, MatchM;
logic MatchNextX, MatchXF; logic MatchNextX, MatchXF;

8
pipelined/src/ifu/bpred/twoBitPredictor.sv
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@ -28,10 +28,8 @@
`include "wally-config.vh" `include "wally-config.vh"
module twoBitPredictor module twoBitPredictor #(parameter k = 10) (
#(parameter int k = 10 input logic clk,
)
(input logic clk,
input logic reset, input logic reset,
input logic StallF, StallD, StallE, StallM, input logic StallF, StallD, StallE, StallM,
input logic FlushD, FlushE, FlushM, input logic FlushD, FlushE, FlushM,
@ -40,7 +38,7 @@ module twoBitPredictor
output logic DirPredictionWrongE, output logic DirPredictionWrongE,
input logic BranchInstrE, BranchInstrM, input logic BranchInstrE, BranchInstrM,
input logic PCSrcE input logic PCSrcE
); );
logic [k-1:0] IndexNextF, IndexM; logic [k-1:0] IndexNextF, IndexM;
logic [1:0] PredictionMemory; logic [1:0] PredictionMemory;