mirror of
https://github.com/openhwgroup/cvw
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Merge pull request #609 from ross144/main
Numerous coverage improvements and testbench fix
This commit is contained in:
David Harris
GitHub
commit
71288879a0
@ -48,29 +48,14 @@ IP_Arty: $(dst)/xlnx_proc_sys_reset.log \
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PreProcessFiles:
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$(MAKE) -C ../../sim deriv
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rm -rf ../src/CopiedFiles_do_not_add_to_repo/
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cp -r ../../src/ ../src/CopiedFiles_do_not_add_to_repo/
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mkdir ../src/CopiedFiles_do_not_add_to_repo/config/
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cp ../../config/rv64gc/config.vh ../src/CopiedFiles_do_not_add_to_repo/config/
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cp ../../config/deriv/fpga/config.vh ../src/CopiedFiles_do_not_add_to_repo/config/
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./insert_debug_comment.sh
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# modify config *** RT: eventually setup for variably defined sized memory
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sed -i "s/ZICCLSM_SUPPORTED.*/ZICCLSM_SUPPORTED = 1;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
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sed -i "s/RESET_VECTOR.*/RESET_VECTOR = 64'h0000000000001000;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
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sed -i "s/BOOTROM_PRELOAD.*/BOOTROM_PRELOAD = 1'b1;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
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sed -i "s/UNCORE_RAM_BASE.*/UNCORE_RAM_BASE = 64'h00002000;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
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sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE = 64'h00000FFF;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
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sed -i "s/UNCORE_RAM_PRELOAD.*/UNCORE_RAM_PRELOAD = 1'b1;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
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sed -i "s/EXT_MEM_SUPPORTED.*/EXT_MEM_SUPPORTED = 1'b1;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
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sed -i "s/EXT_MEM_RANGE.*/EXT_MEM_RANGE = 64'h0FFFFFFF;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
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sed -i "s/SDC_SUPPORTED.*/SDC_SUPPORTED = 1'b1;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
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sed -i "s/SPI_SUPPORTED.*/SPI_SUPPORTED = 1'b0;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh # *** RT: Add SPI when ready
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sed -i "s/GPIO_LOOPBACK_TEST.*/GPIO_LOOPBACK_TEST = 0;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
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sed -i "s/SPI_LOOPBACK_TEST.*/SPI_LOOPBACK_TEST = 0;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
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sed -i "s/UART_PRESCALE.*/UART_PRESCALE = 32'd0;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
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sed -i "s/PLIC_NUM_SRC = .*/PLIC_NUM_SRC = 32'd53;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
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sed -i "s/PLIC_SDC_ID.*/PLIC_SDC_ID = 32'd20;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
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sed -i "s/BPRED_SIZE.*/BPRED_SIZE = 32'd12;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
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sed -i "s/$\$readmemh.*/$\$readmemh(\"..\/..\/..\/fpga\/src\/boot.mem\", ROM, 0);/g" ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv
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#sed -i "s/EXT_MEM_RANGE.*/EXT_MEM_RANGE = 64'h0FFFFFFF;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
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# This line allows the Bootloader to be loaded in a Block RAM on the FPGA
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sed -i "s/logic \[DATA_WIDTH-1:0\].*ROM.*/(\* rom_style=\"block\" \*) &/g" ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv
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@ -308,6 +308,48 @@ coverage exclude -scope /dut/core/ebu/ebu/ebufsmarb -linerange $line-$line -item
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set line [GetLineNum ../src/ebu/ebufsmarb.sv "FinalBeatReg\\("]
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coverage exclude -scope /dut/core/ebu/ebu/ebufsmarb -linerange $line-$line -item e 1 -fecexprrow 1
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set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm Atomic"]
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coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item bc 1
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set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicWait"]
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coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item bc 1
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# The WritebackWriteback and FetchWriteback support back to back pipelined cache writebacks and fetch then
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# writebacks. The cache never issues these type of requests.
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set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm WritebackWriteback"]
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coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item bc 2
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set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWriteback"]
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coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item bc 2
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# FetchWait never occurs because HREADY is never 0.
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set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWait"]
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coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item bc 1
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# all of these HEADY exclusions occur because HREADY is always 1. The ram_ahb module never stalls.
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set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY0"]
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coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1
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set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY1"]
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coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1
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set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY2"]
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coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1
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set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY3"]
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coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 4
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set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY4"]
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coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1
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coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 3
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set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY5"]
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coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1
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set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY6"]
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coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1
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coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 5
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# TLB not recently used never has all RU bits = 1 because it will then clear all to 0
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# This is a blunt instrument; perhaps there is a more graceful exclusion
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coverage exclude -srcfile priorityonehot.sv
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@ -87,27 +87,27 @@ module buscachefsm #(
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always_comb begin
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case(CurrState)
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ADR_PHASE: if (HREADY & |BusRW) NextState = DATA_PHASE;
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else if (HREADY & BusWrite) NextState = CACHE_WRITEBACK;
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ADR_PHASE: if (HREADY & |BusRW) NextState = DATA_PHASE; // exclusion-tag: buscachefsm HREADY0
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else if (HREADY & BusWrite) NextState = CACHE_WRITEBACK; // exclusion-tag: buscachefsm HREADY1
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else if (HREADY & CacheBusRW[1]) NextState = CACHE_FETCH;
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else NextState = ADR_PHASE;
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DATA_PHASE: if(HREADY & BusAtomic) NextState = ATOMIC_READ_DATA_PHASE;
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else if(HREADY & ~BusAtomic) NextState = MEM3;
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DATA_PHASE: if(HREADY & BusAtomic) NextState = ATOMIC_READ_DATA_PHASE; // exclusion-tag: buscachefsm HREADY2
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else if(HREADY & ~BusAtomic) NextState = MEM3; // exclusion-tag: buscachefsm HREADY3
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else NextState = DATA_PHASE;
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ATOMIC_READ_DATA_PHASE: if(HREADY) NextState = ATOMIC_PHASE;
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else NextState = ATOMIC_READ_DATA_PHASE;
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else NextState = ATOMIC_READ_DATA_PHASE; // exclusion-tag: buscachefsm Atomic
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ATOMIC_PHASE: if(HREADY) NextState = MEM3;
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else NextState = ATOMIC_PHASE;
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else NextState = ATOMIC_PHASE; // exclusion-tag: buscachefsm AtomicWait
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MEM3: if(Stall) NextState = MEM3;
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else NextState = ADR_PHASE;
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CACHE_FETCH: if(HREADY & FinalBeatCount & CacheBusRW[0]) NextState = CACHE_WRITEBACK;
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else if(HREADY & FinalBeatCount & CacheBusRW[1]) NextState = CACHE_FETCH;
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CACHE_FETCH: if(HREADY & FinalBeatCount & CacheBusRW[0]) NextState = CACHE_WRITEBACK; // exclusion-tag: buscachefsm FetchWriteback
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else if(HREADY & FinalBeatCount & CacheBusRW[1]) NextState = CACHE_FETCH; // exclusion-tag: buscachefsm FetchWait
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else if(HREADY & FinalBeatCount & ~|CacheBusRW) NextState = ADR_PHASE;
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else NextState = CACHE_FETCH;
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CACHE_WRITEBACK: if(HREADY & FinalBeatCount & CacheBusRW[0]) NextState = CACHE_WRITEBACK;
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else if(HREADY & FinalBeatCount & CacheBusRW[1]) NextState = CACHE_FETCH;
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else if(HREADY & FinalBeatCount & BusCMOZero) NextState = MEM3;
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else if(HREADY & FinalBeatCount & ~|CacheBusRW) NextState = ADR_PHASE;
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CACHE_WRITEBACK: if(HREADY & FinalBeatCount & CacheBusRW[0]) NextState = CACHE_WRITEBACK; // exclusion-tag: buscachefsm WritebackWriteback
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else if(HREADY & FinalBeatCount & CacheBusRW[1]) NextState = CACHE_FETCH; // exclusion-tag: buscachefsm HREADY4
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else if(HREADY & FinalBeatCount & BusCMOZero) NextState = MEM3; // exclusion-tag: buscachefsm HREADY5
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else if(HREADY & FinalBeatCount & ~|CacheBusRW) NextState = ADR_PHASE; // exclusion-tag: buscachefsm HREADY6
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else NextState = CACHE_WRITEBACK;
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default: NextState = ADR_PHASE;
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endcase
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@ -42,6 +42,7 @@ module controller import cvw::*; #(parameter cvw_t P) (
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output logic BranchD, // Branch instruction
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output logic StructuralStallD, // Structural stalls detected by controller
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output logic LoadStallD, // Structural stalls for load, sent to performance counters
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output logic StoreStallD, // load after store hazard
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output logic [4:0] Rs1D, Rs2D, // Register sources to read in Decode or Execute stage
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// Execute stage control signals
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input logic StallE, FlushE, // Stall, flush Execute stage
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@ -159,7 +160,6 @@ module controller import cvw::*; #(parameter cvw_t P) (
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logic CMOStallD; // Structural hazards from cache management ops
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logic MatchDE; // Match between a source register in Decode stage and destination register in Execute stage
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logic FCvtIntStallD, MDUStallD, CSRRdStallD; // Stall due to conversion, load, multiply/divide, CSR read
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logic StoreStallD; // load after store hazard
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logic FunctCZeroD; // Funct7 and Funct3 indicate czero.* (not including Op check)
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// Extract fields
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@ -76,6 +76,7 @@ module ieu import cvw::*; #(parameter cvw_t P) (
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input logic FlushD, FlushE, FlushM, FlushW, // Flush signals
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output logic StructuralStallD, // IEU detects structural hazard in Decode stage
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output logic LoadStallD, // Structural stalls for load, sent to performance counters
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output logic StoreStallD, // load after store hazard
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output logic CSRReadM, CSRWriteM, PrivilegedM,// CSR read, CSR write, is privileged instruction
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output logic CSRWriteFenceM // CSR write or fence instruction needs to flush subsequent instructions
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);
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@ -107,7 +108,7 @@ module ieu import cvw::*; #(parameter cvw_t P) (
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controller #(P) c(
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.clk, .reset, .StallD, .FlushD, .InstrD, .STATUS_FS, .ENVCFG_CBE, .ImmSrcD,
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.IllegalIEUFPUInstrD, .IllegalBaseInstrD,
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.StructuralStallD, .LoadStallD, .Rs1D, .Rs2D,
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.StructuralStallD, .LoadStallD, .StoreStallD, .Rs1D, .Rs2D,
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.StallE, .FlushE, .FlagsE, .FWriteIntE,
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.PCSrcE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .MemReadE, .CSRReadE,
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.Funct3E, .IntDivE, .MDUE, .W64E, .SubArithE, .BranchD, .BranchE, .JumpD, .JumpE, .SCE,
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@ -374,12 +374,12 @@ module lsu import cvw::*; #(parameter cvw_t P) (
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ahbinterface #(P.XLEN, 1'b1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .Flush(FlushW), .HREADY(LSUHREADY),
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.HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA),
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.HWSTRB(LSUHWSTRB), .BusRW, .BusAtomic(AtomicM[1]), .ByteMask(ByteMaskM), .WriteData(LSUWriteDataM[P.XLEN-1:0]),
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.HWSTRB(LSUHWSTRB), .BusRW, .BusAtomic(AtomicM[1]), .ByteMask(ByteMaskM[P.XLEN/8-1:0]), .WriteData(LSUWriteDataM[P.XLEN-1:0]),
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.Stall(GatedStallW), .BusStall, .BusCommitted(BusCommittedM), .FetchBuffer(FetchBuffer));
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// Mux between the 2 sources of read data, 0: Bus, 1: DTIM
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if(P.DTIM_SUPPORTED) mux2 #(P.XLEN) ReadDataMux2(FetchBuffer, DTIMReadDataWordM[P.XLEN-1:0], SelDTIM, ReadDataWordMuxM[P.XLEN-1:0]);
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else assign ReadDataWordMuxM = FetchBuffer[P.XLEN-1:0];
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else assign ReadDataWordMuxM[P.XLEN-1:0] = FetchBuffer[P.XLEN-1:0]; // *** bus only does not support double wide floats.
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assign LSUHBURST = 3'b0;
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assign {DCacheStallM, DCacheCommittedM, DCacheMiss, DCacheAccess} = '0;
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end
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@ -54,7 +54,7 @@ module csr import cvw::*; #(parameter cvw_t P) (
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input logic [3:0] CauseM, // Trap cause
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input logic SelHPTW, // hardware page table walker active, so base endianness on supervisor mode
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// inputs for performance counters
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input logic LoadStallD,
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input logic LoadStallD, StoreStallD,
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input logic ICacheStallF,
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input logic DCacheStallM,
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input logic BPDirPredWrongM,
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@ -275,7 +275,7 @@ module csr import cvw::*; #(parameter cvw_t P) (
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if (P.ZICNTR_SUPPORTED) begin:counters
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csrc #(P) counters(.clk, .reset, .StallE, .StallM, .FlushM,
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.InstrValidNotFlushedM, .LoadStallD, .CSRWriteM, .CSRMWriteM,
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.InstrValidNotFlushedM, .LoadStallD, .StoreStallD, .CSRWriteM, .CSRMWriteM,
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.BPDirPredWrongM, .BTAWrongM, .RASPredPCWrongM, .IClassWrongM, .BPWrongM,
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.InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .sfencevmaM,
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.InterruptM, .ExceptionM, .InvalidateICacheM, .ICacheStallF, .DCacheStallM, .DivBusyE, .FDivBusyE,
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@ -33,7 +33,7 @@ module csrc import cvw::*; #(parameter cvw_t P) (
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input logic clk, reset,
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input logic StallE, StallM,
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input logic FlushM,
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input logic InstrValidNotFlushedM, LoadStallD,
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input logic InstrValidNotFlushedM, LoadStallD, StoreStallD,
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input logic CSRMWriteM, CSRWriteM,
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input logic BPDirPredWrongM,
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input logic BTAWrongM,
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@ -76,6 +76,7 @@ module csrc import cvw::*; #(parameter cvw_t P) (
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logic [P.XLEN-1:0] HPMCOUNTER_REGW[P.COUNTERS-1:0];
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logic [P.XLEN-1:0] HPMCOUNTERH_REGW[P.COUNTERS-1:0];
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logic LoadStallE, LoadStallM;
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logic StoreStallE, StoreStallM;
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logic [P.COUNTERS-1:0] WriteHPMCOUNTERM;
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logic [P.COUNTERS-1:0] CounterEvent;
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logic [63:0] HPMCOUNTERPlusM[P.COUNTERS-1:0];
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@ -86,6 +87,9 @@ module csrc import cvw::*; #(parameter cvw_t P) (
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flopenrc #(1) LoadStallEReg(.clk, .reset, .clear(1'b0), .en(~StallE), .d(LoadStallD), .q(LoadStallE)); // don't flush the load stall during a load stall.
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flopenrc #(1) LoadStallMReg(.clk, .reset, .clear(FlushM), .en(~StallM), .d(LoadStallE), .q(LoadStallM));
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flopenrc #(1) StoreStallEReg(.clk, .reset, .clear(1'b0), .en(~StallE), .d(StoreStallD), .q(StoreStallE)); // don't flush the load stall during a load stall.
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flopenrc #(1) StoreStallMReg(.clk, .reset, .clear(FlushM), .en(~StallM), .d(StoreStallE), .q(StoreStallM));
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// Determine when to increment each counter
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assign CounterEvent[0] = 1'b1; // MCYCLE always increments
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assign CounterEvent[1] = 1'b0; // Counter 1 doesn't exist
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@ -100,7 +104,7 @@ module csrc import cvw::*; #(parameter cvw_t P) (
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assign CounterEvent[9] = RASPredPCWrongM & InstrValidNotFlushedM; // return address stack wrong address
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assign CounterEvent[10] = IClassWrongM & InstrValidNotFlushedM; // instruction class predictor wrong
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assign CounterEvent[11] = LoadStallM; // Load Stalls. don't want to suppress on flush as this only happens if flushed.
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assign CounterEvent[12] = 0; // depricated Store Stall
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assign CounterEvent[12] = StoreStallM; // depricated Store Stall
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assign CounterEvent[13] = DCacheAccess; // data cache access
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assign CounterEvent[14] = DCacheMiss; // data cache miss. Miss asserted 1 cycle at start of cache miss
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assign CounterEvent[15] = DCacheStallM; // d cache miss cycles
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@ -46,6 +46,7 @@ module privileged import cvw::*; #(parameter cvw_t P) (
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// processor events for performance counter logging
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input logic FRegWriteM, // instruction will write floating-point registers
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input logic LoadStallD, // load instruction is stalling
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input logic StoreStallD, // store instruction is stalling
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input logic ICacheStallF, // I cache stalled
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input logic DCacheStallM, // D cache stalled
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input logic BPDirPredWrongM, // branch predictor guessed wrong direction
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@ -135,7 +136,7 @@ module privileged import cvw::*; #(parameter cvw_t P) (
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.InstrM, .InstrOrigM, .PCM, .SrcAM, .IEUAdrM,
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.CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .InterruptM,
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.MTimerInt, .MExtInt, .SExtInt, .MSwInt,
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.MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD,
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.MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, .StoreStallD,
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.BPDirPredWrongM, .BTAWrongM, .RASPredPCWrongM, .BPWrongM,
|
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.sfencevmaM, .ExceptionM, .InvalidateICacheM, .ICacheStallF, .DCacheStallM, .DivBusyE, .FDivBusyE,
|
||||
.IClassWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
|
||||
|
||||
@ -78,6 +78,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
|
||||
logic DivBusyE;
|
||||
logic StructuralStallD;
|
||||
logic LoadStallD;
|
||||
logic StoreStallD;
|
||||
logic SquashSCW;
|
||||
logic MDUActiveE; // Mul/Div instruction being executed
|
||||
logic ENVCFG_ADUE; // HPTW A/D Update enable
|
||||
@ -212,7 +213,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
|
||||
.InstrValidM, .InstrValidE, .InstrValidD, .FCvtIntResW, .FCvtIntW,
|
||||
// hazards
|
||||
.StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
|
||||
.StructuralStallD, .LoadStallD, .PCSrcE,
|
||||
.StructuralStallD, .LoadStallD, .StoreStallD, .PCSrcE,
|
||||
.CSRReadM, .CSRWriteM, .PrivilegedM, .CSRWriteFenceM, .InvalidateICacheM);
|
||||
|
||||
lsu #(P) lsu(
|
||||
@ -286,7 +287,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
|
||||
.InstrM, .InstrOrigM, .CSRReadValW, .EPCM, .TrapVectorM,
|
||||
.RetM, .TrapM, .sfencevmaM, .InvalidateICacheM, .DCacheStallM, .ICacheStallF,
|
||||
.InstrValidM, .CommittedM, .CommittedF,
|
||||
.FRegWriteM, .LoadStallD,
|
||||
.FRegWriteM, .LoadStallD, .StoreStallD,
|
||||
.BPDirPredWrongM, .BTAWrongM, .BPWrongM,
|
||||
.RASPredPCWrongM, .IClassWrongM, .DivBusyE, .FDivBusyE,
|
||||
.InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM,
|
||||
|
||||
@ -326,14 +326,13 @@ module testbench;
|
||||
end else begin
|
||||
// for tests with no self checking mechanism, read .signature.output file and compare to check for errors
|
||||
// clear signature to prevent contamination from previous tests
|
||||
if (!begin_signature_addr)
|
||||
$display("begin_signature addr not found in %s", ProgramLabelMapFile);
|
||||
else if (TEST != "embench") begin // *** quick hack for embench. need a better long term solution
|
||||
CheckSignature(pathname, tests[test], riscofTest, begin_signature_addr, errors);
|
||||
if(errors > 0) totalerrors = totalerrors + 1;
|
||||
end
|
||||
end
|
||||
|
||||
if (!begin_signature_addr)
|
||||
$display("begin_signature addr not found in %s", ProgramLabelMapFile);
|
||||
else if (TEST != "embench") begin // *** quick hack for embench. need a better long term solution
|
||||
CheckSignature(pathname, tests[test], riscofTest, begin_signature_addr, errors);
|
||||
end
|
||||
if(errors > 0) totalerrors = totalerrors + 1;
|
||||
test = test + 1; // *** this probably needs to be moved.
|
||||
if (test == tests.size()) begin
|
||||
if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");
|
||||
|
||||
@ -19,7 +19,7 @@ all: $(OBJECTS)
|
||||
%.elf: $(SRCDIR)/%.$(SEXT) WALLY-init-lib.h Makefile
|
||||
riscv64-unknown-elf-gcc -g -o $@ -march=rv64gqc_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom -mabi=lp64 -mcmodel=medany \
|
||||
-nostartfiles -T../../examples/link/link.ld $<
|
||||
riscv64-unknown-elf-objdump -S $@ > $@.objdump
|
||||
riscv64-unknown-elf-objdump -S -D $@ > $@.objdump
|
||||
riscv64-unknown-elf-elf2hex --bit-width 64 --input $@ --output $@.memfile
|
||||
extractFunctionRadix.sh $@.objdump
|
||||
|
||||
|
||||
@ -96,6 +96,49 @@ main:
|
||||
sw t1, 0(t0) # write to page
|
||||
jalr ra, t0 # jump to page
|
||||
|
||||
# AMO at page has PBMT = 2 or 1 (uncached)
|
||||
li t0, 0x80401000
|
||||
li t1, 10
|
||||
amoadd.w t1, t1, (t0)
|
||||
|
||||
la t2, SpecialPage
|
||||
li t0, 0x200000000 # an address to a specific 1 GiB page
|
||||
j ConcurrentICacheMissDTLBMiss
|
||||
|
||||
.align 6
|
||||
ConcurrentICacheMissDTLBMiss:
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
lw t1, 0(t0)
|
||||
|
||||
# write a cacheline length (512 bits) to memory in uncached region
|
||||
li t0, 0x80401000
|
||||
cbo.zero (t0)
|
||||
|
||||
# Nonleaf PTE has PBMT != 0 causes a page fault during page walking. H
|
||||
li t0, 0x80600000
|
||||
lw t1, 0(t0) # read from page
|
||||
@ -294,6 +337,12 @@ pagetable:
|
||||
.8byte 0x00000000200058C1 # PTE for pages at 0x40000000 pointing to 0x80150000
|
||||
.8byte 0x00000000200048C1 # gigapage at 0x80000000 pointing to 0x80120000
|
||||
.8byte 0x00000000000000C1 # gigapage at VA 0xC0000000 causes access fault
|
||||
.8byte 0x0
|
||||
.8byte 0x0
|
||||
.8byte 0x0
|
||||
.8byte 0x0
|
||||
SpecialPage:
|
||||
.8byte 0x00000000200000CF # 0x2_0000_0000 1GiB page1
|
||||
|
||||
|
||||
# Next page table at 0x80012000 for gigapage at 0x80000000
|
||||
@ -409,6 +458,7 @@ pagetable:
|
||||
.align 12
|
||||
#80400000
|
||||
.8byte 0x60000000200020CF # reserved entry
|
||||
.8byte 0x40000000201000CF # non-cache non-idempotent
|
||||
|
||||
# Leaf page table at 0x80015000 with various permissions for testing CBOM and CBOZ
|
||||
.align 12
|
||||
|
||||
Loading…
Reference in New Issue
Block a user