Merge pull request #609 from ross144/main

Numerous coverage improvements and testbench fix

fpga/generator/Makefile

@@ -48,29 +48,14 @@ IP_Arty: $(dst)/xlnx_proc_sys_reset.log \
 
 
 PreProcessFiles:
+	$(MAKE) -C ../../sim deriv
 	rm -rf ../src/CopiedFiles_do_not_add_to_repo/
 	cp -r ../../src/ ../src/CopiedFiles_do_not_add_to_repo/
 	mkdir ../src/CopiedFiles_do_not_add_to_repo/config/
-	cp ../../config/rv64gc/config.vh ../src/CopiedFiles_do_not_add_to_repo/config/
+	cp ../../config/deriv/fpga/config.vh ../src/CopiedFiles_do_not_add_to_repo/config/
 	./insert_debug_comment.sh
 	# modify config  *** RT: eventually setup for variably defined sized memory
-	sed -i "s/ZICCLSM_SUPPORTED.*/ZICCLSM_SUPPORTED = 1;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
+	#sed -i "s/EXT_MEM_RANGE.*/EXT_MEM_RANGE = 64'h0FFFFFFF;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
-	sed -i "s/RESET_VECTOR.*/RESET_VECTOR = 64'h0000000000001000;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
-	sed -i "s/BOOTROM_PRELOAD.*/BOOTROM_PRELOAD = 1'b1;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
-	sed -i "s/UNCORE_RAM_BASE.*/UNCORE_RAM_BASE = 64'h00002000;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
-	sed -i "s/UNCORE_RAM_RANGE.*/UNCORE_RAM_RANGE = 64'h00000FFF;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
-	sed -i "s/UNCORE_RAM_PRELOAD.*/UNCORE_RAM_PRELOAD = 1'b1;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
-	sed -i "s/EXT_MEM_SUPPORTED.*/EXT_MEM_SUPPORTED = 1'b1;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
-	sed -i "s/EXT_MEM_RANGE.*/EXT_MEM_RANGE = 64'h0FFFFFFF;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
-	sed -i "s/SDC_SUPPORTED.*/SDC_SUPPORTED = 1'b1;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
-	sed -i "s/SPI_SUPPORTED.*/SPI_SUPPORTED = 1'b0;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh   # *** RT: Add SPI when ready
-	sed -i "s/GPIO_LOOPBACK_TEST.*/GPIO_LOOPBACK_TEST = 0;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
-	sed -i "s/SPI_LOOPBACK_TEST.*/SPI_LOOPBACK_TEST = 0;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
-	sed -i "s/UART_PRESCALE.*/UART_PRESCALE = 32'd0;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
-	sed -i "s/PLIC_NUM_SRC = .*/PLIC_NUM_SRC = 32'd53;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
-	sed -i "s/PLIC_SDC_ID.*/PLIC_SDC_ID = 32'd20;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
-	sed -i "s/BPRED_SIZE.*/BPRED_SIZE = 32'd12;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
-	sed -i "s/$\$readmemh.*/$\$readmemh(\"..\/..\/..\/fpga\/src\/boot.mem\", ROM, 0);/g" ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv
 	# This line allows the Bootloader to be loaded in a Block RAM on the FPGA
 	sed -i "s/logic \[DATA_WIDTH-1:0\].*ROM.*/(\* rom_style=\"block\" \*) &/g" ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv
 

sim/coverage-exclusions-rv64gc.do

@@ -308,6 +308,48 @@ coverage exclude -scope /dut/core/ebu/ebu/ebufsmarb -linerange $line-$line -item
 set line [GetLineNum ../src/ebu/ebufsmarb.sv "FinalBeatReg\\("]
 coverage exclude -scope /dut/core/ebu/ebu/ebufsmarb -linerange $line-$line -item e 1 -fecexprrow 1
 
+set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm Atomic"]
+coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line  -item bc 1
+
+set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicWait"]
+coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item bc 1
+
+# The WritebackWriteback and FetchWriteback support back to back pipelined cache writebacks and fetch then
+# writebacks.  The cache never issues these type of requests.
+set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm WritebackWriteback"]
+coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item bc 2
+
+set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWriteback"]
+coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item bc 2
+
+# FetchWait never occurs because HREADY is never 0.
+set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWait"]
+coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item bc 1
+
+# all of these HEADY exclusions occur because HREADY is always 1.  The ram_ahb module never stalls.
+set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY0"]
+coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1
+
+set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY1"]
+coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1
+
+set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY2"]
+coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1
+
+set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY3"]
+coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 4
+
+set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY4"]
+coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1
+coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 3
+
+set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY5"]
+coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1
+
+set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY6"]
+coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1
+coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 5
+
 # TLB not recently used never has all RU bits = 1 because it will then clear all to 0
 # This is a blunt instrument; perhaps there is a more graceful exclusion
 coverage exclude -srcfile priorityonehot.sv 

src/ebu/buscachefsm.sv

@@ -87,27 +87,27 @@ module buscachefsm #(
   
   always_comb begin
       case(CurrState)
-        ADR_PHASE: if (HREADY & |BusRW)                               NextState = DATA_PHASE;
+        ADR_PHASE: if (HREADY & |BusRW)                               NextState = DATA_PHASE; // exclusion-tag: buscachefsm HREADY0
-                   else if (HREADY & BusWrite)                        NextState = CACHE_WRITEBACK;
+                   else if (HREADY & BusWrite)                        NextState = CACHE_WRITEBACK; // exclusion-tag: buscachefsm HREADY1
                    else if (HREADY & CacheBusRW[1])                   NextState = CACHE_FETCH;
                    else                                               NextState = ADR_PHASE;
-        DATA_PHASE:  if(HREADY & BusAtomic)                           NextState = ATOMIC_READ_DATA_PHASE;
+        DATA_PHASE:  if(HREADY & BusAtomic)                           NextState = ATOMIC_READ_DATA_PHASE; // exclusion-tag: buscachefsm HREADY2
-                     else if(HREADY & ~BusAtomic)                     NextState = MEM3;
+                     else if(HREADY & ~BusAtomic)                     NextState = MEM3; // exclusion-tag: buscachefsm HREADY3
                      else                                             NextState = DATA_PHASE;
         ATOMIC_READ_DATA_PHASE: if(HREADY)                            NextState = ATOMIC_PHASE;
-                    else                                              NextState = ATOMIC_READ_DATA_PHASE;
+                    else                                              NextState = ATOMIC_READ_DATA_PHASE; // exclusion-tag: buscachefsm Atomic
         ATOMIC_PHASE: if(HREADY)                                      NextState = MEM3;
-                      else                                            NextState = ATOMIC_PHASE;
+                      else                                            NextState = ATOMIC_PHASE; // exclusion-tag: buscachefsm AtomicWait
         MEM3:        if(Stall)                                        NextState = MEM3;
                      else                                             NextState = ADR_PHASE;
-        CACHE_FETCH: if(HREADY & FinalBeatCount & CacheBusRW[0])      NextState = CACHE_WRITEBACK;
+        CACHE_FETCH: if(HREADY & FinalBeatCount & CacheBusRW[0])      NextState = CACHE_WRITEBACK;  // exclusion-tag: buscachefsm FetchWriteback
-                     else if(HREADY & FinalBeatCount & CacheBusRW[1]) NextState = CACHE_FETCH;
+                     else if(HREADY & FinalBeatCount & CacheBusRW[1]) NextState = CACHE_FETCH;      // exclusion-tag: buscachefsm FetchWait
                      else if(HREADY & FinalBeatCount & ~|CacheBusRW)  NextState = ADR_PHASE;
                      else                                             NextState = CACHE_FETCH;
-        CACHE_WRITEBACK: if(HREADY & FinalBeatCount & CacheBusRW[0])  NextState = CACHE_WRITEBACK;
+        CACHE_WRITEBACK: if(HREADY & FinalBeatCount & CacheBusRW[0])  NextState = CACHE_WRITEBACK; // exclusion-tag: buscachefsm WritebackWriteback
-                     else if(HREADY & FinalBeatCount & CacheBusRW[1]) NextState = CACHE_FETCH;
+                     else if(HREADY & FinalBeatCount & CacheBusRW[1]) NextState = CACHE_FETCH;     // exclusion-tag: buscachefsm HREADY4
-                     else if(HREADY & FinalBeatCount & BusCMOZero)    NextState = MEM3;
+                     else if(HREADY & FinalBeatCount & BusCMOZero)    NextState = MEM3;            // exclusion-tag: buscachefsm HREADY5
-                     else if(HREADY & FinalBeatCount & ~|CacheBusRW)  NextState = ADR_PHASE;
+                     else if(HREADY & FinalBeatCount & ~|CacheBusRW)  NextState = ADR_PHASE;       // exclusion-tag: buscachefsm HREADY6
                      else                                             NextState = CACHE_WRITEBACK;
         default:                                                      NextState = ADR_PHASE;
       endcase

src/ieu/controller.sv

@@ -42,6 +42,7 @@ module controller import cvw::*;  #(parameter cvw_t P) (
   output logic        BranchD,                 // Branch instruction
   output logic        StructuralStallD,        // Structural stalls detected by controller
   output logic        LoadStallD,              // Structural stalls for load, sent to performance counters
+  output logic        StoreStallD,             // load after store hazard
   output logic [4:0]  Rs1D, Rs2D,              // Register sources to read in Decode or Execute stage
   // Execute stage control signals             
   input  logic        StallE, FlushE,          // Stall, flush Execute stage
@@ -159,7 +160,6 @@ module controller import cvw::*;  #(parameter cvw_t P) (
   logic        CMOStallD;                      // Structural hazards from cache management ops
   logic        MatchDE;                        // Match between a source register in Decode stage and destination register in Execute stage
   logic        FCvtIntStallD, MDUStallD, CSRRdStallD; // Stall due to conversion, load, multiply/divide, CSR read 
-  logic        StoreStallD;                    // load after store hazard
   logic        FunctCZeroD;                    // Funct7 and Funct3 indicate czero.* (not including Op check)
   
   // Extract fields

src/ieu/ieu.sv

@@ -76,6 +76,7 @@ module ieu import cvw::*;  #(parameter cvw_t P) (
   input  logic              FlushD, FlushE, FlushM, FlushW,  // Flush signals
   output logic              StructuralStallD,                // IEU detects structural hazard in Decode stage
   output logic              LoadStallD,                      // Structural stalls for load, sent to performance counters
+  output logic              StoreStallD,                     // load after store hazard
   output logic              CSRReadM, CSRWriteM, PrivilegedM,// CSR read, CSR write, is privileged instruction
   output logic              CSRWriteFenceM                   // CSR write or fence instruction needs to flush subsequent instructions
 );
@@ -107,7 +108,7 @@ module ieu import cvw::*;  #(parameter cvw_t P) (
   controller #(P) c(
     .clk, .reset, .StallD, .FlushD, .InstrD, .STATUS_FS, .ENVCFG_CBE, .ImmSrcD,
     .IllegalIEUFPUInstrD, .IllegalBaseInstrD, 
-    .StructuralStallD, .LoadStallD, .Rs1D, .Rs2D, 
+    .StructuralStallD, .LoadStallD, .StoreStallD, .Rs1D, .Rs2D, 
     .StallE, .FlushE, .FlagsE, .FWriteIntE,
     .PCSrcE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .MemReadE, .CSRReadE, 
     .Funct3E, .IntDivE, .MDUE, .W64E, .SubArithE, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, 

src/lsu/lsu.sv

@@ -374,12 +374,12 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
 
       ahbinterface #(P.XLEN, 1'b1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .Flush(FlushW), .HREADY(LSUHREADY), 
         .HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA),
-        .HWSTRB(LSUHWSTRB), .BusRW, .BusAtomic(AtomicM[1]), .ByteMask(ByteMaskM), .WriteData(LSUWriteDataM[P.XLEN-1:0]),
+        .HWSTRB(LSUHWSTRB), .BusRW, .BusAtomic(AtomicM[1]), .ByteMask(ByteMaskM[P.XLEN/8-1:0]), .WriteData(LSUWriteDataM[P.XLEN-1:0]),
         .Stall(GatedStallW), .BusStall, .BusCommitted(BusCommittedM), .FetchBuffer(FetchBuffer));
 
     // Mux between the 2 sources of read data, 0: Bus, 1: DTIM
       if(P.DTIM_SUPPORTED) mux2 #(P.XLEN) ReadDataMux2(FetchBuffer, DTIMReadDataWordM[P.XLEN-1:0], SelDTIM, ReadDataWordMuxM[P.XLEN-1:0]);
-      else assign ReadDataWordMuxM = FetchBuffer[P.XLEN-1:0];
+      else assign ReadDataWordMuxM[P.XLEN-1:0] = FetchBuffer[P.XLEN-1:0]; // *** bus only does not support double wide floats.
       assign LSUHBURST = 3'b0;
       assign {DCacheStallM, DCacheCommittedM, DCacheMiss, DCacheAccess} = '0;
  end

src/privileged/csr.sv

@@ -54,7 +54,7 @@ module csr import cvw::*;  #(parameter cvw_t P) (
   input  logic [3:0]               CauseM,                    // Trap cause
   input  logic                     SelHPTW,                   // hardware page table walker active, so base endianness on supervisor mode
   // inputs for performance counters
-  input  logic                     LoadStallD,
+  input  logic                     LoadStallD, StoreStallD, 
   input  logic                     ICacheStallF,
   input  logic                     DCacheStallM,
   input  logic                     BPDirPredWrongM,
@@ -275,7 +275,7 @@ module csr import cvw::*;  #(parameter cvw_t P) (
   
   if (P.ZICNTR_SUPPORTED) begin:counters
     csrc #(P) counters(.clk, .reset, .StallE, .StallM, .FlushM,
-      .InstrValidNotFlushedM, .LoadStallD, .CSRWriteM, .CSRMWriteM,
+      .InstrValidNotFlushedM, .LoadStallD, .StoreStallD, .CSRWriteM, .CSRMWriteM,
       .BPDirPredWrongM, .BTAWrongM, .RASPredPCWrongM, .IClassWrongM, .BPWrongM,
       .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .sfencevmaM,
       .InterruptM, .ExceptionM, .InvalidateICacheM, .ICacheStallF, .DCacheStallM, .DivBusyE, .FDivBusyE,

src/privileged/csrc.sv

@@ -33,7 +33,7 @@ module csrc  import cvw::*;  #(parameter cvw_t P) (
   input  logic              clk, reset,
   input  logic              StallE, StallM, 
   input  logic              FlushM, 
-  input  logic              InstrValidNotFlushedM, LoadStallD, 
+  input  logic              InstrValidNotFlushedM, LoadStallD, StoreStallD,
   input  logic              CSRMWriteM, CSRWriteM,
   input  logic              BPDirPredWrongM,
   input  logic              BTAWrongM,
@@ -76,6 +76,7 @@ module csrc  import cvw::*;  #(parameter cvw_t P) (
   logic [P.XLEN-1:0]       HPMCOUNTER_REGW[P.COUNTERS-1:0];
   logic [P.XLEN-1:0]       HPMCOUNTERH_REGW[P.COUNTERS-1:0];
   logic                    LoadStallE, LoadStallM;
+  logic                    StoreStallE, StoreStallM;
   logic [P.COUNTERS-1:0]   WriteHPMCOUNTERM;
   logic [P.COUNTERS-1:0]   CounterEvent;
   logic [63:0]             HPMCOUNTERPlusM[P.COUNTERS-1:0];
@@ -86,6 +87,9 @@ module csrc  import cvw::*;  #(parameter cvw_t P) (
   flopenrc #(1) LoadStallEReg(.clk, .reset, .clear(1'b0), .en(~StallE), .d(LoadStallD), .q(LoadStallE));  // don't flush the load stall during a load stall.
   flopenrc #(1) LoadStallMReg(.clk, .reset, .clear(FlushM), .en(~StallM), .d(LoadStallE), .q(LoadStallM));  
 
+  flopenrc #(1) StoreStallEReg(.clk, .reset, .clear(1'b0), .en(~StallE), .d(StoreStallD), .q(StoreStallE));  // don't flush the load stall during a load stall.
+  flopenrc #(1) StoreStallMReg(.clk, .reset, .clear(FlushM), .en(~StallM), .d(StoreStallE), .q(StoreStallM));  
+  
   // Determine when to increment each counter
   assign CounterEvent[0]    = 1'b1;                                                      // MCYCLE always increments
   assign CounterEvent[1]    = 1'b0;                                                      // Counter 1 doesn't exist
@@ -100,7 +104,7 @@ module csrc  import cvw::*;  #(parameter cvw_t P) (
     assign CounterEvent[9]  = RASPredPCWrongM & InstrValidNotFlushedM;                   // return address stack wrong address
     assign CounterEvent[10] = IClassWrongM & InstrValidNotFlushedM;                      // instruction class predictor wrong
     assign CounterEvent[11] = LoadStallM;                                                // Load Stalls. don't want to suppress on flush as this only happens if flushed.
-    assign CounterEvent[12] = 0;                                                         // depricated Store Stall
+    assign CounterEvent[12] = StoreStallM;                                               // depricated Store Stall
     assign CounterEvent[13] = DCacheAccess;                                              // data cache access
     assign CounterEvent[14] = DCacheMiss;                                                // data cache miss. Miss asserted 1 cycle at start of cache miss
     assign CounterEvent[15] = DCacheStallM;                                              // d cache miss cycles

src/privileged/privileged.sv

@@ -46,6 +46,7 @@ module privileged import cvw::*;  #(parameter cvw_t P) (
   // processor events for performance counter logging                      
   input  logic              FRegWriteM,                                     // instruction will write floating-point registers
   input  logic              LoadStallD,                                     // load instruction is stalling
+  input  logic              StoreStallD,                                    // store instruction is stalling
   input  logic              ICacheStallF,                                   // I cache stalled
   input  logic              DCacheStallM,                                   // D cache stalled
   input  logic              BPDirPredWrongM,                                // branch predictor guessed wrong direction
@@ -135,7 +136,7 @@ module privileged import cvw::*;  #(parameter cvw_t P) (
     .InstrM, .InstrOrigM, .PCM, .SrcAM, .IEUAdrM, 
     .CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .InterruptM,
     .MTimerInt, .MExtInt, .SExtInt, .MSwInt,
-    .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, 
+    .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, .StoreStallD,
     .BPDirPredWrongM, .BTAWrongM, .RASPredPCWrongM, .BPWrongM,
     .sfencevmaM, .ExceptionM, .InvalidateICacheM, .ICacheStallF, .DCacheStallM, .DivBusyE, .FDivBusyE,
     .IClassWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,

src/wally/wallypipelinedcore.sv

@@ -78,6 +78,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
   logic                          DivBusyE;
   logic                          StructuralStallD;
   logic                          LoadStallD;
+  logic                          StoreStallD;
   logic                          SquashSCW;
   logic                          MDUActiveE;                      // Mul/Div instruction being executed
   logic                          ENVCFG_ADUE;                     // HPTW A/D Update enable
@@ -212,7 +213,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
      .InstrValidM, .InstrValidE, .InstrValidD, .FCvtIntResW, .FCvtIntW,
      // hazards
      .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
-     .StructuralStallD, .LoadStallD, .PCSrcE,
+     .StructuralStallD, .LoadStallD, .StoreStallD, .PCSrcE,
      .CSRReadM, .CSRWriteM, .PrivilegedM, .CSRWriteFenceM, .InvalidateICacheM); 
 
   lsu #(P) lsu(
@@ -286,7 +287,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
       .InstrM, .InstrOrigM, .CSRReadValW, .EPCM, .TrapVectorM,
       .RetM, .TrapM, .sfencevmaM, .InvalidateICacheM, .DCacheStallM, .ICacheStallF,
       .InstrValidM, .CommittedM, .CommittedF,
-      .FRegWriteM, .LoadStallD,
+      .FRegWriteM, .LoadStallD, .StoreStallD,
       .BPDirPredWrongM, .BTAWrongM, .BPWrongM,
       .RASPredPCWrongM, .IClassWrongM, .DivBusyE, .FDivBusyE,
       .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM,

testbench/testbench.sv

@@ -326,14 +326,13 @@ module testbench;
       end else begin 
         // for tests with no self checking mechanism, read .signature.output file and compare to check for errors
         // clear signature to prevent contamination from previous tests
-      end
-
         if (!begin_signature_addr)
           $display("begin_signature addr not found in %s", ProgramLabelMapFile);
         else if (TEST != "embench") begin   // *** quick hack for embench.  need a better long term solution
           CheckSignature(pathname, tests[test], riscofTest, begin_signature_addr, errors);
-      end
           if(errors > 0) totalerrors = totalerrors + 1;
+        end
+      end
       test = test + 1; // *** this probably needs to be moved.
       if (test == tests.size()) begin
         if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");

tests/coverage/Makefile

@@ -19,7 +19,7 @@ all: $(OBJECTS)
 %.elf: $(SRCDIR)/%.$(SEXT) WALLY-init-lib.h Makefile
 	riscv64-unknown-elf-gcc -g -o $@ -march=rv64gqc_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom -mabi=lp64 -mcmodel=medany \
 	    -nostartfiles -T../../examples/link/link.ld $<
-	riscv64-unknown-elf-objdump -S $@ > $@.objdump
+	riscv64-unknown-elf-objdump -S -D $@ > $@.objdump
 	riscv64-unknown-elf-elf2hex --bit-width 64 --input $@ --output $@.memfile
 	extractFunctionRadix.sh $@.objdump
     

tests/coverage/tlbmisc.S

@@ -96,6 +96,49 @@ main:
     sw t1, 0(t0)    # write to page
     jalr ra, t0     # jump to page
 
+    # AMO at page has PBMT = 2 or 1 (uncached)
+    li t0, 0x80401000
+    li t1, 10
+    amoadd.w t1, t1, (t0)
+
+    la t2, SpecialPage
+    li t0, 0x200000000  # an address to a specific 1 GiB page
+    j ConcurrentICacheMissDTLBMiss
+
+.align 6
+ConcurrentICacheMissDTLBMiss:
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+    lw t1, 0(t0)
+
+    # write a cacheline length (512 bits) to memory in uncached region
+    li t0, 0x80401000
+    cbo.zero (t0)
+
     # Nonleaf PTE has PBMT != 0     causes a page fault during page walking.  H
     li t0, 0x80600000
     lw t1, 0(t0)    # read from page
@@ -294,6 +337,12 @@ pagetable:
     .8byte 0x00000000200058C1 # PTE for pages at 0x40000000 pointing to 0x80150000
     .8byte 0x00000000200048C1 # gigapage at 0x80000000 pointing to 0x80120000
     .8byte 0x00000000000000C1 # gigapage at VA 0xC0000000 causes access fault
+    .8byte 0x0
+    .8byte 0x0
+    .8byte 0x0
+    .8byte 0x0
+SpecialPage:    
+    .8byte 0x00000000200000CF   # 0x2_0000_0000 1GiB page1
  
 
 # Next page table at 0x80012000 for gigapage at 0x80000000
@@ -409,6 +458,7 @@ pagetable:
 .align 12
     #80400000
     .8byte 0x60000000200020CF   # reserved entry
+    .8byte 0x40000000201000CF   # non-cache non-idempotent
 
 # Leaf page table at 0x80015000 with various permissions for testing CBOM and CBOZ
 .align 12