diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc
index 890894bce..869b8d923 100644
--- a/fpga/constraints/debug2.xdc
+++ b/fpga/constraints/debug2.xdc
@@ -825,3 +825,8 @@ set_property port_width 64 [get_debug_ports u_ila_0/probe169]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe169]
connect_debug_port u_ila_0/probe169 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[0]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[1]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[2]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[3]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[4]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[5]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[6]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[7]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[8]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[9]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[10]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[11]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[12]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[13]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[14]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[15]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[16]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[17]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[18]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[19]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[20]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[21]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[22]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[23]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[24]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[25]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[26]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[27]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[28]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[29]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[30]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[31]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[32]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[33]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[34]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[35]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[36]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[37]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[38]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[39]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[40]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[41]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[42]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[43]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[44]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[45]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[46]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[47]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[48]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[49]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[50]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[51]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[52]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[53]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[54]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[55]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[56]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[57]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[58]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[59]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[60]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[61]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[62]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[63]}]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 2 [get_debug_ports u_ila_0/probe170]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe170]
+connect_debug_port u_ila_0/probe170 [get_nets [list {wallypipelinedsoc/core/ebu/HTRANS[0]} {wallypipelinedsoc/core/ebu/HTRANS[1]}]]
diff --git a/fpga/generator/wave_config.wcfg b/fpga/generator/wave_config.wcfg
index 9a6af16f2..413d5cdeb 100644
--- a/fpga/generator/wave_config.wcfg
+++ b/fpga/generator/wave_config.wcfg
@@ -10,12 +10,12 @@
-
+
-
+
@@ -69,14 +69,6 @@
true
STYLE_DIGITAL
-
- FullPathName
- wallypipelinedsoc/core/ReadDataM[63:0]
- ReadDataM[63:0]
- HEXRADIX
- true
- STYLE_DIGITAL
-
FullPathName
wallypipelinedsoc/core/lsu/WriteDataM[63:0]
@@ -98,14 +90,6 @@
true
STYLE_DIGITAL
-
- FullPathName
- wallypipelinedsoc/core/priv.priv/trap/SIP_REGW[9:9]
- SIP_REGW[9:9]
- HEXRADIX
- true
- STYLE_DIGITAL
-
PLIC
@@ -148,22 +132,6 @@
MIDELEG_REGW[11:0]
HEXRADIX
-
- FullPathName
- wallypipelinedsoc/core/priv.priv/trap/MPendingIntsM[11:0]
- MPendingIntsM[11:0]
- HEXRADIX
- true
- STYLE_DIGITAL
-
-
- FullPathName
- wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[11:0]
- SPendingIntsM[11:0]
- HEXRADIX
- true
- STYLE_DIGITAL
-
FullPathName
wallypipelinedsoc/core/priv.priv/InterruptM
@@ -280,30 +248,6 @@
true
STYLE_DIGITAL
-
- FullPathName
- wallypipelinedsoc/core/priv.priv/trap/SIE_REGW[9:9]
- SIE_REGW[9:9]
- HEXRADIX
- true
- STYLE_DIGITAL
-
-
- FullPathName
- wallypipelinedsoc/core/priv.priv/trap/SIE_REGW_1[1:1]
- SIE_REGW_1[1:1]
- HEXRADIX
- true
- STYLE_DIGITAL
-
-
- FullPathName
- wallypipelinedsoc/core/priv.priv/trap/SIE_REGW_2[5:5]
- SIE_REGW_2[5:5]
- HEXRADIX
- true
- STYLE_DIGITAL
-
sdc
diff --git a/pipelined/src/cache/sram1p1rw.sv b/pipelined/src/cache/sram1p1rw.sv
index ca1b07437..2a739cea1 100644
--- a/pipelined/src/cache/sram1p1rw.sv
+++ b/pipelined/src/cache/sram1p1rw.sv
@@ -74,7 +74,7 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) (
for(index = 0; index < WIDTH/8; index++)
always_ff @(posedge clk)
if(ce & WriteEnable & ByteMask[index])
- StoredData[Adr][index*8 +: 8] <= #1 CacheWriteData[index*8 +: 8];
+ StoredData[Adr][index*8 +: 8] <= #1 CacheWriteData[index*8 +: 8];
assign ReadData = StoredData[AdrD];
end
diff --git a/pipelined/src/generic/flop/bram1p1rw.sv b/pipelined/src/generic/flop/bram1p1rw.sv
index 51fe54214..8d0a3bf1b 100644
--- a/pipelined/src/generic/flop/bram1p1rw.sv
+++ b/pipelined/src/generic/flop/bram1p1rw.sv
@@ -39,6 +39,7 @@ module bram1p1rw
parameter NUM_COL = 8,
parameter COL_WIDTH = 8,
parameter ADDR_WIDTH = 10,
+ parameter PRELOAD_ENABLED = 0,
// Addr Width in bits : 2 *ADDR_WIDTH = RAM Depth
parameter DATA_WIDTH = NUM_COL*COL_WIDTH // Data Width in bits
//----------------------------------------------------------------------
@@ -54,6 +55,55 @@ module bram1p1rw
logic [DATA_WIDTH-1:0] RAM [(2**ADDR_WIDTH)-1:0];
integer i;
+ if(PRELOAD_ENABLED) begin
+ initial begin
+ RAM[0] = 64'h9581819300002197;
+ RAM[1] = 64'h4281420141014081;
+ RAM[2] = 64'h4481440143814301;
+ RAM[3] = 64'h4681460145814501;
+ RAM[4] = 64'h4881480147814701;
+ RAM[5] = 64'h4a814a0149814901;
+ RAM[6] = 64'h4c814c014b814b01;
+ RAM[7] = 64'h4e814e014d814d01;
+ RAM[8] = 64'h0110011b4f814f01;
+ RAM[9] = 64'h059b45011161016e;
+ RAM[10] = 64'h0004063705fe0010;
+ RAM[11] = 64'h05a000ef8006061b;
+ RAM[12] = 64'h0ff003930000100f;
+ RAM[13] = 64'h4e952e3110060e37;
+ RAM[14] = 64'hc602829b0053f2b7;
+ RAM[15] = 64'h2023fe02dfe312fd;
+ RAM[16] = 64'h829b0053f2b7007e;
+ RAM[17] = 64'hfe02dfe312fdc602;
+ RAM[18] = 64'h4de31efd000e2023;
+ RAM[19] = 64'h059bf1402573fdd0;
+ RAM[20] = 64'h0000061705e20870;
+ RAM[21] = 64'h0010029b01260613;
+ RAM[22] = 64'h11010002806702fe;
+ RAM[23] = 64'h84b2842ae426e822;
+ RAM[24] = 64'h892ee04aec064511;
+ RAM[25] = 64'h06e000ef07e000ef;
+ RAM[26] = 64'h979334fd02905563;
+ RAM[27] = 64'h07930177d4930204;
+ RAM[28] = 64'h4089093394be2004;
+ RAM[29] = 64'h04138522008905b3;
+ RAM[30] = 64'h19e3014000ef2004;
+ RAM[31] = 64'h64a2644260e2fe94;
+ RAM[32] = 64'h6749808261056902;
+ RAM[33] = 64'hdfed8b8510472783;
+ RAM[34] = 64'h2423479110a73823;
+ RAM[35] = 64'h10472783674910f7;
+ RAM[36] = 64'h20058693ffed8b89;
+ RAM[37] = 64'h05a1118737836749;
+ RAM[38] = 64'hfed59be3fef5bc23;
+ RAM[39] = 64'h1047278367498082;
+ RAM[40] = 64'h47858082dfed8b85;
+ RAM[41] = 64'h40a7853b4015551b;
+ RAM[42] = 64'h808210a7a02367c9;
+ end
+end
+
+
always @ (posedge clk) begin
dout <= RAM[addr];
if(we) begin
diff --git a/pipelined/src/uncore/ram.sv b/pipelined/src/uncore/ram.sv
index b850321e8..72b2a7486 100644
--- a/pipelined/src/uncore/ram.sv
+++ b/pipelined/src/uncore/ram.sv
@@ -70,7 +70,7 @@ module ram #(parameter BASE=0, RANGE = 65535) (
mux2 #(32) adrmux(HADDR, HADDRD, memwriteD | ~HREADY, RamAddr);
// single-ported RAM
- bram1p1rw #(`XLEN/8, 8, ADDR_WIDTH)
+ bram1p1rw #(`XLEN/8, 8, ADDR_WIDTH, `FPGA)
memory(.clk(HCLK), .we(memwriteD), .bwe(HWSTRB), .addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .dout(HREADRam), .din(HWDATA));
endmodule