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Working CBO tests for 64 bit!

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This commit is contained in:
Ross Thompson 2023-08-21 12:55:07 -05:00
parent 34a8c042b7
commit 6ffbdaac0a
4 changed files with 50 additions and 4 deletions
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1
testbench/tests.vh
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@ -1936,6 +1936,7 @@ string arch64zbs[] = '{
string wally64priv[] = '{ string wally64priv[] = '{
`WALLYTEST, `WALLYTEST,
"rv64i_m/privilege/src/WALLY-csr-permission-s-01.S", "rv64i_m/privilege/src/WALLY-csr-permission-s-01.S",
"rv64i_m/privilege/src/WALLY-cbom-01.S",
"rv64i_m/privilege/src/WALLY-csr-permission-u-01.S", "rv64i_m/privilege/src/WALLY-csr-permission-u-01.S",
"rv64i_m/privilege/src/WALLY-mie-01.S", "rv64i_m/privilege/src/WALLY-mie-01.S",
"rv64i_m/privilege/src/WALLY-minfo-01.S", "rv64i_m/privilege/src/WALLY-minfo-01.S",

1
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag
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@ -56,6 +56,7 @@ target_tests_nosim = \
WALLY-trap-u-01 \ WALLY-trap-u-01 \
WALLY-status-fp-enabled-01 \ WALLY-status-fp-enabled-01 \
WALLY-wfi-01 \ WALLY-wfi-01 \
WALLY-cbom-01 \
# unclear why status-fp-enabled and wfi aren't simulating ok # unclear why status-fp-enabled and wfi aren't simulating ok

46
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-cbom-01.reference_output
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@ -1,3 +1,31 @@
deadbeef # begin_signature
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef # destination 1 deadbeef # destination 1
deadbeef deadbeef
deadbeef deadbeef
@ -523,6 +551,22 @@ ffffffff
ffffffff ffffffff
ffffffff ffffffff
ffffffff ffffffff
0bad0bad # controls ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
0bad0bad # controls
0bad0bad
0bad0bad
0bad0bad
0bad0bad 0bad0bad
0bad0bad 0bad0bad

6
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cbom-01.S
View File

@ -444,7 +444,7 @@ SourceData:
.int 48, 49, 50, 51, 52, 53, 54, 55 .int 48, 49, 50, 51, 52, 53, 54, 55
.int 56, 57, 58, 59, 60, 61, 62, 63 .int 56, 57, 58, 59, 60, 61, 62, 63
.int 64, 65, 66, 67, 68, 69, 70, 71 .int 64, 65, 66, 67, 68, 69, 70, 71
.int 72, 73, 74, 75, 76, 77, 79, 79 .int 72, 73, 74, 75, 76, 77, 78, 79
.int 80, 81, 82, 83, 84, 85, 86, 87 .int 80, 81, 82, 83, 84, 85, 86, 87
.int 88, 89, 90, 91, 92, 93, 94, 95 .int 88, 89, 90, 91, 92, 93, 94, 95
.int 96, 97, 98, 99, 100, 101, 102, 103 .int 96, 97, 98, 99, 100, 101, 102, 103
@ -458,7 +458,7 @@ RVMODEL_DATA_BEGIN
.fill 28, 4, 0xdeadbeef # this is annoying, but RVMODEL_DATA_END and BEGIN insert .fill 28, 4, 0xdeadbeef # this is annoying, but RVMODEL_DATA_END and BEGIN insert
# 4 bytes. This needs to be aligned to a cacheline # 4 bytes. This needs to be aligned to a cacheline
.align 6 .align 6
Destination1: Destination1:
.fill 128, 4, 0xdeadbeef .fill 128, 4, 0xdeadbeef
Destination2: Destination2:
@ -469,7 +469,7 @@ Destination4:
.fill 128, 4, 0xdeadbeef .fill 128, 4, 0xdeadbeef
signature: signature:
.fill 128, 4, 0xdeadbeef .fill 32, 4, 0x0bad0bad
RVMODEL_DATA_END RVMODEL_DATA_END