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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev

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This commit is contained in:
David Harris 2023-11-19 06:49:25 -08:00
commit 6fd32b6643
11 changed files with 574 additions and 59 deletions
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6
.gitmodules vendored
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@ -23,9 +23,9 @@
[submodule "addins/vivado-boards"] [submodule "addins/vivado-boards"]
path = addins/vivado-boards path = addins/vivado-boards
url = https://github.com/Digilent/vivado-boards/ url = https://github.com/Digilent/vivado-boards/
[submodule "addins/vivado-risc-v"] [submodule "addins/ahbsdc"]
path = addins/vivado-risc-v path = addins/ahbsdc
url = https://github.com/eugene-tarassov/vivado-risc-v.git url = git@github.com:jacobpease/ahbsdc.git
[submodule "addins/riscv-arch-test"] [submodule "addins/riscv-arch-test"]
path = addins/riscv-arch-test path = addins/riscv-arch-test
url = https://github.com/riscv-non-isa/riscv-arch-test url = https://github.com/riscv-non-isa/riscv-arch-test

1
addins/ahbsdc Submodule

@ -0,0 +1 @@
Subproject commit 5df21aa6625eca120e64ea353ca641aff37d90b2

1
addins/vivado-risc-v

@ -1 +0,0 @@
Subproject commit c76a8613a177b3a04face2cb8e15dd07a8d2fc40

1
fpga/constraints/marked_debug.txt
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@ -45,6 +45,7 @@ ifu/ifu.sv: logic PCPF
ifu/ifu.sv: logic PostSpillInstrRawF ifu/ifu.sv: logic PostSpillInstrRawF
mmu/hptw.sv: logic ITLBWriteF mmu/hptw.sv: logic ITLBWriteF
mmu/hptw.sv: statetype WalkerState mmu/hptw.sv: statetype WalkerState
mmu/hptw.sv: logic ValidPTE
privileged/csrs.sv: logic CSRSReadValM privileged/csrs.sv: logic CSRSReadValM
privileged/csrs.sv: logic SEPC_REGW privileged/csrs.sv: logic SEPC_REGW
privileged/csrs.sv: logic MIP_REGW privileged/csrs.sv: logic MIP_REGW

8
fpga/generator/wally.tcl
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@ -42,13 +42,9 @@ if {$board=="ArtyA7"} {
# read in all other rtl # read in all other rtl
read_verilog -sv [glob -type f ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*/*.sv] read_verilog -sv [glob -type f ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*/*.sv]
# *** Once the sdc is updated to use ahb changes these to system verilog. # *** Once the sdc is updated to use ahb changes these to system verilog.
read_verilog [glob -type f ../src/axi_sdc_controller.v] read_verilog [glob -type f ../../addins/ahbsdc/sdc/*.v]
read_verilog [glob -type f ../../addins/vivado-risc-v/sdc/sd_cmd_master.v]
read_verilog [glob -type f ../../addins/vivado-risc-v/sdc/sd_cmd_serial_host.v]
read_verilog [glob -type f ../../addins/vivado-risc-v/sdc/sd_data_master.v]
read_verilog [glob -type f ../../addins/vivado-risc-v/sdc/sd_data_serial_host.v]
set_property include_dirs {../src/CopiedFiles_do_not_add_to_repo/config ../../config/shared ../../addins/vivado-risc-v/sdc} [current_fileset] set_property include_dirs {../src/CopiedFiles_do_not_add_to_repo/config ../../config/shared ../../addins/ahbsdc/sdc} [current_fileset]
if {$board=="ArtyA7"} { if {$board=="ArtyA7"} {
add_files -fileset constrs_1 -norecurse ../constraints/constraints-$board.xdc add_files -fileset constrs_1 -norecurse ../constraints/constraints-$board.xdc

513
fpga/src/boot.mem Normal file
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@ -0,0 +1,513 @@
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00600100d2e3ca40

21
linux/Makefile
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@ -27,14 +27,6 @@ BINARIES := fw_jump.elf vmlinux busybox
OBJDUMPS := $(foreach name, $(BINARIES), $(basename $(name) .elf)) OBJDUMPS := $(foreach name, $(BINARIES), $(basename $(name) .elf))
OBJDUMPS := $(foreach name, $(OBJDUMPS), $(DIS)/$(name).objdump) OBJDUMPS := $(foreach name, $(OBJDUMPS), $(DIS)/$(name).objdump)
define linuxDir =
$(shell find $(BUILDROOT)/output/build -maxdepth 2 -type d -regex ".*/linux-[0-9]+\.[0-9]+\.[0-9]+$$")
endef
define busyboxDir =
$(shell find $(BUILDROOT)/output/build -maxdepth 2 -type d -regex ".*/busybox-[0-9]+\.[0-9]+\.[0-9]+$$")
endef
.PHONY: all generate disassemble install clean cleanDTB cleanDriver test .PHONY: all generate disassemble install clean cleanDTB cleanDriver test
all: all:
@ -46,8 +38,7 @@ all:
# Temp rule for debugging # Temp rule for debugging
test: test:
@echo $(linuxDir) echo $(shell find $(BUILDROOT)/output/build -maxdepth 2 -type d -regex ".*/linux-[0-9]+\.[0-9]+\.[0-9]+$$")
@echo $(busyboxDir)
generate: $(DTB) $(IMAGES) generate: $(DTB) $(IMAGES)
@ -74,11 +65,13 @@ $(DIS)/%.objdump: $(IMAGES)/%.elf
$(DIS)/%.objdump: $(IMAGES)/% $(DIS)/%.objdump: $(IMAGES)/%
riscv64-unknown-elf-objdump -S $< >> $@ riscv64-unknown-elf-objdump -S $< >> $@
$(IMAGES)/vmlinux: $(call linuxDir)/vmlinux $(IMAGES)/vmlinux:
cp $< $@ linuxDir=$$(find $(BUILDROOT)/output/build -maxdepth 2 -type d -regex ".*/linux-[0-9]+\.[0-9]+\.[0-9]+$$") ;\
cp $$linuxDir/vmlinux $@ ;\
$(IMAGES)/busybox: $(call busyboxDir)/busybox $(IMAGES)/busybox:
cp $< $@ busyboxDir=$$(find $(BUILDROOT)/output/build -maxdepth 2 -type d -regex ".*/busybox-[0-9]+\.[0-9]+\.[0-9]+$$") ;\
cp $$busyboxDir/busybox $@ ;\
# Generating new Buildroot directories -------------------------------- # Generating new Buildroot directories --------------------------------

22
src/generic/mem/rom1p1r.sv
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@ -33,7 +33,7 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, DATA_WIDTH = 32, PRELOAD_ENABLED = 0)
); );
// Core Memory // Core Memory
logic [DATA_WIDTH-1:0] ROM [(2**ADDR_WIDTH)-1:0]; (*rom_style="block" *) logic [DATA_WIDTH-1:0] ROM [(2**ADDR_WIDTH)-1:0];
// dh 10/30/23 ROM macros are presently commented out // dh 10/30/23 ROM macros are presently commented out
// because they don't point to a generated ROM // because they don't point to a generated ROM
@ -41,15 +41,23 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, DATA_WIDTH = 32, PRELOAD_ENABLED = 0)
rom1p1r_128x64 rom1 (.CLK(clk), .CEB(~ce), .A(addr[6:0]), .Q(dout)); rom1p1r_128x64 rom1 (.CLK(clk), .CEB(~ce), .A(addr[6:0]), .Q(dout));
end if ((`USE_SRAM == 1) & (ADDR_WDITH == 7) & (DATA_WIDTH == 32)) begin end if ((`USE_SRAM == 1) & (ADDR_WDITH == 7) & (DATA_WIDTH == 32)) begin
rom1p1r_128x32 rom1 (.CLK(clk), .CEB(~ce), .A(addr[6:0]), .Q(dout)); rom1p1r_128x32 rom1 (.CLK(clk), .CEB(~ce), .A(addr[6:0]), .Q(dout));
end else begin */ end else begin */
always @ (posedge clk)
if(ce) dout <= ROM[addr]; initial begin
if (PRELOAD_ENABLED) begin
$readmemh("../../../fpga/src/boot.mem", ROM, 0);
end
end
always @ (posedge clk) begin
if(ce) dout <= ROM[addr];
end
// for FPGA, initialize with zero-stage bootloader // for FPGA, initialize with zero-stage bootloader
if(PRELOAD_ENABLED) begin /*if(PRELOAD_ENABLED) begin
initial begin initial begin
ROM[0]=64'h8001819300002197; ROM[0]=64'h8001819300002197;
ROM[1]=64'h4281420141014081; ROM[1]=64'h4281420141014081;
@ -195,6 +203,6 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, DATA_WIDTH = 32, PRELOAD_ENABLED = 0)
ROM[141]=64'h0000808241010113; ROM[141]=64'h0000808241010113;
end // if (PRELOAD_ENABLED) end // if (PRELOAD_ENABLED)
end end*/
endmodule endmodule

57
src/lsu/align.sv
View File

@ -30,33 +30,34 @@
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
module align import cvw::*; #(parameter cvw_t P) ( module align import cvw::*; #(parameter cvw_t P) (
input logic clk, input logic clk,
input logic reset, input logic reset,
input logic StallM, FlushM, input logic StallM, FlushM,
input logic [P.XLEN-1:0] IEUAdrM, // 2 byte aligned PC in Fetch stage input logic [P.XLEN-1:0] IEUAdrM, // 2 byte aligned PC in Fetch stage
input logic [P.XLEN-1:0] IEUAdrE, // The next IEUAdrM input logic [P.XLEN-1:0] IEUAdrE, // The next IEUAdrM
input logic [2:0] Funct3M, // Size of memory operation input logic [2:0] Funct3M, // Size of memory operation
input logic [1:0] MemRWM, input logic [1:0] MemRWM,
input logic CacheableM, input logic CacheableM,
input logic [P.LLEN*2-1:0]DCacheReadDataWordM, // Instruction from the IROM, I$, or bus. Used to check if the instruction if compressed input logic [P.LLEN*2-1:0] DCacheReadDataWordM, // Instruction from the IROM, I$, or bus. Used to check if the instruction if compressed
input logic CacheBusHPWTStall, // I$ or bus are stalled. Transition to second fetch of spill after the first is fetched input logic CacheBusHPWTStall, // I$ or bus are stalled. Transition to second fetch of spill after the first is fetched
input logic DTLBMissM, // ITLB miss, ignore memory request input logic DTLBMissM, // ITLB miss, ignore memory request
input logic DataUpdateDAM, // ITLB miss, ignore memory request input logic DataUpdateDAM, // ITLB miss, ignore memory request
input logic SelHPTW,
input logic [(P.LLEN-1)/8:0] ByteMaskM, input logic [(P.LLEN-1)/8:0] ByteMaskM,
input logic [(P.LLEN-1)/8:0] ByteMaskExtendedM, input logic [(P.LLEN-1)/8:0] ByteMaskExtendedM,
input logic [P.LLEN-1:0] LSUWriteDataM, input logic [P.LLEN-1:0] LSUWriteDataM,
output logic [(P.LLEN*2-1)/8:0] ByteMaskSpillM, output logic [(P.LLEN*2-1)/8:0] ByteMaskSpillM,
output logic [P.LLEN*2-1:0] LSUWriteDataSpillM, output logic [P.LLEN*2-1:0] LSUWriteDataSpillM,
output logic [P.XLEN-1:0] IEUAdrSpillE, // The next PCF for one of the two memory addresses of the spill output logic [P.XLEN-1:0] IEUAdrSpillE, // The next PCF for one of the two memory addresses of the spill
output logic [P.XLEN-1:0] IEUAdrSpillM, // IEUAdrM for one of the two memory addresses of the spill output logic [P.XLEN-1:0] IEUAdrSpillM, // IEUAdrM for one of the two memory addresses of the spill
output logic SelSpillE, // During the transition between the two spill operations, the IFU should stall the pipeline output logic SelSpillE, // During the transition between the two spill operations, the IFU should stall the pipeline
output logic [1:0] MemRWSpillM, output logic [1:0] MemRWSpillM,
output logic SelStoreDelay, //*** this is bad. really don't like moving this outside output logic SelStoreDelay, //*** this is bad. really don't like moving this outside
output logic [P.LLEN-1:0] DCacheReadDataWordSpillM, // The final 32 bit instruction after merging the two spilled fetches into 1 instruction output logic [P.LLEN-1:0] DCacheReadDataWordSpillM, // The final 32 bit instruction after merging the two spilled fetches into 1 instruction
output logic SpillStallM); output logic SpillStallM);
localparam LLENINBYTES = P.LLEN/8; localparam LLENINBYTES = P.LLEN/8;
localparam OFFSET_BIT_POS = $clog2(P.DCACHE_LINELENINBITS/8); localparam OFFSET_BIT_POS = $clog2(P.DCACHE_LINELENINBITS/8);
@ -83,6 +84,7 @@ module align import cvw::*; #(parameter cvw_t P) (
logic [$clog2(LLENINBYTES)-1:0] ByteOffsetM; logic [$clog2(LLENINBYTES)-1:0] ByteOffsetM;
logic HalfSpillM, WordSpillM; logic HalfSpillM, WordSpillM;
logic [$clog2(LLENINBYTES)-1:0] AccessByteOffsetM; logic [$clog2(LLENINBYTES)-1:0] AccessByteOffsetM;
logic ValidAccess;
/* verilator lint_off WIDTHEXPAND */ /* verilator lint_off WIDTHEXPAND */
assign IEUAdrIncrementM = IEUAdrM + LLENINBYTES; assign IEUAdrIncrementM = IEUAdrM + LLENINBYTES;
@ -116,17 +118,18 @@ module align import cvw::*; #(parameter cvw_t P) (
assign WordMisalignedM = (ByteOffsetM[1:0] != '0) & Funct3M[1:0] == 2'b10; assign WordMisalignedM = (ByteOffsetM[1:0] != '0) & Funct3M[1:0] == 2'b10;
assign HalfSpillM = (IEUAdrM[OFFSET_BIT_POS-1:1] == '1) & HalfMisalignedM; assign HalfSpillM = (IEUAdrM[OFFSET_BIT_POS-1:1] == '1) & HalfMisalignedM;
assign WordSpillM = (IEUAdrM[OFFSET_BIT_POS-1:2] == '1) & WordMisalignedM; assign WordSpillM = (IEUAdrM[OFFSET_BIT_POS-1:2] == '1) & WordMisalignedM;
assign ValidAccess = (|MemRWM) & ~SelHPTW;
if(P.LLEN == 64) begin if(P.LLEN == 64) begin
logic DoubleSpillM; logic DoubleSpillM;
logic DoubleMisalignedM; logic DoubleMisalignedM;
assign DoubleMisalignedM = (ByteOffsetM[2:0] != '0) & Funct3M[1:0] == 2'b11; assign DoubleMisalignedM = (ByteOffsetM[2:0] != '0) & Funct3M[1:0] == 2'b11;
assign DoubleSpillM = (IEUAdrM[OFFSET_BIT_POS-1:3] == '1) & DoubleMisalignedM; assign DoubleSpillM = (IEUAdrM[OFFSET_BIT_POS-1:3] == '1) & DoubleMisalignedM;
assign MisalignedM = HalfMisalignedM | WordMisalignedM | DoubleMisalignedM; assign MisalignedM = ValidAccess & (HalfMisalignedM | WordMisalignedM | DoubleMisalignedM);
assign SpillM = (|MemRWM) & CacheableM & (HalfSpillM | WordSpillM | DoubleSpillM); assign SpillM = ValidAccess & CacheableM & (HalfSpillM | WordSpillM | DoubleSpillM);
end else begin end else begin
assign SpillM = (|MemRWM) & CacheableM & (HalfSpillM | WordSpillM); assign SpillM = ValidAccess & CacheableM & (HalfSpillM | WordSpillM);
assign MisalignedM = HalfMisalignedM | WordMisalignedM; assign MisalignedM = ValidAccess & (HalfMisalignedM | WordMisalignedM);
end end
// align by shifting // align by shifting

2
src/lsu/lsu.sv
View File

@ -159,7 +159,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
logic [P.XLEN-1:0] IEUAdrSpillE, IEUAdrSpillM; logic [P.XLEN-1:0] IEUAdrSpillE, IEUAdrSpillM;
align #(P) align(.clk, .reset, .StallM, .FlushM, .IEUAdrE, .IEUAdrM, .Funct3M, align #(P) align(.clk, .reset, .StallM, .FlushM, .IEUAdrE, .IEUAdrM, .Funct3M,
.MemRWM, .CacheableM, .MemRWM, .CacheableM,
.DCacheReadDataWordM, .CacheBusHPWTStall, .DTLBMissM, .DataUpdateDAM, .DCacheReadDataWordM, .CacheBusHPWTStall, .DTLBMissM, .DataUpdateDAM, .SelHPTW,
.ByteMaskM, .ByteMaskExtendedM, .LSUWriteDataM, .ByteMaskSpillM, .LSUWriteDataSpillM, .ByteMaskM, .ByteMaskExtendedM, .LSUWriteDataM, .ByteMaskSpillM, .LSUWriteDataSpillM,
.IEUAdrSpillE, .IEUAdrSpillM, .SelSpillE, .MemRWSpillM, .DCacheReadDataWordSpillM, .SpillStallM, .IEUAdrSpillE, .IEUAdrSpillM, .SelSpillE, .MemRWSpillM, .DCacheReadDataWordSpillM, .SpillStallM,
.SelStoreDelay); .SelStoreDelay);

1
testbench/testbench.sv
View File

@ -389,6 +389,7 @@ module testbench;
assign SDCCmd = SDCCmdOE ? SDCCmdOut : 1'bz; assign SDCCmd = SDCCmdOE ? SDCCmdOut : 1'bz;
assign SDCCmdIn = SDCCmd; assign SDCCmdIn = SDCCmd;
assign SDCDat = sd_dat_reg_t ? sd_dat_reg_o : sd_dat_i;
assign SDCDatIn = SDCDat; assign SDCDatIn = SDCDat;
-----/\----- EXCLUDED -----/\----- */ -----/\----- EXCLUDED -----/\----- */
assign SDCIntr = '0; assign SDCIntr = '0;