From 961cf91482b1da5bc617c1036cadb988981ae8da Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Tue, 26 Sep 2023 15:16:45 -0500 Subject: [PATCH 1/7] Linux Makefile: Fixed find utility crashing for real this time. --- linux/Makefile | 30 +++++++----------------------- 1 file changed, 7 insertions(+), 23 deletions(-) diff --git a/linux/Makefile b/linux/Makefile index 433bf0e73..093913eee 100644 --- a/linux/Makefile +++ b/linux/Makefile @@ -27,23 +27,6 @@ BINARIES := fw_jump.elf vmlinux busybox OBJDUMPS := $(foreach name, $(BINARIES), $(basename $(name) .elf)) OBJDUMPS := $(foreach name, $(OBJDUMPS), $(DIS)/$(name).objdump) -# LINUXDIR := $(shell ls $(BUILDROOT)/output/build | grep -e '^linux-[0-9]\+\.[0-9]\+\.[0-9]\+$$' ) -# LINUXDIR := $(BUILDROOT)/output/build/$(LINUXDIR) -# BUSYBOXDIR := $(shell ls $(BUILDROOT)/output/build | grep -e '^linux-[0-9]\+\.[0-9]\+\.[0-9]\+$$' ) -# BUSYBOXDIR := $(BUILDROOT)/output/build/$(BUSYBOXDIR) - -# Gets Linux and Busybox output folders for objedect dumps -# LINUXDIR ?= $(shell find $(BUILDROOT)/output/build -maxdepth 2 -type d -regex ".*/linux-[0-9]+\.[0-9]+\.[0-9]+$$") -# BUSYBOXDIR ?= $(shell find $(BUILDROOT)/output/build -maxdepth 2 -type d -regex ".*/busybox-[0-9]+\.[0-9]+\.[0-9]+$$") - -define linuxDir = -$(shell find $(BUILDROOT)/output/build -maxdepth 2 -type d -regex ".*/linux-[0-9]+\.[0-9]+\.[0-9]+$$") -endef - -define busyboxDir = -$(shell find $(BUILDROOT)/output/build -maxdepth 2 -type d -regex ".*/busybox-[0-9]+\.[0-9]+\.[0-9]+$$") -endef - .PHONY: all generate disassemble install clean cleanDTB cleanDriver test # Generate all device trees ------------------------------------------- @@ -59,8 +42,7 @@ all: # Temp rule for debugging test: - @echo $(linuxDir) - @echo $(busyboxDir) + echo $(shell find $(BUILDROOT)/output/build -maxdepth 2 -type d -regex ".*/linux-[0-9]+\.[0-9]+\.[0-9]+$$") generate: $(DTB) $(IMAGES) @@ -87,11 +69,13 @@ $(DIS)/%.objdump: $(IMAGES)/%.elf $(DIS)/%.objdump: $(IMAGES)/% riscv64-unknown-elf-objdump -S $< >> $@ -$(IMAGES)/vmlinux: $(call linuxDir)/vmlinux - cp $< $@ +$(IMAGES)/vmlinux: + linuxDir=$$(find $(BUILDROOT)/output/build -maxdepth 2 -type d -regex ".*/linux-[0-9]+\.[0-9]+\.[0-9]+$$") ;\ + cp $$linuxDir/vmlinux $@ ;\ -$(IMAGES)/busybox: $(call busyboxDir)/busybox - cp $< $@ +$(IMAGES)/busybox: + busyboxDir=$$(find $(BUILDROOT)/output/build -maxdepth 2 -type d -regex ".*/busybox-[0-9]+\.[0-9]+\.[0-9]+$$") ;\ + cp $$busyboxDir/busybox $@ ;\ # Generating new Buildroot directories -------------------------------- From 2b1c604016b5ddd878b64b18debadf6ea4e676e5 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Tue, 17 Oct 2023 14:13:18 -0500 Subject: [PATCH 2/7] Slight modification to testbench.sv --- testbench/testbench.sv | 1 + 1 file changed, 1 insertion(+) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 74077e547..dd83f7610 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -387,6 +387,7 @@ module testbench; assign SDCCmd = SDCCmdOE ? SDCCmdOut : 1'bz; assign SDCCmdIn = SDCCmd; + assign SDCDat = sd_dat_reg_t ? sd_dat_reg_o : sd_dat_i; assign SDCDatIn = SDCDat; -----/\----- EXCLUDED -----/\----- */ assign SDCIntr = '0; From ff73f798edf00a4a8f9a1e2730d6af51b6c4d021 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Thu, 16 Nov 2023 13:59:12 -0600 Subject: [PATCH 3/7] Replaced vivado-risc-v addins directory with new SDC repo. --- .gitmodules | 6 +++--- fpga/generator/wally.tcl | 8 ++------ 2 files changed, 5 insertions(+), 9 deletions(-) diff --git a/.gitmodules b/.gitmodules index 361441a18..54d9dd970 100644 --- a/.gitmodules +++ b/.gitmodules @@ -23,9 +23,9 @@ [submodule "addins/vivado-boards"] path = addins/vivado-boards url = https://github.com/Digilent/vivado-boards/ -[submodule "addins/vivado-risc-v"] - path = addins/vivado-risc-v - url = https://github.com/eugene-tarassov/vivado-risc-v.git +[submodule "addins/ahbsdc"] + path = addins/ahbsdc + url = https://github.com/JacobPease/ahbsdc.git [submodule "addins/riscv-arch-test"] path = addins/riscv-arch-test url = https://github.com/riscv-non-isa/riscv-arch-test diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index d699c3d21..bad9981df 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -42,13 +42,9 @@ if {$board=="ArtyA7"} { # read in all other rtl read_verilog -sv [glob -type f ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*/*.sv] # *** Once the sdc is updated to use ahb changes these to system verilog. -read_verilog [glob -type f ../src/axi_sdc_controller.v] -read_verilog [glob -type f ../../addins/vivado-risc-v/sdc/sd_cmd_master.v] -read_verilog [glob -type f ../../addins/vivado-risc-v/sdc/sd_cmd_serial_host.v] -read_verilog [glob -type f ../../addins/vivado-risc-v/sdc/sd_data_master.v] -read_verilog [glob -type f ../../addins/vivado-risc-v/sdc/sd_data_serial_host.v] +read_verilog [glob -type f ../../addins/ahbsdc/sdc/*.v] -set_property include_dirs {../src/CopiedFiles_do_not_add_to_repo/config ../../config/shared ../../addins/vivado-risc-v/sdc} [current_fileset] +set_property include_dirs {../src/CopiedFiles_do_not_add_to_repo/config ../../config/shared ../../addins/ahbsdc/sdc} [current_fileset] if {$board=="ArtyA7"} { add_files -fileset constrs_1 -norecurse ../constraints/constraints-$board.xdc From 9df87872ef73d8ec4aaa7db36f39424f3e6b6e6c Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Thu, 16 Nov 2023 15:13:12 -0600 Subject: [PATCH 4/7] Deleted vivado-risc-v directory and added ahbsdc. --- addins/vivado-risc-v | 1 - 1 file changed, 1 deletion(-) delete mode 160000 addins/vivado-risc-v diff --git a/addins/vivado-risc-v b/addins/vivado-risc-v deleted file mode 160000 index c76a8613a..000000000 --- a/addins/vivado-risc-v +++ /dev/null @@ -1 +0,0 @@ -Subproject commit c76a8613a177b3a04face2cb8e15dd07a8d2fc40 From 38cf7f0fb74553f19898a267753258d49574d4e8 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Thu, 16 Nov 2023 17:46:48 -0600 Subject: [PATCH 5/7] ahbsdc submodule actually added this time. --- .gitmodules | 2 +- addins/ahbsdc | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) create mode 160000 addins/ahbsdc diff --git a/.gitmodules b/.gitmodules index 54d9dd970..054afa6fb 100644 --- a/.gitmodules +++ b/.gitmodules @@ -25,7 +25,7 @@ url = https://github.com/Digilent/vivado-boards/ [submodule "addins/ahbsdc"] path = addins/ahbsdc - url = https://github.com/JacobPease/ahbsdc.git + url = git@github.com:jacobpease/ahbsdc.git [submodule "addins/riscv-arch-test"] path = addins/riscv-arch-test url = https://github.com/riscv-non-isa/riscv-arch-test diff --git a/addins/ahbsdc b/addins/ahbsdc new file mode 160000 index 000000000..5df21aa66 --- /dev/null +++ b/addins/ahbsdc @@ -0,0 +1 @@ +Subproject commit 5df21aa6625eca120e64ea353ca641aff37d90b2 From 8cbd3de41338eb8d0331156933a66518fe9ef67e Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Sat, 18 Nov 2023 19:01:39 -0600 Subject: [PATCH 6/7] Fixed Zicclsm bug. Misalignment and spill detection were not masked by access type. Therefore a page table walk which always aligned could have had an IEUAdrM misaligned which erroneously caused a shift in the read data. --- src/lsu/align.sv | 57 +++++++++++++++++++++++++----------------------- src/lsu/lsu.sv | 2 +- 2 files changed, 31 insertions(+), 28 deletions(-) diff --git a/src/lsu/align.sv b/src/lsu/align.sv index 573b7e50f..ce704a316 100644 --- a/src/lsu/align.sv +++ b/src/lsu/align.sv @@ -30,33 +30,34 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module align import cvw::*; #(parameter cvw_t P) ( - input logic clk, - input logic reset, - input logic StallM, FlushM, - input logic [P.XLEN-1:0] IEUAdrM, // 2 byte aligned PC in Fetch stage - input logic [P.XLEN-1:0] IEUAdrE, // The next IEUAdrM - input logic [2:0] Funct3M, // Size of memory operation - input logic [1:0] MemRWM, - input logic CacheableM, - input logic [P.LLEN*2-1:0]DCacheReadDataWordM, // Instruction from the IROM, I$, or bus. Used to check if the instruction if compressed - input logic CacheBusHPWTStall, // I$ or bus are stalled. Transition to second fetch of spill after the first is fetched - input logic DTLBMissM, // ITLB miss, ignore memory request - input logic DataUpdateDAM, // ITLB miss, ignore memory request + input logic clk, + input logic reset, + input logic StallM, FlushM, + input logic [P.XLEN-1:0] IEUAdrM, // 2 byte aligned PC in Fetch stage + input logic [P.XLEN-1:0] IEUAdrE, // The next IEUAdrM + input logic [2:0] Funct3M, // Size of memory operation + input logic [1:0] MemRWM, + input logic CacheableM, + input logic [P.LLEN*2-1:0] DCacheReadDataWordM, // Instruction from the IROM, I$, or bus. Used to check if the instruction if compressed + input logic CacheBusHPWTStall, // I$ or bus are stalled. Transition to second fetch of spill after the first is fetched + input logic DTLBMissM, // ITLB miss, ignore memory request + input logic DataUpdateDAM, // ITLB miss, ignore memory request + input logic SelHPTW, - input logic [(P.LLEN-1)/8:0] ByteMaskM, - input logic [(P.LLEN-1)/8:0] ByteMaskExtendedM, - input logic [P.LLEN-1:0] LSUWriteDataM, + input logic [(P.LLEN-1)/8:0] ByteMaskM, + input logic [(P.LLEN-1)/8:0] ByteMaskExtendedM, + input logic [P.LLEN-1:0] LSUWriteDataM, output logic [(P.LLEN*2-1)/8:0] ByteMaskSpillM, - output logic [P.LLEN*2-1:0] LSUWriteDataSpillM, + output logic [P.LLEN*2-1:0] LSUWriteDataSpillM, - output logic [P.XLEN-1:0] IEUAdrSpillE, // The next PCF for one of the two memory addresses of the spill - output logic [P.XLEN-1:0] IEUAdrSpillM, // IEUAdrM for one of the two memory addresses of the spill - output logic SelSpillE, // During the transition between the two spill operations, the IFU should stall the pipeline - output logic [1:0] MemRWSpillM, - output logic SelStoreDelay, //*** this is bad. really don't like moving this outside - output logic [P.LLEN-1:0] DCacheReadDataWordSpillM, // The final 32 bit instruction after merging the two spilled fetches into 1 instruction - output logic SpillStallM); + output logic [P.XLEN-1:0] IEUAdrSpillE, // The next PCF for one of the two memory addresses of the spill + output logic [P.XLEN-1:0] IEUAdrSpillM, // IEUAdrM for one of the two memory addresses of the spill + output logic SelSpillE, // During the transition between the two spill operations, the IFU should stall the pipeline + output logic [1:0] MemRWSpillM, + output logic SelStoreDelay, //*** this is bad. really don't like moving this outside + output logic [P.LLEN-1:0] DCacheReadDataWordSpillM, // The final 32 bit instruction after merging the two spilled fetches into 1 instruction + output logic SpillStallM); localparam LLENINBYTES = P.LLEN/8; localparam OFFSET_BIT_POS = $clog2(P.DCACHE_LINELENINBITS/8); @@ -83,6 +84,7 @@ module align import cvw::*; #(parameter cvw_t P) ( logic [$clog2(LLENINBYTES)-1:0] ByteOffsetM; logic HalfSpillM, WordSpillM; logic [$clog2(LLENINBYTES)-1:0] AccessByteOffsetM; + logic ValidAccess; /* verilator lint_off WIDTHEXPAND */ assign IEUAdrIncrementM = IEUAdrM + LLENINBYTES; @@ -116,17 +118,18 @@ module align import cvw::*; #(parameter cvw_t P) ( assign WordMisalignedM = (ByteOffsetM[1:0] != '0) & Funct3M[1:0] == 2'b10; assign HalfSpillM = (IEUAdrM[OFFSET_BIT_POS-1:1] == '1) & HalfMisalignedM; assign WordSpillM = (IEUAdrM[OFFSET_BIT_POS-1:2] == '1) & WordMisalignedM; + assign ValidAccess = (|MemRWM) & ~SelHPTW; if(P.LLEN == 64) begin logic DoubleSpillM; logic DoubleMisalignedM; assign DoubleMisalignedM = (ByteOffsetM[2:0] != '0) & Funct3M[1:0] == 2'b11; assign DoubleSpillM = (IEUAdrM[OFFSET_BIT_POS-1:3] == '1) & DoubleMisalignedM; - assign MisalignedM = HalfMisalignedM | WordMisalignedM | DoubleMisalignedM; - assign SpillM = (|MemRWM) & CacheableM & (HalfSpillM | WordSpillM | DoubleSpillM); + assign MisalignedM = ValidAccess & (HalfMisalignedM | WordMisalignedM | DoubleMisalignedM); + assign SpillM = ValidAccess & CacheableM & (HalfSpillM | WordSpillM | DoubleSpillM); end else begin - assign SpillM = (|MemRWM) & CacheableM & (HalfSpillM | WordSpillM); - assign MisalignedM = HalfMisalignedM | WordMisalignedM; + assign SpillM = ValidAccess & CacheableM & (HalfSpillM | WordSpillM); + assign MisalignedM = ValidAccess & (HalfMisalignedM | WordMisalignedM); end // align by shifting diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index ba7d8e119..ebda946a4 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -158,7 +158,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( logic [P.XLEN-1:0] IEUAdrSpillE, IEUAdrSpillM; align #(P) align(.clk, .reset, .StallM, .FlushM, .IEUAdrE, .IEUAdrM, .Funct3M, .MemRWM, .CacheableM, - .DCacheReadDataWordM, .CacheBusHPWTStall, .DTLBMissM, .DataUpdateDAM, + .DCacheReadDataWordM, .CacheBusHPWTStall, .DTLBMissM, .DataUpdateDAM, .SelHPTW, .ByteMaskM, .ByteMaskExtendedM, .LSUWriteDataM, .ByteMaskSpillM, .LSUWriteDataSpillM, .IEUAdrSpillE, .IEUAdrSpillM, .SelSpillE, .MemRWSpillM, .DCacheReadDataWordSpillM, .SpillStallM, .SelStoreDelay); From 87e6a5ccf2b16c4fa956a506f252c87cc477b1bb Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Sat, 18 Nov 2023 19:15:39 -0600 Subject: [PATCH 7/7] Updated ROM to preload bootloader from file and infer a block ram when building for FPGA. --- fpga/constraints/marked_debug.txt | 1 + fpga/src/boot.mem | 513 ++++++++++++++++++++++++++++++ src/generic/mem/rom1p1r.sv | 22 +- 3 files changed, 529 insertions(+), 7 deletions(-) create mode 100644 fpga/src/boot.mem diff --git a/fpga/constraints/marked_debug.txt b/fpga/constraints/marked_debug.txt index 3973fc451..7d5636f31 100644 --- a/fpga/constraints/marked_debug.txt +++ b/fpga/constraints/marked_debug.txt @@ -45,6 +45,7 @@ ifu/ifu.sv: logic PCPF ifu/ifu.sv: logic PostSpillInstrRawF mmu/hptw.sv: logic ITLBWriteF mmu/hptw.sv: statetype WalkerState +mmu/hptw.sv: logic ValidPTE privileged/csrs.sv: logic CSRSReadValM privileged/csrs.sv: logic SEPC_REGW privileged/csrs.sv: logic MIP_REGW diff --git a/fpga/src/boot.mem b/fpga/src/boot.mem new file mode 100644 index 000000000..4ad2f0657 --- /dev/null +++ b/fpga/src/boot.mem @@ -0,0 +1,513 @@ +8001819300002197 +4281420141014081 +4481440143814301 +4681460145814501 +4881480147814701 +4a814a0149814901 +4c814c014b814b01 +4e814e014d814d01 +0110011b4f814f01 +059b45011161016e +0004063705fe0010 +1f6000ef8006061b +0ff003930000100f +4e952e3110060e37 +c602829b0053f2b7 +2023fe02dfe312fd +829b0053f2b7007e +fe02dfe312fdc602 +4de31efd000e2023 +059bf1402573fdd0 +0000061705e20870 +0010029b01260613 +68110002806702fe +0085179bf0080813 +038008130107f7b3 +480508a86c632781 +1533357902a87963 +38030000181700a8 +1c6301057833f268 +081a403018370808 +0105783342280813 +1815751308081063 +00367513c295e14d +654ded510207e793 +c1701ff00613f130 +0637c530fff6861b +664dcd10167d0200 +17fd001007b7c25c +859b5a5cc20cd21c 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+0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +0000000000000000 +00600100d2e3ca40 diff --git a/src/generic/mem/rom1p1r.sv b/src/generic/mem/rom1p1r.sv index 93f8c82df..5a45e354a 100644 --- a/src/generic/mem/rom1p1r.sv +++ b/src/generic/mem/rom1p1r.sv @@ -33,7 +33,7 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, DATA_WIDTH = 32, PRELOAD_ENABLED = 0) ); // Core Memory - logic [DATA_WIDTH-1:0] ROM [(2**ADDR_WIDTH)-1:0]; + (*rom_style="block" *) logic [DATA_WIDTH-1:0] ROM [(2**ADDR_WIDTH)-1:0]; // dh 10/30/23 ROM macros are presently commented out // because they don't point to a generated ROM @@ -41,15 +41,23 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, DATA_WIDTH = 32, PRELOAD_ENABLED = 0) rom1p1r_128x64 rom1 (.CLK(clk), .CEB(~ce), .A(addr[6:0]), .Q(dout)); end if ((`USE_SRAM == 1) & (ADDR_WDITH == 7) & (DATA_WIDTH == 32)) begin - rom1p1r_128x32 rom1 (.CLK(clk), .CEB(~ce), .A(addr[6:0]), .Q(dout)); + rom1p1r_128x32 rom1 (.CLK(clk), .CEB(~ce), .A(addr[6:0]), .Q(dout)); - end else begin */ - always @ (posedge clk) - if(ce) dout <= ROM[addr]; + end else begin */ + + initial begin + if (PRELOAD_ENABLED) begin + $readmemh("../../../fpga/src/boot.mem", ROM, 0); + end + end + + always @ (posedge clk) begin + if(ce) dout <= ROM[addr]; + end // for FPGA, initialize with zero-stage bootloader - if(PRELOAD_ENABLED) begin + /*if(PRELOAD_ENABLED) begin initial begin ROM[0]=64'h8001819300002197; ROM[1]=64'h4281420141014081; @@ -195,6 +203,6 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, DATA_WIDTH = 32, PRELOAD_ENABLED = 0) ROM[141]=64'h0000808241010113; end // if (PRELOAD_ENABLED) - end + end*/ endmodule