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	Added cause_s_soft_from_m_interrupt
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				@ -162,6 +162,11 @@ cause_s_soft_interrupt:
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    csrs sip, t3 // set supervisor software interrupt pending. SIP is a subset of MIP, so writing this should also change MIP.
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    ret
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cause_s_soft_from_m_interrupt:
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    li t3, 0x2
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    csrs mip, t3 // set supervisor software interrupt pending. SIP is a subset of MIP, so writing this should also change MIP.
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    ret
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cause_m_ext_interrupt:
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    // ========== Configure PLIC ==========
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    li a3, 0x40
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