From 6f15ae1225b2faa83611397f64743bac23ac6800 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 22 Mar 2023 23:08:39 -0700 Subject: [PATCH] Added cause_s_soft_from_m_interrupt --- .../rv64i_m/privilege/src/WALLY-TEST-LIB-64.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h index 00e235f35..85b5ab8c4 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h @@ -162,6 +162,11 @@ cause_s_soft_interrupt: csrs sip, t3 // set supervisor software interrupt pending. SIP is a subset of MIP, so writing this should also change MIP. ret +cause_s_soft_from_m_interrupt: + li t3, 0x2 + csrs mip, t3 // set supervisor software interrupt pending. SIP is a subset of MIP, so writing this should also change MIP. + ret + cause_m_ext_interrupt: // ========== Configure PLIC ========== li a3, 0x40