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https://github.com/openhwgroup/cvw
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Fixed another bug in the btb.
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d2b7047744
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@ -144,7 +144,7 @@ module bpred (
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// BTB contains target address for all CFI
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// BTB contains target address for all CFI
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btb #(`BTB_SIZE)
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btb #(`BTB_SIZE)
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TargetPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
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TargetPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
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.PCNextF, .PCF, .PCD, .PCE, .PCM,
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.PCNextF, .PCF, .PCD, .PCE, .PCM,
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.PredPCF,
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.PredPCF,
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.BTBPredInstrClassF,
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.BTBPredInstrClassF,
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@ -33,7 +33,7 @@
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module btb #(parameter Depth = 10 ) (
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module btb #(parameter Depth = 10 ) (
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input logic clk,
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input logic clk,
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input logic reset,
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input logic reset,
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input logic StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM,
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input logic StallF, StallD, StallE, StallM, StallW, FlushD, FlushE, FlushM, FlushW,
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input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, // PC at various stages
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input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, // PC at various stages
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output logic [`XLEN-1:0] PredPCF, // BTB's guess at PC
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output logic [`XLEN-1:0] PredPCF, // BTB's guess at PC
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output logic [3:0] BTBPredInstrClassF, // BTB's guess at instruction class
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output logic [3:0] BTBPredInstrClassF, // BTB's guess at instruction class
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@ -93,7 +93,7 @@ module btb #(parameter Depth = 10 ) (
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// An optimization may be using a PC relative address.
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// An optimization may be using a PC relative address.
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ram2p1r1wbe #(2**Depth, `XLEN+4) memory(
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ram2p1r1wbe #(2**Depth, `XLEN+4) memory(
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.clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredictionF),
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.clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredictionF),
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.ce2(~StallM & ~FlushM), .wa2(PCMIndex), .wd2({InstrClassM, IEUAdrM}), .we2(UpdateEn), .bwe2('1));
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.ce2(~StallW & ~FlushW), .wa2(PCMIndex), .wd2({InstrClassM, IEUAdrM}), .we2(UpdateEn), .bwe2('1));
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flopenrc #(`XLEN) BTBD(clk, reset, FlushD, ~StallD, PredPCF, PredPCD);
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flopenrc #(`XLEN) BTBD(clk, reset, FlushD, ~StallD, PredPCF, PredPCD);
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@ -83,7 +83,7 @@ module gshareForward #(parameter k = 10) (
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.rd1(TableDirPredictionF),
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.rd1(TableDirPredictionF),
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.wa2(IndexM),
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.wa2(IndexM),
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.wd2(NewDirPredictionM),
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.wd2(NewDirPredictionM),
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.we2(BranchInstrM & ~StallW & ~FlushW),
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.we2(BranchInstrM),
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.bwe2(1'b1));
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.bwe2(1'b1));
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flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, DirPredictionF, DirPredictionD);
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flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, DirPredictionF, DirPredictionD);
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@ -102,7 +102,7 @@ module gshareForward #(parameter k = 10) (
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assign GHRNext = BranchInstrM ? {PCSrcM, GHR[k-1:1]} : GHR;
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assign GHRNext = BranchInstrM ? {PCSrcM, GHR[k-1:1]} : GHR;
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assign GHRM = GHR;
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assign GHRM = GHR;
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flopenr #(k) GHRReg(clk, reset, ~StallM & ~FlushM & BranchInstrM, GHRNext, GHR);
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flopenr #(k) GHRReg(clk, reset, ~StallW & ~FlushW & BranchInstrM, GHRNext, GHR);
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flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
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flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
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endmodule
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endmodule
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@ -50,8 +50,8 @@ string tvpaths[] = '{
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string embench[] = '{
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string embench[] = '{
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`EMBENCH,
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`EMBENCH,
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"bd_speedopt_speed/src/cubic/cubic", // cubic is likely going to removed when embench 2.0 launches
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"bd_speedopt_speed/src/nsichneu/nsichneu",
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"bd_speedopt_speed/src/nsichneu/nsichneu",
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"bd_speedopt_speed/src/cubic/cubic", // cubic is likely going to removed when embench 2.0 launches
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"bd_speedopt_speed/src/aha-mont64/aha-mont64",
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"bd_speedopt_speed/src/aha-mont64/aha-mont64",
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"bd_speedopt_speed/src/crc32/crc32",
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"bd_speedopt_speed/src/crc32/crc32",
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"bd_speedopt_speed/src/edn/edn",
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"bd_speedopt_speed/src/edn/edn",
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