From 6eefa5b1e35d7ad3e66b97c443a545d5f91dfcb7 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 20 Feb 2023 17:54:22 -0600 Subject: [PATCH] Fixed another bug in the btb. --- src/ifu/bpred/bpred.sv | 2 +- src/ifu/bpred/btb.sv | 4 ++-- src/ifu/bpred/gshareForward.sv | 4 ++-- testbench/tests.vh | 2 +- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index 97101a3ea..b0ea2683b 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -144,7 +144,7 @@ module bpred ( // BTB contains target address for all CFI btb #(`BTB_SIZE) - TargetPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, + TargetPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .PCNextF, .PCF, .PCD, .PCE, .PCM, .PredPCF, .BTBPredInstrClassF, diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv index a8f67efeb..8e2d0e259 100644 --- a/src/ifu/bpred/btb.sv +++ b/src/ifu/bpred/btb.sv @@ -33,7 +33,7 @@ module btb #(parameter Depth = 10 ) ( input logic clk, input logic reset, - input logic StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM, + input logic StallF, StallD, StallE, StallM, StallW, FlushD, FlushE, FlushM, FlushW, input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, // PC at various stages output logic [`XLEN-1:0] PredPCF, // BTB's guess at PC output logic [3:0] BTBPredInstrClassF, // BTB's guess at instruction class @@ -93,7 +93,7 @@ module btb #(parameter Depth = 10 ) ( // An optimization may be using a PC relative address. ram2p1r1wbe #(2**Depth, `XLEN+4) memory( .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredictionF), - .ce2(~StallM & ~FlushM), .wa2(PCMIndex), .wd2({InstrClassM, IEUAdrM}), .we2(UpdateEn), .bwe2('1)); + .ce2(~StallW & ~FlushW), .wa2(PCMIndex), .wd2({InstrClassM, IEUAdrM}), .we2(UpdateEn), .bwe2('1)); flopenrc #(`XLEN) BTBD(clk, reset, FlushD, ~StallD, PredPCF, PredPCD); diff --git a/src/ifu/bpred/gshareForward.sv b/src/ifu/bpred/gshareForward.sv index 77ab90fba..57bcd4bee 100644 --- a/src/ifu/bpred/gshareForward.sv +++ b/src/ifu/bpred/gshareForward.sv @@ -83,7 +83,7 @@ module gshareForward #(parameter k = 10) ( .rd1(TableDirPredictionF), .wa2(IndexM), .wd2(NewDirPredictionM), - .we2(BranchInstrM & ~StallW & ~FlushW), + .we2(BranchInstrM), .bwe2(1'b1)); flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, DirPredictionF, DirPredictionD); @@ -102,7 +102,7 @@ module gshareForward #(parameter k = 10) ( assign GHRNext = BranchInstrM ? {PCSrcM, GHR[k-1:1]} : GHR; assign GHRM = GHR; - flopenr #(k) GHRReg(clk, reset, ~StallM & ~FlushM & BranchInstrM, GHRNext, GHR); + flopenr #(k) GHRReg(clk, reset, ~StallW & ~FlushW & BranchInstrM, GHRNext, GHR); flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM); endmodule diff --git a/testbench/tests.vh b/testbench/tests.vh index 6ab4533fa..2ec4e43fc 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -50,8 +50,8 @@ string tvpaths[] = '{ string embench[] = '{ `EMBENCH, - "bd_speedopt_speed/src/cubic/cubic", // cubic is likely going to removed when embench 2.0 launches "bd_speedopt_speed/src/nsichneu/nsichneu", + "bd_speedopt_speed/src/cubic/cubic", // cubic is likely going to removed when embench 2.0 launches "bd_speedopt_speed/src/aha-mont64/aha-mont64", "bd_speedopt_speed/src/crc32/crc32", "bd_speedopt_speed/src/edn/edn",