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https://github.com/openhwgroup/cvw
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sucessfully simulate first 30 instructions
still need to find a better solution to InstrAccessFault/DataAccessFault though
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@ -37,15 +37,6 @@ module testbench_busybear #(parameter XLEN=64, MISA=32'h00000104, ZCSR = 1, ZCOU
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$display("file couldn't be opened");
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$display("file couldn't be opened");
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$stop;
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$stop;
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end
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end
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// scan_file = $fscanf(data_file, "%x\n", read_data);
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// $display("%x", read_data);
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// scan_file = $fscanf(data_file, "%s\n", read_data);
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// $display("%s", read_data);
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// //if (!$feof(data_file)) begin
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// // $display(read_data);
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// //end
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// end
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end
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end
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// read register trace file
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// read register trace file
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@ -98,18 +89,39 @@ module testbench_busybear #(parameter XLEN=64, MISA=32'h00000104, ZCSR = 1, ZCOU
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end
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end
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end
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end
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logic speculative, nextSpec;
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initial begin
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speculative = 0;
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nextSpec = 0;
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end
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always @(PCF) begin
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always @(PCF) begin
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speculative <= nextSpec;
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if (speculative) begin
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speculative <= (PCF != pcExpected);
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end
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if (~speculative) begin
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// first read instruction
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// first read instruction
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scan_file_PC = $fscanf(data_file_PC, "%x\n", InstrF);
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scan_file_PC = $fscanf(data_file_PC, "%x\n", InstrF);
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// then expected PC value
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// then expected PC value
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scan_file_PC = $fscanf(data_file_PC, "%x\n", pcExpected);
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scan_file_PC = $fscanf(data_file_PC, "%x\n", pcExpected);
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// are we at a branch/jump?
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case (InstrF[6:0]) //todo: add C versions of these
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7'b1101111, //JAL
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7'b1100111, //JALR
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7'b1100011: //B
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nextSpec <= 1;
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default:
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nextSpec <= 0;
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endcase
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//check things!
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//check things!
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if (PCF !== pcExpected) begin
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if ((~nextSpec) && (PCF !== pcExpected)) begin
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$display("%t ps: PC does not equal PC expected: %x, %x", $time, PCF, pcExpected);
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$display("%t ps: PC does not equal PC expected: %x, %x", $time, PCF, pcExpected);
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// $stop;
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// $stop;
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end
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end
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end
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end
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end
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// Track names of instructions
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// Track names of instructions
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string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
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string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
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