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https://github.com/openhwgroup/cvw
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Merge pull request #726 from Karl-Han/wsim_verilator
Add Verilator to Wsim support
This commit is contained in:
commit
6d464157f7
2
.gitignore
vendored
2
.gitignore
vendored
@ -1,5 +1,7 @@
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**/work*
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**/wally_*.log
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/**/obj_dir*
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/**/gmon*
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.nfs*
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4
bin/wsim
4
bin/wsim
@ -65,6 +65,8 @@ if (args.sim == "questa"):
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print("Running Questa with command: " + cmd)
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os.system(cmd)
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elif (args.sim == "verilator"):
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print("Running Verilator on %s %s", args.config, args.testsuite)
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# PWD=${WALLY}/sim CONFIG=rv64gc TESTSUITE=arch64i
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print(f"Running Verilator on {args.config} {args.testsuite}")
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os.system(f"/usr/bin/make -C {regressionDir}/verilator WALLYCONF={args.config} TEST={args.testsuite}")
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elif (args.sim == "vcs"):
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print("Running VCS on %s %s", args.config, args.testsuite)
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@ -36,7 +36,6 @@ obj_dir_non_profiling/Vtestbench_$(WALLYCONF): $(SOURCE)
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"-I${WALLY}/config/shared" "-I${WALLY}/config/$(WALLYCONF)" \
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wrapper.c \
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${WALLY}/src/cvw.sv ${WALLY}/testbench/testbench.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv
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obj_dir_profiling/Vtestbench_$(WALLYCONF): $(SOURCE)
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mkdir -p obj_dir_profiling
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32
sim/verilator/README.md
Normal file
32
sim/verilator/README.md
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# Simulation with Verilator
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Different executables will be built for different architecture configurations, e.g., rv64gc, rv32i. A executable can run all the test suites that it can run with `+TEST=<testsuite>`.
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Demand:
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- Avoid unnecessary compilation by sharing the same executable for a specific configuration
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- executables are stored in `obj_dir_non_profiling` and `obj_dir_profiling` correspondingly
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- Wsim should support `-s verilator` option and run simulation with Verilator.
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## Folder Structure
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This folder contains the following files that help the simulation of Wally with Verilator:
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- Makefile: simplify the usage with Verialtor
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- executables
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- `obj_dir_non_profiling`: non-profiling executables for different configurations
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- `obj_dir_profiling`: profiling executables for different configurations
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- logs in `logs` and `logs_profiling` correspondingly
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- [NOT WORKING] `logs`: contains all the logs
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## Examples
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```shell
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# non-profiling mode
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make WALLYCONF=rv64gc TEST=arch64i run
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# profiling mode
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make WALLYCONF=rv64gc TEST=arch64i profile
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# remove all the temporary files, including executables and logs
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make clean
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```
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@ -1,42 +0,0 @@
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#!/bin/bash
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# simulate with Verilator
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export PATH=$PATH:/usr/local/bin/
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verilator=`which verilator`
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basepath=$(dirname $0)/..
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#for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i rv64fpquad; do
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# define associateive array of tests to run
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declare -A suites
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rv64gccases=("arch64zba" "arch64zbb" "arch64zbc" "arch64zbs" "arch64i" "arch64m" "arch64a" "arch64f" "arch64d" "arch64c" "arch64f_fma" "arch64d_fma" "wally64priv")
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suites["rv64gc"]=${rv64gccases[@]}
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rv64icases=("arch64i")
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suites["rv64i"]=${rv32icases[@]}
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rv32gccases=("arch32zba" "arch32zbb" "arch32zbc" "arch32zbs" "arch32i" "arch32m" "arch32a" "arch32f" "arch32d" "arch32c" "arch64f_fma" "arch64d_fma" "wally32priv")
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suites["rv32gc"]=${rv32gccases[@]}
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rv32imccases=("arch32i" "arch32m" "arch32c")
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suites["rv32imc"]=${rv32imccases[@]}
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rv32icases=("arch32i")
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suites["rv32i"]=${rv32icases[@]}
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rv32ecases=("arch32e")
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suites["rv32e"]=${rv32ecases[@]}
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for config in ${!suites[@]}; do
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for suite in ${suites[${config}]}; do
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echo "Verilating ${config} ${suite}"
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if !($verilator --timescale "1ns/1ns" --timing --binary "$@" -GTEST="\"${suite}\"" --top-module testbench "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/cvw.sv $basepath/testbench/testbench.sv $basepath/testbench/common/*.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
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echo "Exiting after ${config} ${suite} verilation due to errors or warnings"
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exit 1
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fi
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./obj_dir/Vtestbench
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done
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done
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echo "Verilation complete"
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# command line to invoke Verilator on rv64gc arch64i
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# verilator -GTEST="\"arch64i\"" --timescale "1ns/1ns" --timing --binary --top-module testbench "-I../config/shared" "-I../config/rv64gc" ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv --relative-includes
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# command line with debugging to address core dumps
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# verilator -CFLAGS -DVL_DEBUG -CFLAGS -D_GLIBCXX_DEBUG -CFLAGS -ggdb -LDFLAGS -ggdb -CFLAGS -fsanitize=address,undefined -LDFLAGS -fsanitize=address,undefined --timescale "1ns/1ns" --timing --binary --top-module testbench "-I../config/shared" "-I../config/rv64gc" ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv --relative-includes
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@ -321,13 +321,18 @@ module testbench;
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end_signature_addr = ProgramAddrLabelArray["sig_end_canary"];
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signature_size = end_signature_addr - begin_signature_addr;
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end
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logic EcallFaultM;
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if (P.ZICSR_SUPPORTED)
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assign EcallFaultM = dut.core.priv.priv.EcallFaultM;
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else
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assign EcallFaultM = 0;
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always @(posedge clk) begin
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////////////////////////////////////////////////////////////////////////////////
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// Verify the test ran correctly by checking the memory against a known signature.
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////////////////////////////////////////////////////////////////////////////////
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if(TestBenchReset) test = 1;
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if (P.ZICSR_SUPPORTED & TEST == "coremark")
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if (dut.core.priv.priv.EcallFaultM) begin
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if (EcallFaultM) begin
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$display("Benchmark: coremark is done.");
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$stop;
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end
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@ -863,11 +868,16 @@ end
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// Check errors
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testadr = ($unsigned(begin_signature_addr))/(P.XLEN/8);
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testadrNoBase = (begin_signature_addr - P.UNCORE_RAM_BASE)/(P.XLEN/8);
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// logic UNCORE_RAM_SUPPORTED;
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// if(P.UNCORE_RAM_SUPPORTED)
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// assign UNCORE_RAM_SUPPORTED = P.UNCORE_RAM_SUPPORTED;
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// else
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// assign UNCORE_RAM_SUPPORTED = 0;
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for (i=0; i<sigentries; i++) begin
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logic [P.XLEN-1:0] sig;
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// **************************************
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// ***** BUG BUG BUG make sure RT undoes this.
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//if (P.DTIM_SUPPORTED) sig = testbench.dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i];
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//else if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncoregen.uncore.ram.ram.memory.RAM[testadrNoBase+i];
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if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncoregen.uncore.ram.ram.memory.RAM[testadrNoBase+i];
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//if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncoregen.uncore.ram.ram.memory.RAM[testadrNoBase+i];
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@ -875,8 +885,10 @@ end
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//if (signature[i] !== sig & (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i])) begin
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if (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i]) begin
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errors = errors+1;
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$display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h",
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TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]);
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// $display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h",
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// TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]);
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$display(" Error on test %s result %d: adr = %h sim (D$) %h signature = %h",
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TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], signature[i]);
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$stop; // if this is changed to $finish, wally-batch.do does not get to the next step to run coverage
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end
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end
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