Merge pull request #726 from Karl-Han/wsim_verilator

Add Verilator to Wsim support

.gitignore

@@ -1,5 +1,7 @@
 **/work*
 **/wally_*.log
+/**/obj_dir*
+/**/gmon*
 
 .nfs*
 

bin/wsim

@@ -65,6 +65,8 @@ if (args.sim == "questa"):
     print("Running Questa with command: " + cmd)
     os.system(cmd)
 elif (args.sim == "verilator"):
-    print("Running Verilator on %s %s", args.config, args.testsuite)
+    # PWD=${WALLY}/sim CONFIG=rv64gc TESTSUITE=arch64i
+    print(f"Running Verilator on {args.config} {args.testsuite}")
+    os.system(f"/usr/bin/make -C {regressionDir}/verilator WALLYCONF={args.config} TEST={args.testsuite}")
 elif (args.sim == "vcs"):
     print("Running VCS on %s %s", args.config, args.testsuite)

sim/verilator/Makefile

@@ -36,7 +36,6 @@ obj_dir_non_profiling/Vtestbench_$(WALLYCONF): $(SOURCE)
 	"-I${WALLY}/config/shared" "-I${WALLY}/config/$(WALLYCONF)" \
 	wrapper.c \
 	${WALLY}/src/cvw.sv ${WALLY}/testbench/testbench.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv
-
 	
 obj_dir_profiling/Vtestbench_$(WALLYCONF): $(SOURCE)
 	mkdir -p obj_dir_profiling

sim/verilator/README.md

@@ -0,0 +1,32 @@
+# Simulation with Verilator
+
+Different executables will be built for different architecture configurations, e.g., rv64gc, rv32i. A executable can run all the test suites that it can run with `+TEST=<testsuite>`.
+
+Demand:
+
+- Avoid unnecessary compilation by sharing the same executable for a specific configuration
+    - executables are stored in `obj_dir_non_profiling` and `obj_dir_profiling` correspondingly
+- Wsim should support `-s verilator` option and run simulation with Verilator.
+
+## Folder Structure
+
+This folder contains the following files that help the simulation of Wally with Verilator:
+
+- Makefile: simplify the usage with Verialtor
+- executables
+    - `obj_dir_non_profiling`: non-profiling executables for different configurations
+    - `obj_dir_profiling`: profiling executables for different configurations
+- logs in `logs` and `logs_profiling` correspondingly
+- [NOT WORKING] `logs`: contains all the logs
+
+## Examples
+
+```shell
+# non-profiling mode
+make WALLYCONF=rv64gc TEST=arch64i run
+# profiling mode
+make WALLYCONF=rv64gc TEST=arch64i profile
+
+# remove all the temporary files, including executables and logs
+make clean
+```

sim/verilator/verilate

@@ -1,42 +0,0 @@
-#!/bin/bash
-# simulate with Verilator
-
-export PATH=$PATH:/usr/local/bin/
-verilator=`which verilator`
-
-basepath=$(dirname $0)/..
-#for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i rv64fpquad; do
-
-# define associateive array of tests to run
-declare -A suites
-rv64gccases=("arch64zba" "arch64zbb" "arch64zbc" "arch64zbs" "arch64i" "arch64m" "arch64a" "arch64f" "arch64d" "arch64c" "arch64f_fma" "arch64d_fma" "wally64priv")
-suites["rv64gc"]=${rv64gccases[@]}
-rv64icases=("arch64i")
-suites["rv64i"]=${rv32icases[@]}
-rv32gccases=("arch32zba" "arch32zbb" "arch32zbc" "arch32zbs" "arch32i" "arch32m" "arch32a" "arch32f" "arch32d" "arch32c" "arch64f_fma" "arch64d_fma" "wally32priv")
-suites["rv32gc"]=${rv32gccases[@]}
-rv32imccases=("arch32i" "arch32m" "arch32c")
-suites["rv32imc"]=${rv32imccases[@]}
-rv32icases=("arch32i")
-suites["rv32i"]=${rv32icases[@]}
-rv32ecases=("arch32e")
-suites["rv32e"]=${rv32ecases[@]}
-
-for config in ${!suites[@]}; do
-    for suite in ${suites[${config}]}; do
-        echo "Verilating ${config} ${suite}"
-        if !($verilator --timescale "1ns/1ns" --timing --binary "$@" -GTEST="\"${suite}\"" --top-module testbench "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/cvw.sv $basepath/testbench/testbench.sv $basepath/testbench/common/*.sv   $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
-            echo "Exiting after ${config} ${suite} verilation due to errors or warnings"
-            exit 1
-        fi
-        ./obj_dir/Vtestbench 
-    done
-done
-echo "Verilation complete"
-
-# command line to invoke Verilator on rv64gc arch64i
-# verilator -GTEST="\"arch64i\"" --timescale "1ns/1ns" --timing --binary --top-module testbench "-I../config/shared" "-I../config/rv64gc" ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv --relative-includes
-
-# command line with debugging to address core dumps
-# verilator -CFLAGS -DVL_DEBUG -CFLAGS -D_GLIBCXX_DEBUG -CFLAGS -ggdb -LDFLAGS -ggdb -CFLAGS -fsanitize=address,undefined -LDFLAGS -fsanitize=address,undefined --timescale "1ns/1ns" --timing --binary --top-module testbench "-I../config/shared" "-I../config/rv64gc" ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv --relative-includes
-

testbench/testbench.sv

@@ -321,13 +321,18 @@ module testbench;
  	end_signature_addr = ProgramAddrLabelArray["sig_end_canary"];
   	signature_size = end_signature_addr - begin_signature_addr;
   end
+  logic EcallFaultM;
+  if (P.ZICSR_SUPPORTED)
+    assign EcallFaultM = dut.core.priv.priv.EcallFaultM;
+  else
+    assign EcallFaultM = 0;
   always @(posedge clk) begin
     ////////////////////////////////////////////////////////////////////////////////
     // Verify the test ran correctly by checking the memory against a known signature.
     ////////////////////////////////////////////////////////////////////////////////
     if(TestBenchReset) test = 1;
     if (P.ZICSR_SUPPORTED & TEST == "coremark")
-      if (dut.core.priv.priv.EcallFaultM) begin
+      if (EcallFaultM) begin
         $display("Benchmark: coremark is done.");
         $stop;
       end
@@ -863,11 +868,16 @@ end
     // Check errors
     testadr = ($unsigned(begin_signature_addr))/(P.XLEN/8);
     testadrNoBase = (begin_signature_addr - P.UNCORE_RAM_BASE)/(P.XLEN/8);
+    // logic UNCORE_RAM_SUPPORTED;
+    // if(P.UNCORE_RAM_SUPPORTED)
+    //   assign UNCORE_RAM_SUPPORTED = P.UNCORE_RAM_SUPPORTED;
+    // else
+    //   assign UNCORE_RAM_SUPPORTED = 0;
     for (i=0; i<sigentries; i++) begin
-      logic [P.XLEN-1:0] sig;
       // **************************************
       // ***** BUG BUG BUG make sure RT undoes this.
       //if (P.DTIM_SUPPORTED) sig = testbench.dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i];
+
       //else if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncoregen.uncore.ram.ram.memory.RAM[testadrNoBase+i];
       if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncoregen.uncore.ram.ram.memory.RAM[testadrNoBase+i];
       //if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncoregen.uncore.ram.ram.memory.RAM[testadrNoBase+i];
@@ -875,8 +885,10 @@ end
       //if (signature[i] !== sig & (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i])) begin
       if (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i]) begin  
         errors = errors+1;
-        $display("  Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h", 
-			     TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]);
+        // $display("  Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h", 
+			  //    TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]);
+        $display("  Error on test %s result %d: adr = %h sim (D$) %h signature = %h", 
+			     TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], signature[i]);
         $stop; // if this is changed to $finish, wally-batch.do does not get to the next step to run coverage
       end
     end