From e25177cf4c69bb30f3396a177da35edaa390a8df Mon Sep 17 00:00:00 2001 From: Kunlin Han Date: Thu, 11 Apr 2024 20:02:20 -0700 Subject: [PATCH 1/3] Add verilator support for wsim. --- .gitignore | 2 ++ bin/wsim | 4 +++- sim/verilator/Makefile | 45 +++++++++++++++++++++++++++++++++++++++++ sim/verilator/README.md | 19 +++++++++++++++++ sim/verilator/verilate | 42 -------------------------------------- 5 files changed, 69 insertions(+), 43 deletions(-) create mode 100644 sim/verilator/Makefile create mode 100644 sim/verilator/README.md delete mode 100755 sim/verilator/verilate diff --git a/.gitignore b/.gitignore index fc32b283a..a77e4dac2 100644 --- a/.gitignore +++ b/.gitignore @@ -1,5 +1,7 @@ **/work* **/wally_*.log +/**/obj_dir* +/**/gmon* .nfs* diff --git a/bin/wsim b/bin/wsim index 7e386e4a3..0796c51cd 100755 --- a/bin/wsim +++ b/bin/wsim @@ -65,6 +65,8 @@ if (args.sim == "questa"): print("Running Questa with command: " + cmd) os.system(cmd) elif (args.sim == "verilator"): - print("Running Verilator on %s %s", args.config, args.testsuite) + # PWD=${WALLY}/sim CONFIG=rv64gc TESTSUITE=arch64i + print(f"Running Verilator on {args.config} {args.testsuite}") + os.system(f"/usr/bin/make -C {regressionDir}/verilator WALLYCONF={args.config} TEST={args.testsuite}") elif (args.sim == "vcs"): print("Running VCS on %s %s", args.config, args.testsuite) diff --git a/sim/verilator/Makefile b/sim/verilator/Makefile new file mode 100644 index 000000000..bba4b6bb9 --- /dev/null +++ b/sim/verilator/Makefile @@ -0,0 +1,45 @@ +.PHONY: profile run questa clean + +OPT= +PARAMS?=-DVERILATOR=1 --no-trace-top +NONPROF?=--stats +WORKING_DIR=${WALLY}/sim/verilator +TARGET=$(WORKING_DIR)/target +SOURCE=${WALLY}/config/shared/*.vh ${WALLY}/config/${WALLYCONF} ${WALLY}/src/cvw.sv ${WALLY}/testbench/testbench.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv + +WALLYCONF?=rv64gc +TEST?=arch64i + +default: run + +profile: obj_dir_profiling/Vtestbench_$(WALLYCONF) + $(WORKING_DIR)/obj_dir_profiling/Vtestbench_$(WALLYCONF) +TEST=$(TEST) + mv gmon.out gmon_$(WALLYCONF).out + gprof $(WORKING_DIR)/obj_dir_profiling/Vtestbench_$(WALLYCONF) gmon_$(WALLYCONF).out > gmon_$(WALLYCONF).log + verilator_profcfunc gmon_$(WALLYCONF).log > gmon_$(WALLYCONF).log2 + +run: obj_dir_non_profiling/Vtestbench_$(WALLYCONF) + time $(WORKING_DIR)/obj_dir_non_profiling/Vtestbench_$(WALLYCONF) +TEST=$(TEST) + +obj_dir_non_profiling/Vtestbench_$(WALLYCONF): $(SOURCE) + mkdir -p obj_dir_non_profiling + time verilator \ + --Mdir obj_dir_non_profiling -o Vtestbench_$(WALLYCONF) \ + $(OPT) $(PARAMS) $(NONPROF) \ + --timescale "1ns/1ns" --timing --binary --top-module testbench --relative-includes \ + "-I${WALLY}/config/shared" "-I${WALLY}/config/$(WALLYCONF)" \ + ${WALLY}/src/cvw.sv ${WALLY}/testbench/testbench.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv + +obj_dir_profiling/Vtestbench_$(WALLYCONF): $(SOURCE) + mkdir -p obj_dir_profiling + time verilator \ + --Mdir obj_dir_profiling -o Vtestbench_$(WALLYCONF) \ + --prof-cfuncs $(OPT) $(PARAMS) \ + --timescale "1ns/1ns" --timing --binary --top-module testbench --relative-includes \ + "-I${WALLY}/config/shared" "-I${WALLY}/config/$(WALLYCONF)" ${WALLY}/src/cvw.sv ${WALLY}/testbench/testbench.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv + +questa: + time vsim -c -do "do ${WALLY}/sim/wally-batch.do $(WALLYCONF) $(TEST)" + +clean: + rm -rf $(WORKING_DIR)/obj_dir_non_profiling $(WORKING_DIR)/obj_dir_profiling \ No newline at end of file diff --git a/sim/verilator/README.md b/sim/verilator/README.md new file mode 100644 index 000000000..8f239e9d0 --- /dev/null +++ b/sim/verilator/README.md @@ -0,0 +1,19 @@ +# Simulation with Verilator + +Different executables will be built for different architecture configurations, e.g., rv64gc, rv32i. A executable can run all the test suites that it can run with `+TEST=`. + +This folder contains the following files that help the simulation of Wally with Verilator: + +- executables + - `obj_dir_non_profiling`: non-profiling executables for different configurations + - `obj_dir_profiling`: profiling executables for different configurations +- [NOT WORKING] `logs`: contains all the logs + +## Examples + +```shell +# non-profiling mode +make WALLYCONF=rv64gc TEST=arch64i run +# profiling mode +make WALLYCONF=rv64gc TEST=arch64i profile +``` \ No newline at end of file diff --git a/sim/verilator/verilate b/sim/verilator/verilate deleted file mode 100755 index 23eb115e1..000000000 --- a/sim/verilator/verilate +++ /dev/null @@ -1,42 +0,0 @@ -#!/bin/bash -# simulate with Verilator - -export PATH=$PATH:/usr/local/bin/ -verilator=`which verilator` - -basepath=$(dirname $0)/.. -#for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i rv64fpquad; do - -# define associateive array of tests to run -declare -A suites -rv64gccases=("arch64zba" "arch64zbb" "arch64zbc" "arch64zbs" "arch64i" "arch64m" "arch64a" "arch64f" "arch64d" "arch64c" "arch64f_fma" "arch64d_fma" "wally64priv") -suites["rv64gc"]=${rv64gccases[@]} -rv64icases=("arch64i") -suites["rv64i"]=${rv32icases[@]} -rv32gccases=("arch32zba" "arch32zbb" "arch32zbc" "arch32zbs" "arch32i" "arch32m" "arch32a" "arch32f" "arch32d" "arch32c" "arch64f_fma" "arch64d_fma" "wally32priv") -suites["rv32gc"]=${rv32gccases[@]} -rv32imccases=("arch32i" "arch32m" "arch32c") -suites["rv32imc"]=${rv32imccases[@]} -rv32icases=("arch32i") -suites["rv32i"]=${rv32icases[@]} -rv32ecases=("arch32e") -suites["rv32e"]=${rv32ecases[@]} - -for config in ${!suites[@]}; do - for suite in ${suites[${config}]}; do - echo "Verilating ${config} ${suite}" - if !($verilator --timescale "1ns/1ns" --timing --binary "$@" -GTEST="\"${suite}\"" --top-module testbench "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/cvw.sv $basepath/testbench/testbench.sv $basepath/testbench/common/*.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then - echo "Exiting after ${config} ${suite} verilation due to errors or warnings" - exit 1 - fi - ./obj_dir/Vtestbench - done -done -echo "Verilation complete" - -# command line to invoke Verilator on rv64gc arch64i -# verilator -GTEST="\"arch64i\"" --timescale "1ns/1ns" --timing --binary --top-module testbench "-I../config/shared" "-I../config/rv64gc" ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv --relative-includes - -# command line with debugging to address core dumps -# verilator -CFLAGS -DVL_DEBUG -CFLAGS -D_GLIBCXX_DEBUG -CFLAGS -ggdb -LDFLAGS -ggdb -CFLAGS -fsanitize=address,undefined -LDFLAGS -fsanitize=address,undefined --timescale "1ns/1ns" --timing --binary --top-module testbench "-I../config/shared" "-I../config/rv64gc" ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv --relative-includes - From a55bb01d1d9512c444b4a193908f551aedece9eb Mon Sep 17 00:00:00 2001 From: Kunlin Han Date: Thu, 11 Apr 2024 20:16:13 -0700 Subject: [PATCH 2/3] Update README and put logs in the right places. --- sim/verilator/Makefile | 9 +++++++-- sim/verilator/README.md | 13 +++++++++++++ 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/sim/verilator/Makefile b/sim/verilator/Makefile index bba4b6bb9..8b08e275d 100644 --- a/sim/verilator/Makefile +++ b/sim/verilator/Makefile @@ -17,9 +17,14 @@ profile: obj_dir_profiling/Vtestbench_$(WALLYCONF) mv gmon.out gmon_$(WALLYCONF).out gprof $(WORKING_DIR)/obj_dir_profiling/Vtestbench_$(WALLYCONF) gmon_$(WALLYCONF).out > gmon_$(WALLYCONF).log verilator_profcfunc gmon_$(WALLYCONF).log > gmon_$(WALLYCONF).log2 + mkdir -p $(WORKING_DIR)/logs_profiling + mv gmon_$(WALLYCONF)* $(WORKING_DIR)/logs_profiling + echo "Please check $(WORKING_DIR)/logs_profiling/gmon_$(WALLYCONF)* for logs and output files." run: obj_dir_non_profiling/Vtestbench_$(WALLYCONF) - time $(WORKING_DIR)/obj_dir_non_profiling/Vtestbench_$(WALLYCONF) +TEST=$(TEST) + mkdir -p $(WORKING_DIR)/logs + time $(WORKING_DIR)/obj_dir_non_profiling/Vtestbench_$(WALLYCONF) +TEST=$(TEST) 2>&1 > $(WORKING_DIR)/logs/$(WALLYCONF)_$(TEST).log + echo "Please check $(WORKING_DIR)/logs/$(WALLYCONF)_$(TEST).log for logs and output files." obj_dir_non_profiling/Vtestbench_$(WALLYCONF): $(SOURCE) mkdir -p obj_dir_non_profiling @@ -42,4 +47,4 @@ questa: time vsim -c -do "do ${WALLY}/sim/wally-batch.do $(WALLYCONF) $(TEST)" clean: - rm -rf $(WORKING_DIR)/obj_dir_non_profiling $(WORKING_DIR)/obj_dir_profiling \ No newline at end of file + rm -rf $(WORKING_DIR)/obj_dir_non_profiling $(WORKING_DIR)/obj_dir_profiling $(WORKING_DIR)/logs $(WORKING_DIR)/logs_profiling \ No newline at end of file diff --git a/sim/verilator/README.md b/sim/verilator/README.md index 8f239e9d0..5fd1b57b3 100644 --- a/sim/verilator/README.md +++ b/sim/verilator/README.md @@ -2,11 +2,21 @@ Different executables will be built for different architecture configurations, e.g., rv64gc, rv32i. A executable can run all the test suites that it can run with `+TEST=`. +Demand: + +- Avoid unnecessary compilation by sharing the same executable for a specific configuration + - executables are stored in `obj_dir_non_profiling` and `obj_dir_profiling` correspondingly +- Wsim should support `-s verilator` option and run simulation with Verilator. + +## Folder Structure + This folder contains the following files that help the simulation of Wally with Verilator: +- Makefile: simplify the usage with Verialtor - executables - `obj_dir_non_profiling`: non-profiling executables for different configurations - `obj_dir_profiling`: profiling executables for different configurations +- logs in `logs` and `logs_profiling` correspondingly - [NOT WORKING] `logs`: contains all the logs ## Examples @@ -16,4 +26,7 @@ This folder contains the following files that help the simulation of Wally with make WALLYCONF=rv64gc TEST=arch64i run # profiling mode make WALLYCONF=rv64gc TEST=arch64i profile + +# remove all the temporary files, including executables and logs +make clean ``` \ No newline at end of file From eeb5c591431a599b5c7959f2ca657e2a120205a1 Mon Sep 17 00:00:00 2001 From: Kunlin Han Date: Fri, 12 Apr 2024 16:06:10 -0700 Subject: [PATCH 3/3] Remove unnecessary sig and avoid uninitialized signal inside always block. --- testbench/testbench.sv | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 3a4eeb617..cd7a6ad3b 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -321,13 +321,18 @@ module testbench; end_signature_addr = ProgramAddrLabelArray["sig_end_canary"]; signature_size = end_signature_addr - begin_signature_addr; end + logic EcallFaultM; + if (P.ZICSR_SUPPORTED) + assign EcallFaultM = dut.core.priv.priv.EcallFaultM; + else + assign EcallFaultM = 0; always @(posedge clk) begin //////////////////////////////////////////////////////////////////////////////// // Verify the test ran correctly by checking the memory against a known signature. //////////////////////////////////////////////////////////////////////////////// if(TestBenchReset) test = 1; if (P.ZICSR_SUPPORTED & TEST == "coremark") - if (dut.core.priv.priv.EcallFaultM) begin + if (EcallFaultM) begin $display("Benchmark: coremark is done."); $stop; end @@ -861,20 +866,25 @@ end // Check errors testadr = ($unsigned(begin_signature_addr))/(P.XLEN/8); testadrNoBase = (begin_signature_addr - P.UNCORE_RAM_BASE)/(P.XLEN/8); + // logic UNCORE_RAM_SUPPORTED; + // if(P.UNCORE_RAM_SUPPORTED) + // assign UNCORE_RAM_SUPPORTED = P.UNCORE_RAM_SUPPORTED; + // else + // assign UNCORE_RAM_SUPPORTED = 0; for (i=0; i