Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Revert "intdivble changes"

Browse Source 
This reverts commit 3618c6c593.
This commit is contained in:
Kevin Kim 2024-06-28 21:28:09 -07:00
parent 3618c6c593
commit 6cb6ff429b
3 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/fpu/fdivsqrt/fdivsqrt.sv
View File

@ -67,7 +67,7 @@ module fdivsqrt import cvw::*; #(parameter cvw_t P) (
// Integer div/rem signals
logic BZeroM; // Denominator is zero
logic [P.INTDIVBLEN-1:0] IntNormShiftM; // Integer normalizatoin shift amount
logic [P.DIVBLEN-1:0] IntNormShiftM; // Integer normalizatoin shift amount
logic ALTBM, AsM, BsM, W64M; // Special handling for postprocessor
logic [P.XLEN-1:0] AM; // Original Numerator for postprocessor
logic ISpecialCaseE; // Integer div/remainder special cases

2
src/fpu/fdivsqrt/fdivsqrtpostproc.sv
View File

@ -38,7 +38,7 @@ module fdivsqrtpostproc import cvw::*; #(parameter cvw_t P) (
input logic SqrtM, SpecialCaseM,
input logic [P.XLEN-1:0] AM, // U/Q(XLEN.0)
input logic RemOpM, ALTBM, BZeroM, AsM, BsM, W64M,
input logic [P.INTDIVBLEN-1:0] IntNormShiftM,
input logic [P.DIVBLEN-1:0] IntNormShiftM,
output logic [P.DIVb:0] UmM, // U1.DIVb result significand
output logic WZeroE,
output logic DivStickyM,

4
src/fpu/fdivsqrt/fdivsqrtpreproc.sv
View File

@ -57,7 +57,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
logic [P.NE+1:0] UeE; // Result Exponent (FP only)
logic [P.DIVb:0] IFX, IFD; // Correctly-sized inputs for iterator, selected from int or fp input
logic [P.DIVBLEN-1:0] mE, ell; // Leading zeros of inputs
logic [P.INTDIVBLEN-1:0] IntResultBitsE; // bits in integer result
logic [P.DIVBLEN-1:0] IntResultBitsE; // bits in integer result
logic AZeroE, BZeroE; // A or B is Zero for integer division
logic SignedDivE; // signed division
logic AsE, BsE; // Signs of integer inputs
@ -214,7 +214,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
fdivsqrtcycles #(P) cyclecalc(.Nf, .IntDivE, .IntResultBitsE, .CyclesE);
if (P.IDIV_ON_FPU) begin:intpipelineregs
logic [P.INTDIVBLEN-1:0] IntDivNormShiftE, IntRemNormShiftE, IntNormShiftE;
logic [P.DIVBLEN-1:0] IntDivNormShiftE, IntRemNormShiftE, IntNormShiftE;
logic RemOpE;
/* verilator lint_off WIDTH */