From 6cb6ff429be6b9e5ee9c1e7e77816f579ca31801 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 28 Jun 2024 21:28:09 -0700 Subject: [PATCH] Revert "intdivble changes" This reverts commit 3618c6c593d4d29db97d48614cd914f9b5c934ca. --- src/fpu/fdivsqrt/fdivsqrt.sv | 2 +- src/fpu/fdivsqrt/fdivsqrtpostproc.sv | 2 +- src/fpu/fdivsqrt/fdivsqrtpreproc.sv | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/fpu/fdivsqrt/fdivsqrt.sv b/src/fpu/fdivsqrt/fdivsqrt.sv index 8aa9b59c7..2a43b2d91 100644 --- a/src/fpu/fdivsqrt/fdivsqrt.sv +++ b/src/fpu/fdivsqrt/fdivsqrt.sv @@ -67,7 +67,7 @@ module fdivsqrt import cvw::*; #(parameter cvw_t P) ( // Integer div/rem signals logic BZeroM; // Denominator is zero - logic [P.INTDIVBLEN-1:0] IntNormShiftM; // Integer normalizatoin shift amount + logic [P.DIVBLEN-1:0] IntNormShiftM; // Integer normalizatoin shift amount logic ALTBM, AsM, BsM, W64M; // Special handling for postprocessor logic [P.XLEN-1:0] AM; // Original Numerator for postprocessor logic ISpecialCaseE; // Integer div/remainder special cases diff --git a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv index 10d9e038f..869b06f74 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv @@ -38,7 +38,7 @@ module fdivsqrtpostproc import cvw::*; #(parameter cvw_t P) ( input logic SqrtM, SpecialCaseM, input logic [P.XLEN-1:0] AM, // U/Q(XLEN.0) input logic RemOpM, ALTBM, BZeroM, AsM, BsM, W64M, - input logic [P.INTDIVBLEN-1:0] IntNormShiftM, + input logic [P.DIVBLEN-1:0] IntNormShiftM, output logic [P.DIVb:0] UmM, // U1.DIVb result significand output logic WZeroE, output logic DivStickyM, diff --git a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv index cdc076ae4..737d9089a 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv @@ -57,7 +57,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) ( logic [P.NE+1:0] UeE; // Result Exponent (FP only) logic [P.DIVb:0] IFX, IFD; // Correctly-sized inputs for iterator, selected from int or fp input logic [P.DIVBLEN-1:0] mE, ell; // Leading zeros of inputs - logic [P.INTDIVBLEN-1:0] IntResultBitsE; // bits in integer result + logic [P.DIVBLEN-1:0] IntResultBitsE; // bits in integer result logic AZeroE, BZeroE; // A or B is Zero for integer division logic SignedDivE; // signed division logic AsE, BsE; // Signs of integer inputs @@ -214,7 +214,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) ( fdivsqrtcycles #(P) cyclecalc(.Nf, .IntDivE, .IntResultBitsE, .CyclesE); if (P.IDIV_ON_FPU) begin:intpipelineregs - logic [P.INTDIVBLEN-1:0] IntDivNormShiftE, IntRemNormShiftE, IntNormShiftE; + logic [P.DIVBLEN-1:0] IntDivNormShiftE, IntRemNormShiftE, IntNormShiftE; logic RemOpE; /* verilator lint_off WIDTH */