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Merge pull request #621 from davidharrishmc/dev

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fixed two-bit bpred configurations in derivlist.txt
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Rose Thompson 2024-02-07 09:05:30 -06:00 committed by GitHub
commit 6cad6657e0
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5 changed files with 36 additions and 25 deletions
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12
config/derivlist.txt
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@ -328,22 +328,22 @@ deriv bpred_GSHARE_16_16_10_0_rv32gc bpred_GSHARE_16_16_10_1_rv32gc
INSTR_CLASS_PRED 0 INSTR_CLASS_PRED 0
deriv bpred_TWOBIT_6_16_10_0_rv32gc bpred_GSHARE_6_16_10_0_rv32gc deriv bpred_TWOBIT_6_16_10_0_rv32gc bpred_GSHARE_6_16_10_0_rv32gc
INSTR_CLASS_PRED 0 BPRED_TYPE `BP_TWOBIT
deriv bpred_TWOBIT_8_16_10_0_rv32gc bpred_GSHARE_8_16_10_0_rv32gc deriv bpred_TWOBIT_8_16_10_0_rv32gc bpred_GSHARE_8_16_10_0_rv32gc
INSTR_CLASS_PRED 0 BPRED_TYPE `BP_TWOBIT
deriv bpred_TWOBIT_10_16_10_0_rv32gc bpred_GSHARE_10_16_10_0_rv32gc deriv bpred_TWOBIT_10_16_10_0_rv32gc bpred_GSHARE_10_16_10_0_rv32gc
INSTR_CLASS_PRED 0 BPRED_TYPE `BP_TWOBIT
deriv bpred_TWOBIT_12_16_10_0_rv32gc bpred_GSHARE_12_16_10_0_rv32gc deriv bpred_TWOBIT_12_16_10_0_rv32gc bpred_GSHARE_12_16_10_0_rv32gc
INSTR_CLASS_PRED 0 BPRED_TYPE `BP_TWOBIT
deriv bpred_TWOBIT_14_16_10_0_rv32gc bpred_GSHARE_14_16_10_0_rv32gc deriv bpred_TWOBIT_14_16_10_0_rv32gc bpred_GSHARE_14_16_10_0_rv32gc
INSTR_CLASS_PRED 0 BPRED_TYPE `BP_TWOBIT
deriv bpred_TWOBIT_16_16_10_0_rv32gc bpred_GSHARE_16_16_10_0_rv32gc deriv bpred_TWOBIT_16_16_10_0_rv32gc bpred_GSHARE_16_16_10_0_rv32gc
INSTR_CLASS_PRED 0 BPRED_TYPE `BP_TWOBIT
deriv bpred_GSHARE_10_2_10_0_rv32gc bpred_GSHARE_10_2_10_1_rv32gc deriv bpred_GSHARE_10_2_10_0_rv32gc bpred_GSHARE_10_2_10_1_rv32gc
INSTR_CLASS_PRED 0 INSTR_CLASS_PRED 0

5
src/fpu/fctrl.sv
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@ -237,11 +237,10 @@ module fctrl import cvw::*; #(parameter cvw_t P) (
5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1_0; // fcvt.l.q q->l 5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1_0; // fcvt.l.q q->l
5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1_0; // fcvt.lu.q q->lu 5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1_0; // fcvt.lu.q q->lu
endcase endcase
// coverage on // coverage off
// Not covered in testing because rv64gc is not RV64Q or RV32D
7'b1011001: if (P.ZFA_SUPPORTED & P.XLEN == 32 & P.D_SUPPORTED & Funct3D == 3'b000) 7'b1011001: if (P.ZFA_SUPPORTED & P.XLEN == 32 & P.D_SUPPORTED & Funct3D == 3'b000)
ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0; // fmvp.d.x (Zfa) *** untested, controls could be wrong ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0; // fmvp.d.x (Zfa) *** untested, controls could be wrong
// Not covered in testing because rv64gc does not support quad precision
// coverage off
7'b1011011: if (P.ZFA_SUPPORTED & P.XLEN == 64 & P.Q_SUPPORTED & Funct3D == 3'b000) 7'b1011011: if (P.ZFA_SUPPORTED & P.XLEN == 64 & P.Q_SUPPORTED & Funct3D == 3'b000)
ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0; // fmvp.q.x (Zfa) ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0; // fmvp.q.x (Zfa)
// coverage on // coverage on

6
testbench/testbench.sv
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@ -310,7 +310,7 @@ module testbench;
if (TEST == "coremark") if (TEST == "coremark")
if (dut.core.priv.priv.EcallFaultM) begin if (dut.core.priv.priv.EcallFaultM) begin
$display("Benchmark: coremark is done."); $display("Benchmark: coremark is done.");
$finish; $stop;
end end
if(Validate) begin if(Validate) begin
if (TEST == "embench") begin if (TEST == "embench") begin
@ -347,7 +347,7 @@ module testbench;
if (test == tests.size()) begin if (test == tests.size()) begin
if (totalerrors == 0) $display("SUCCESS! All tests ran without failures."); if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");
else $display("FAIL: %d test programs had errors", totalerrors); else $display("FAIL: %d test programs had errors", totalerrors);
$finish; $stop; // if this is changed to $finish, wally-batch.do does not go to the next step to run coverage
end end
end end
end end
@ -631,7 +631,7 @@ module testbench;
errors = errors+1; errors = errors+1;
$display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h", $display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h",
TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]); TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]);
$finish; $stop; // if this is changed to $finish, wally-batch.do does not get to the next step to run coverage
end end
end end
if (errors) $display("%s failed with %d errors. :(", TestName, errors); if (errors) $display("%s failed with %d errors. :(", TestName, errors);

16
testbench/tests.vh
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@ -1134,10 +1134,10 @@ string imperas32f[] = '{
string arch64zfh_fma[] = '{ string arch64zfh_fma[] = '{
`RISCVARCHTEST, `RISCVARCHTEST,
//"rv64i_m/F/src/fmadd_b15-01.S", "rv64i_m/Zfh/src/fmadd_b15-01.S",
"rv64i_m/Zfh/src/fmsub_b15-01.S" "rv64i_m/Zfh/src/fmsub_b15-01.S",
// "rv64i_m/F/src/fnmadd_b15-01.S", "rv64i_m/Zfh/src/fnmadd_b15-01.S",
// "rv64i_m/F/src/fnmsub_b15-01.S" "rv64i_m/Zfh/src/fnmsub_b15-01.S"
}; };
string arch64f_divsqrt[] = '{ string arch64f_divsqrt[] = '{
@ -2178,10 +2178,10 @@ string arch64zbs[] = '{
string arch32zfh_fma[] = '{ string arch32zfh_fma[] = '{
`RISCVARCHTEST, `RISCVARCHTEST,
//"rv32i_m/D/src/fmadd.d_b15-01.S", "rv32i_m/Zfh/src/fmadd_b15-01.S",
//"rv32i_m/D/src/fmsub.d_b15-01.S", "rv32i_m/Zfh/src/fmsub_b15-01.S",
// "rv32i_m/D/src/fnmadd.d_b15-01.S", "rv32i_m/Zfh/src/fnmadd_b15-01.S",
"rv32i_m/Zfh/src/fnmsub.d_b15-01.S" "rv32i_m/Zfh/src/fnmsub_b15-01.S"
}; };
string arch32d_divsqrt[] = '{ string arch32d_divsqrt[] = '{

20
tests/coverage/fpu.S
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@ -40,12 +40,24 @@ main:
# zfa instructions (because Zfa tests aren't running yet) # zfa instructions (because Zfa tests aren't running yet)
fli.d fs0, 16 fli.d fs0, 16
fcvtmod.w.d t0, fs0, rtz fcvtmod.w.d t0, fs0, rtz
fminm.d fs1, fs0, fs0 # fminm.d fs1, fs0, fs0
fmaxm.d fs1, fs0, fs0 # fmaxm.d fs1, fs0, fs0
# fltq.d t0, fs1, ft0
# fleq.d t0, fs1, ft0
fcvt.d.q fs1, fs0
fcvt.h.q fs1, fs0
fcvt.s.q fs1, fs0
# round for now because these tests are excluded from Zfa until rounding is implemented
fround.s fs1, fs0
froundnx.s fs1, fs0
fround.d fs1, fs0 fround.d fs1, fs0
froundnx.d fs1, fs0 froundnx.d fs1, fs0
fltq.d t0, fs1, ft0 fround.h fs1, fs0
fleq.d t0, fs1, ft0 froundnx.h fs1, fs0
fround.s fs1, fs0
froundnx.s fs1, fs0
fmvp.d.x
#Result Sign Test Coverage #Result Sign Test Coverage
la t0, TestData2 la t0, TestData2