From 3bea7bb4313ae8204c34d40e86d3814c7b68afdc Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Wed, 2 Mar 2022 17:28:20 +0000
Subject: [PATCH 1/2] removed imperas-riscv-tests

---
 pipelined/src/fma/fma16_template.sv | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)
 create mode 100644 pipelined/src/fma/fma16_template.sv

diff --git a/pipelined/src/fma/fma16_template.sv b/pipelined/src/fma/fma16_template.sv
new file mode 100644
index 000000000..70d06a771
--- /dev/null
+++ b/pipelined/src/fma/fma16_template.sv
@@ -0,0 +1,24 @@
+// fma16.sv
+// David_Harris@hmc.edu 26 February 2022
+// 16-bit floating-point multiply-accumulate
+
+// Operation: general purpose multiply, add, fma, with optional negation
+//   If mul=1, p = x * y.  Else p = x.
+//   If add=1, result = p + z.  Else result = p.
+//   If negr or negz = 1, negate result or z to handle negations and subtractions
+//   fadd: mul = 0, add = 1, negr = negz = 0
+//   fsub: mul = 0, add = 1, negr = 0, negz = 1
+//   fmul: mul = 1, add = 0, negr = 0, negz = 0
+//   fmadd:  mul = 1, add = 1, negr = 0, negz = 0
+//   fmsub:  mul = 1, add = 1, negr = 0, negz = 1
+//   fnmadd: mul = 1, add = 1, negr = 1, negz = 0
+//   fnmsub: mul = 1, add = 1, negr = 1, negz = 1
+
+module fma16(
+  input  logic [15:0] x, y, z,
+  input  logic        mul, add, negr, negz,
+  input  logic [1:0]  roundmode,  // 00: rz, 01: rne, 10: rp, 11: rn
+  output logic [15:0] result);
+ 
+endmodule
+