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Modified IROM to return the correct offset when unaligned.

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This commit is contained in:
Ross Thompson 2022-12-30 11:48:40 -06:00
parent 5d844801d2
commit 6ac7adbfc4
2 changed files with 12 additions and 5 deletions
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15
pipelined/src/ifu/irom.sv
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@ -41,12 +41,19 @@ module irom(
logic [`XLEN-1:0] ReadDataFull; logic [`XLEN-1:0] ReadDataFull;
rom1p1r #(ADDR_WDITH, `XLEN) rom(.clk, .ce, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataFull)); rom1p1r #(ADDR_WDITH, `XLEN) rom(.clk, .ce, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataFull));
if (`XLEN == 32) assign ReadData = ReadDataFull; if (`XLEN == 32) begin
logic AdrD;
flopen #(1) AdrReg(clk, ce, Adr[1], AdrD);
assign ReadData = AdrD ? {16'b0, ReadDataFull[31:16]} : ReadDataFull;
end
// have to delay Ardr[OFFSET-1] by 1 cycle // have to delay Ardr[OFFSET-1] by 1 cycle
else begin else begin
logic AdrD; logic [OFFSET-2:0] AdrD;
flopen #(1) AdrReg(clk, ce, Adr[OFFSET-1], AdrD); flopen #(OFFSET-1) AdrReg(clk, ce, Adr[OFFSET-1:1], AdrD);
assign ReadData = AdrD ? ReadDataFull[63:32] : ReadDataFull[31:0]; assign ReadData = AdrD == 2'b11 ? {16'b0, ReadDataFull[63:48]} :
AdrD == 2'b10 ? ReadDataFull[63:32] :
AdrD == 2'b01 ? ReadDataFull[47:16] :
ReadDataFull[31:0];
end end
endmodule endmodule

2
pipelined/src/ifu/spillsupport.sv
View File

@ -92,7 +92,7 @@ module spillsupport #(parameter CACHE_ENABLED)
flopenr #(16) SpillInstrReg(.clk(clk), flopenr #(16) SpillInstrReg(.clk(clk),
.en(SpillSaveF & ~Flush), .en(SpillSaveF & ~Flush),
.reset(reset), .reset(reset),
.d(SavedInstr), .d(InstrRawF[15:0]),
.q(SpillDataLine0)); .q(SpillDataLine0));
mux2 #(32) postspillmux(.d0(InstrRawF), .d1({InstrRawF[15:0], SpillDataLine0}), .s(SpillF), mux2 #(32) postspillmux(.d0(InstrRawF), .d1({InstrRawF[15:0], SpillDataLine0}), .s(SpillF),