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fix name of DSCR that I mistakenly made

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This commit is contained in:
James Stine 2024-06-03 16:42:05 -05:00
parent 77ec3d58c6
commit 6a7f145de2
2 changed files with 8 additions and 8 deletions
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10
src/ifu/ifu.sv
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@ -145,7 +145,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
logic [LINELEN-1:0] FetchBuffer; logic [LINELEN-1:0] FetchBuffer;
logic [31:0] ShiftUncachedInstr; logic [31:0] ShiftUncachedInstr;
// Debug scan chain // Debug scan chain
logic DB_SCR; logic DSCR;
assign PCFExt = {2'b00, PCSpillF}; assign PCFExt = {2'b00, PCSpillF};
@ -411,12 +411,12 @@ module ifu import cvw::*; #(parameter cvw_t P) (
if (P.ZICSR_SUPPORTED | P.A_SUPPORTED) begin if (P.ZICSR_SUPPORTED | P.A_SUPPORTED) begin
mux2 #(32) FlushInstrMMux(InstrE, nop, FlushM, NextInstrE); mux2 #(32) FlushInstrMMux(InstrE, nop, FlushM, NextInstrE);
if (P.DEBUG_SUPPORTED) if (P.DEBUG_SUPPORTED)
flopenrs #(32) InstrMReg(clk, reset, ~StallM, NextInstrE, InstrM, DebugScanEn, DB_SCR, DebugScanOut); flopenrs #(32) InstrMReg(clk, reset, ~StallM, NextInstrE, InstrM, DebugScanEn, DSCR, DebugScanOut);
else else
flopenr #(32) InstrMReg(clk, reset, ~StallM, NextInstrE, InstrM); flopenr #(32) InstrMReg(clk, reset, ~StallM, NextInstrE, InstrM);
end else begin end else begin
assign InstrM = '0; assign InstrM = '0;
assign DebugScanOut = DB_SCR; assign DebugScanOut = DSCR;
end end
// FIXME: delete once working // FIXME: delete once working
@ -426,12 +426,12 @@ module ifu import cvw::*; #(parameter cvw_t P) (
// PCM is only needed with CSRs or branch prediction // PCM is only needed with CSRs or branch prediction
if (P.ZICSR_SUPPORTED | P.BPRED_SUPPORTED) if (P.ZICSR_SUPPORTED | P.BPRED_SUPPORTED)
if (P.DEBUG_SUPPORTED) if (P.DEBUG_SUPPORTED)
flopenrs #(P.XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM, DebugScanEn, DebugScanIn, DB_SCR); flopenrs #(P.XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM, DebugScanEn, DebugScanIn, DSCR);
else else
flopenr #(P.XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM); flopenr #(P.XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM);
else begin else begin
assign PCM = '0; assign PCM = '0;
assign DB_SCR = DebugScanIn; assign DSCR = DebugScanIn;
end end
// FIXME: delete once working // FIXME: delete once working

6
src/lsu/lsu.sv
View File

@ -155,7 +155,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
logic [P.XLEN-1:0] WriteDataZM; logic [P.XLEN-1:0] WriteDataZM;
logic LSULoadPageFaultM, LSUStoreAmoPageFaultM; logic LSULoadPageFaultM, LSUStoreAmoPageFaultM;
logic DB_SCR; // Debug Register Scan In logic DSCR; // Debug Register Scan In
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////
// Pipeline for IEUAdr E to M // Pipeline for IEUAdr E to M
@ -163,7 +163,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////
if (P.DEBUG_SUPPORTED) if (P.DEBUG_SUPPORTED)
flopenrcs #(P.XLEN) AddressMReg(.clk, .reset, .clear(FlushM), .en(~StallM), .d(IEUAdrE), .q(IEUAdrM), .scan(DebugScanEn), .scanin(DebugScanIn), .scanout(DB_SCR)); flopenrcs #(P.XLEN) AddressMReg(.clk, .reset, .clear(FlushM), .en(~StallM), .d(IEUAdrE), .q(IEUAdrM), .scan(DebugScanEn), .scanin(DebugScanIn), .scanout(DSCR));
else else
flopenrc #(P.XLEN) AddressMReg(.clk, .reset, .clear(FlushM), .en(~StallM), .d(IEUAdrE), .q(IEUAdrM)); flopenrc #(P.XLEN) AddressMReg(.clk, .reset, .clear(FlushM), .en(~StallM), .d(IEUAdrE), .q(IEUAdrM));
@ -433,7 +433,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
// Capture ReadDataM // Capture ReadDataM
if (P.DEBUG_SUPPORTED) begin if (P.DEBUG_SUPPORTED) begin
flopenrs #(P.LLEN) ReadDataMScan (.clk, .reset, .en(DebugCapture), .d(ReadDataM), .q(), .scan(DebugScanEn), .scanin(DB_SCR), .scanout(DebugScanOut)); flopenrs #(P.LLEN) ReadDataMScan (.clk, .reset, .en(DebugCapture), .d(ReadDataM), .q(), .scan(DebugScanEn), .scanin(DSCR), .scanout(DebugScanOut));
end end
// Compute byte masks // Compute byte masks