From 6a7f145de240fa5e798a5a3a51e359bc8d7da723 Mon Sep 17 00:00:00 2001
From: James Stine <james.stine@okstate.edu>
Date: Mon, 3 Jun 2024 16:42:05 -0500
Subject: [PATCH] fix name of DSCR that I mistakenly made

---
 src/ifu/ifu.sv | 10 +++++-----
 src/lsu/lsu.sv |  6 +++---
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv
index 14a3e6cd4..d5d2f093f 100644
--- a/src/ifu/ifu.sv
+++ b/src/ifu/ifu.sv
@@ -145,7 +145,7 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
   logic [LINELEN-1:0]          FetchBuffer;
   logic [31:0]                 ShiftUncachedInstr;
   // Debug scan chain                                                                                                                
-  logic                        DB_SCR;
+  logic                        DSCR;
   
   assign PCFExt = {2'b00, PCSpillF};
 
@@ -411,12 +411,12 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
   if (P.ZICSR_SUPPORTED | P.A_SUPPORTED) begin
     mux2    #(32)     FlushInstrMMux(InstrE, nop, FlushM, NextInstrE);
     if (P.DEBUG_SUPPORTED)
-      flopenrs #(32)     InstrMReg(clk, reset, ~StallM, NextInstrE, InstrM, DebugScanEn, DB_SCR, DebugScanOut);
+      flopenrs #(32)     InstrMReg(clk, reset, ~StallM, NextInstrE, InstrM, DebugScanEn, DSCR, DebugScanOut);
     else
       flopenr #(32)     InstrMReg(clk, reset, ~StallM, NextInstrE, InstrM);
   end else begin
     assign InstrM = '0;
-    assign DebugScanOut = DB_SCR;
+    assign DebugScanOut = DSCR;
   end
 
   // FIXME: delete once working
@@ -426,12 +426,12 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
   // PCM is only needed with CSRs or branch prediction
   if (P.ZICSR_SUPPORTED | P.BPRED_SUPPORTED)
      if (P.DEBUG_SUPPORTED)
-      flopenrs #(P.XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM, DebugScanEn, DebugScanIn, DB_SCR);
+      flopenrs #(P.XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM, DebugScanEn, DebugScanIn, DSCR);
     else
       flopenr #(P.XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM);
   else begin
     assign PCM = '0;
-    assign DB_SCR = DebugScanIn;
+    assign DSCR = DebugScanIn;
   end
 
   // FIXME: delete once working
diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv
index 47e812e47..7e8ab9272 100644
--- a/src/lsu/lsu.sv
+++ b/src/lsu/lsu.sv
@@ -155,7 +155,7 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
   logic [P.XLEN-1:0]     WriteDataZM;
   logic                  LSULoadPageFaultM, LSUStoreAmoPageFaultM;
 
-  logic                  DB_SCR;                                 // Debug Register Scan In
+  logic                  DSCR;                                   // Debug Register Scan In
   
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Pipeline for IEUAdr E to M
@@ -163,7 +163,7 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
   /////////////////////////////////////////////////////////////////////////////////////////////
 
   if (P.DEBUG_SUPPORTED)
-    flopenrcs #(P.XLEN) AddressMReg(.clk, .reset, .clear(FlushM), .en(~StallM), .d(IEUAdrE), .q(IEUAdrM), .scan(DebugScanEn), .scanin(DebugScanIn), .scanout(DB_SCR));
+    flopenrcs #(P.XLEN) AddressMReg(.clk, .reset, .clear(FlushM), .en(~StallM), .d(IEUAdrE), .q(IEUAdrM), .scan(DebugScanEn), .scanin(DebugScanIn), .scanout(DSCR));
   else
     flopenrc #(P.XLEN) AddressMReg(.clk, .reset, .clear(FlushM), .en(~StallM), .d(IEUAdrE), .q(IEUAdrM)); 
 
@@ -433,7 +433,7 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
 
   // Capture ReadDataM
   if (P.DEBUG_SUPPORTED) begin
-    flopenrs #(P.LLEN) ReadDataMScan (.clk, .reset, .en(DebugCapture), .d(ReadDataM), .q(), .scan(DebugScanEn), .scanin(DB_SCR), .scanout(DebugScanOut));
+    flopenrs #(P.LLEN) ReadDataMScan (.clk, .reset, .en(DebugCapture), .d(ReadDataM), .q(), .scan(DebugScanEn), .scanin(DSCR), .scanout(DebugScanOut));
   end
 
   // Compute byte masks