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Updated subword misaligned.

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This commit is contained in:
Rose Thompson 2024-02-22 13:29:39 -06:00
parent 7e1ea1e6d9
commit 69d31d50e2
3 changed files with 14 additions and 6 deletions
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2
src/lsu/lsu.sv
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@ -427,7 +427,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
if(MISALIGN_SUPPORT) begin
subwordreadmisaligned #(P.LLEN) subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM,
.FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM);
subwordwritedouble #(P.LLEN) subwordwrite(.LSUFunct3M, .PAdrM(PAdrM[2:0]), .FpLoadStoreM, .BigEndianM, .AllowShiftM, .IMAFWriteDataM, .LittleEndianWriteDataM);
subwordwritemisaligned #(P.LLEN) subwordwrite(.LSUFunct3M, .PAdrM(PAdrM[2:0]), .FpLoadStoreM, .BigEndianM, .AllowShiftM, .IMAFWriteDataM, .LittleEndianWriteDataM);
end else begin
subwordread #(P.LLEN) subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM,
.FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM);

12
src/lsu/subworddreadmisaligned.sv
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@ -38,6 +38,7 @@ module subwordreadmisaligned #(parameter LLEN)
output logic [LLEN-1:0] ReadDataM
);
logic [LLEN*2-1:0] ReadDataAlignedM;
logic [7:0] ByteM;
logic [15:0] HalfwordM;
logic [31:0] WordM;
@ -64,13 +65,20 @@ module subwordreadmisaligned #(parameter LLEN)
default: LengthM = 5'd8;
endcase
logic [LLEN*2-1:0] ReadDataAlignedM;
assign ReadDataAlignedM = ReadDataWordMuxM >> (PAdrSwap[$clog2(LLEN/4)-1:0] * 8);
assign ByteM = ReadDataAlignedM[7:0];
assign HalfwordM = ReadDataAlignedM[15:0];
assign WordM = ReadDataAlignedM[31:0];
logic [LLEN-1:0] lb, lh_flh, lw_flw, ld_fld, lbu, lbu_flq, lhu, lwu;
assign lb = {{LLEN-8{ByteM[7]}}, ByteM};
assign lh_flh = {{LLEN-16{HalfwordM[15]|FpLoadStoreM}}, HalfwordM[15:0]};;
assign lw_flw = {{LLEN-32{WordM[31]|FpLoadStoreM}}, WordM[31:0]};
//assign ld_fld = {{LLEN-64{DblWordM[63]|FpLoadStoreM}}, DblWordM[63:0]};
if (LLEN == 128) begin:swrmux
logic [63:0] DblWordM;
logic [127:0] QdWordM;
@ -120,7 +128,7 @@ module subwordreadmisaligned #(parameter LLEN)
3'b001: ReadDataM = {{LLEN-16{HalfwordM[15]|FpLoadStoreM}}, HalfwordM[15:0]}; // lh/flh
3'b010: ReadDataM = {{LLEN-32{WordM[31]|FpLoadStoreM}}, WordM[31:0]}; // lw/flw
3'b011: ReadDataM = WordM[LLEN-1:0]; // fld
//3'b011: ReadDataM = WordM[LLEN-1:0]; // fld
3'b100: ReadDataM = {{LLEN-8{1'b0}}, ByteM[7:0]}; // lbu
3'b101: ReadDataM = {{LLEN-16{1'b0}}, HalfwordM[15:0]}; // lhu

6
src/lsu/subwordwritedouble.sv → src/lsu/subwordwritemisaligned.sv
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@ -1,5 +1,5 @@
///////////////////////////////////////////
// subwordwrite.sv
// subwordwritemisaligned.sv
//
// Written: David_Harris@hmc.edu
// Created: 9 January 2021
@ -28,7 +28,7 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module subwordwritedouble #(parameter LLEN) (
module subwordwritemisaligned #(parameter LLEN) (
input logic [2:0] LSUFunct3M,
input logic [2:0] PAdrM,
input logic FpLoadStoreM,
@ -38,7 +38,7 @@ module subwordwritedouble #(parameter LLEN) (
output logic [LLEN*2-1:0] LittleEndianWriteDataM
);
// *** RT: This is logic is duplicated in subwordreaddouble. Merge the two.
// *** RT: This is logic is duplicated in subwordreadmisaligned. Merge the two.
logic [4:0] PAdrSwap;
logic [4:0] BigEndianPAdr;
logic [4:0] LengthM;