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https://github.com/openhwgroup/cvw
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changed shifter source select signal name
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1506d50c63
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@ -56,6 +56,9 @@ module alu #(parameter WIDTH=32) (
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logic Rotate;
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logic Rotate;
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logic [WIDTH:0] shA; // XLEN+1 bit input source to shifter
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logic [WIDTH:0] shA; // XLEN+1 bit input source to shifter
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logic [WIDTH-1:0] rotA; // XLEN bit input source to shifter
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logic [WIDTH-1:0] rotA; // XLEN bit input source to shifter
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logic [1:0] shASelect; // select signal for shifter source generation mux
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assign shASelect = {W64,SubArith};
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if (`ZBS_SUPPORTED) begin: zbsdec
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if (`ZBS_SUPPORTED) begin: zbsdec
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@ -67,7 +70,7 @@ module alu #(parameter WIDTH=32) (
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// Sign/Zero extend mux
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// Sign/Zero extend mux
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if (WIDTH == 64) begin // rv64 must handle word s/z extensions
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if (WIDTH == 64) begin // rv64 must handle word s/z extensions
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always_comb
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always_comb
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case ({W64, SubArith})
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case (shASelect)
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2'b00: shA = {{1'b0}, A};
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2'b00: shA = {{1'b0}, A};
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2'b01: shA = {A[63], A};
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2'b01: shA = {A[63], A};
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2'b10: shA = {{33'b0}, A[31:0]};
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2'b10: shA = {{33'b0}, A[31:0]};
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@ -197,7 +197,8 @@ module controller(
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assign CSRWriteD = CSRReadD & !(CSRZeroSrcD & InstrD[13]); // Don't write if setting or clearing zeros
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assign CSRWriteD = CSRReadD & !(CSRZeroSrcD & InstrD[13]); // Don't write if setting or clearing zeros
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assign SFenceVmaD = PrivilegedD & (InstrD[31:25] == 7'b0001001);
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assign SFenceVmaD = PrivilegedD & (InstrD[31:25] == 7'b0001001);
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assign FenceD = SFenceVmaD | FenceXD; // possible sfence.vma or fence.i
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assign FenceD = SFenceVmaD | FenceXD; // possible sfence.vma or fence.i
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//NOTE: Move the B conditional logic into bctrl
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if (`ZBA_SUPPORTED) begin
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if (`ZBA_SUPPORTED) begin
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// ALU Decoding is more comprehensive when ZBA is supported. Only conflict with Funct3 is with slt instructionsb
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// ALU Decoding is more comprehensive when ZBA is supported. Only conflict with Funct3 is with slt instructionsb
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assign sltD = (Funct3D == 3'b010 & (~BSelectD[3]));
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assign sltD = (Funct3D == 3'b010 & (~BSelectD[3]));
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