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Exclude (FlushStage & SetValidWay) condition for RO caches
Spent a long time trying to find a way to see if this condition was possible, only to become relativly convinced that it isn't. Basically, since RO cache writes only happen after a long period of stall for the bus access, there's no way a flushD can be active at the same time as a RO cache write. TrapM causes a FlushD, but interrupts are gated by the "commited" logic and the exception pipeline stalls. I feel like its worth keeping the logic to be safe so I've chosen to exclude it rather than explicitely remove it.
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src/cache/cacheway.sv
vendored
9
src/cache/cacheway.sv
vendored
@ -101,14 +101,21 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
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if (!READ_ONLY_CACHE) begin
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assign SetDirtyWay = SetDirty & SelData;
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assign SelectedWriteWordEn = (SetValidWay | SetDirtyWay) & ~FlushStage;
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assign SetValidEN = SetValidWay & ~FlushStage;
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end
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else begin
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// Don't cover FlushStage assertion during SetValidWay.
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// it's not explicitely gated anywhere, but for read-only caches,
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// there's no way that a FlushD can happen during the write stage
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// of a fetch.
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// coverage off -item e 1 -fecexprrow 4
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assign SelectedWriteWordEn = SetValidWay & ~FlushStage;
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// coverage off -item e 1 -fecexprrow 4
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assign SetValidEN = SetValidWay & ~FlushStage;
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end
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// If writing the whole line set all write enables to 1, else only set the correct word.
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assign FinalByteMask = SetValidWay ? '1 : LineByteMask; // OR
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assign SetValidEN = SetValidWay & ~FlushStage;
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Tag Array
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