From 68a01cb0f87b5c175bfd2fd5af56211dfaacc2d6 Mon Sep 17 00:00:00 2001 From: Alec Vercruysse Date: Tue, 11 Apr 2023 16:59:11 -0700 Subject: [PATCH] Exclude (FlushStage & SetValidWay) condition for RO caches Spent a long time trying to find a way to see if this condition was possible, only to become relativly convinced that it isn't. Basically, since RO cache writes only happen after a long period of stall for the bus access, there's no way a flushD can be active at the same time as a RO cache write. TrapM causes a FlushD, but interrupts are gated by the "commited" logic and the exception pipeline stalls. I feel like its worth keeping the logic to be safe so I've chosen to exclude it rather than explicitely remove it. --- src/cache/cacheway.sv | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index 174b82c59..568e626e5 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -101,14 +101,21 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26, if (!READ_ONLY_CACHE) begin assign SetDirtyWay = SetDirty & SelData; assign SelectedWriteWordEn = (SetValidWay | SetDirtyWay) & ~FlushStage; + assign SetValidEN = SetValidWay & ~FlushStage; end else begin + // Don't cover FlushStage assertion during SetValidWay. + // it's not explicitely gated anywhere, but for read-only caches, + // there's no way that a FlushD can happen during the write stage + // of a fetch. + // coverage off -item e 1 -fecexprrow 4 assign SelectedWriteWordEn = SetValidWay & ~FlushStage; + // coverage off -item e 1 -fecexprrow 4 + assign SetValidEN = SetValidWay & ~FlushStage; end // If writing the whole line set all write enables to 1, else only set the correct word. assign FinalByteMask = SetValidWay ? '1 : LineByteMask; // OR - assign SetValidEN = SetValidWay & ~FlushStage; ///////////////////////////////////////////////////////////////////////////////////////////// // Tag Array