From 680a0148760db7a6c1e9c61c3ee0209bb170049e Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 2 Jan 2024 10:16:20 -0800 Subject: [PATCH] Finished LSU tlbcontrol coverage tests --- src/lsu/lsu.sv | 2 +- src/mmu/hptw.sv | 2 +- tests/coverage/tlbmisc.S | 23 +++++++++++++++++++---- 3 files changed, 21 insertions(+), 6 deletions(-) diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index 6417bc573..6a869076e 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -308,7 +308,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( if(P.ZICBOZ_SUPPORTED) begin assign BusCMOZero = CMOpM[3] & ~CacheableM; - assign CacheCMOpM = CacheableM ? CMOpM : '0; + assign CacheCMOpM = (CacheableM & ~SelHPTW) ? CMOpM : '0; assign BusAtomic = AtomicM[1] & ~CacheableM; end else begin assign BusCMOZero = '0; diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index 97e7f536e..294a6f8f4 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -262,7 +262,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( // 2. If the store would generate an exception don't store to dcache but still write the TLB. When we go back // to LEAF then the PMA/P. Wait this does not work. The PMA/P won't be looking a the address in the table, but // rather than physical address of the translated instruction/data. So we must generate the exception. - // *** DH 1/1/24 another bug: when the NAPOT bits (PTE[62:61]) are nonzero on a nonleaf PTE, the walker should make a page fault + // *** DH 1/1/24 another bug: when the NAPOT bits (PTE[62:61]) are nonzero on a nonleaf PTE, the walker should make a page fault (Issue 546) flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset | FlushW, 1'b1, NextWalkerState, IDLE, WalkerState); always_comb case (WalkerState) diff --git a/tests/coverage/tlbmisc.S b/tests/coverage/tlbmisc.S index e25615cd2..8d34c1ef1 100644 --- a/tests/coverage/tlbmisc.S +++ b/tests/coverage/tlbmisc.S @@ -59,6 +59,12 @@ main: li t0, 0x80200000 jalr ra, t0 # jump to misaligned megapage + # exercise ebufsmarb + li t0, 0x80000000 + lw t1, 0(t0) # fetch from an address to warm up tlb entries + li t0, 0x80A00000 + lw t1, 0(t0) # trigger TLB miss on a non-first entry + jal backandforth # exercise malformed PBMT pages @@ -91,6 +97,9 @@ main: li t0, 0x80803000 cbo.zero (t0) cbo.clean (t0) + li t0, 0x80804000 + cbo.zero (t0) + cbo.clean (t0) # set mstatus.MXR li a0, 3 @@ -114,6 +123,9 @@ main: li t0, 0x80803000 cbo.zero (t0) cbo.clean (t0) + li t0, 0x80804000 + cbo.zero (t0) + cbo.clean (t0) # clear mstatus.MXR li a0, 3 @@ -130,6 +142,8 @@ main: ecall j done +backandforth: + ret changetoipfhandler: li a0, 3 @@ -197,7 +211,7 @@ pagetable: .8byte 0x00000000200050C1 # for VA starting at 80400000 (bad PBMT pages) .8byte 0x4000000020004CC1 # for VA starting at 80600000 (bad entry: nonleaf PTE can't have PBMT != 0) .8byte 0x00000000200054C1 # for VA starting at 80800000 (testing rwx permissiosn with cbom/cboz) - .8byte 0x0000000020004CC1 + .8byte 0x0000000020004CC1 # for VA starting at 80A00000 (pointer to NAPOT 64 KiB pages like at 80000000) .8byte 0x0000000020004CC1 .8byte 0x0000000020004CC1 .8byte 0x0000000020004CC1 @@ -311,8 +325,9 @@ pagetable: .align 12 #80800000 .8byte 0x00000000200000CF # valid rwx for VA 80800000 - .8byte 0x00000000200000CF # valid r x for VA 80801000 - .8byte 0x00000000200000CF # valid r for VA 80802000 - .8byte 0x00000000200000CF # valid x for CA 80003000 + .8byte 0x00000000200000CB # valid r x for VA 80801000 + .8byte 0x00000000200000C3 # valid r for VA 80802000 + .8byte 0x00000000200000C5 # valid x for VA 80803000 + .8byte 0x00000000200000CD # valid wx for VA 80804000 (illegal combination, but used to test tlbcontrol)