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Dcache and LSU clean up.

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This commit is contained in:
Ross Thompson 2021-08-10 13:36:21 -05:00
parent cce0571925
commit 67c1028862
2 changed files with 6 additions and 206 deletions
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46
wally-pipelined/src/cache/dcache.sv vendored
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@ -61,7 +61,6 @@ module dcache
// from ptw // from ptw
input logic SelPTW, input logic SelPTW,
input logic WalkerPageFaultM, input logic WalkerPageFaultM,
output logic [`XLEN-1:0] LSUData,
output logic MemAfterIWalkDone, output logic MemAfterIWalkDone,
// ahb side // ahb side
output logic [`PA_BITS-1:0] AHBPAdr, // to ahb output logic [`PA_BITS-1:0] AHBPAdr, // to ahb
@ -79,7 +78,7 @@ module dcache
localparam integer BLOCKLEN = `DCACHE_BLOCKLENINBITS; localparam integer BLOCKLEN = `DCACHE_BLOCKLENINBITS;
localparam integer NUMLINES = `DCACHE_WAYSIZEINBYTES*8/BLOCKLEN; localparam integer NUMLINES = `DCACHE_WAYSIZEINBYTES*8/BLOCKLEN;
localparam integer NUMWAYS = `DCACHE_NUMWAYS; localparam integer NUMWAYS = `DCACHE_NUMWAYS;
localparam integer NUMREPL_BITS = `DCACHE_REPLBITS; localparam integer NUMREPL_BITS = `DCACHE_REPLBITS; // *** not used
localparam integer BLOCKBYTELEN = BLOCKLEN/8; localparam integer BLOCKBYTELEN = BLOCKLEN/8;
localparam integer OFFSETLEN = $clog2(BLOCKBYTELEN); localparam integer OFFSETLEN = $clog2(BLOCKBYTELEN);
@ -113,25 +112,19 @@ module dcache
logic [BLOCKLEN-1:0] FinalWriteDataWordsM; logic [BLOCKLEN-1:0] FinalWriteDataWordsM;
logic [LOGWPL-1:0] FetchCount, NextFetchCount; logic [LOGWPL-1:0] FetchCount, NextFetchCount;
logic [WORDSPERLINE-1:0] SRAMWordEnable; logic [WORDSPERLINE-1:0] SRAMWordEnable;
logic SelMemWriteDataM;
logic [2:0] Funct3W;
logic SRAMWordWriteEnableM, SRAMWordWriteEnableW; logic SRAMWordWriteEnableM;
logic SRAMBlockWriteEnableM; logic SRAMBlockWriteEnableM;
logic [NUMWAYS-1:0] SRAMBlockWayWriteEnableM; logic [NUMWAYS-1:0] SRAMBlockWayWriteEnableM;
logic SRAMWriteEnable; logic SRAMWriteEnable;
logic [NUMWAYS-1:0] SRAMWayWriteEnable; logic [NUMWAYS-1:0] SRAMWayWriteEnable;
logic SaveSRAMRead;
logic [1:0] AtomicW;
logic [NUMWAYS-1:0] VictimWay; logic [NUMWAYS-1:0] VictimWay;
logic [NUMWAYS-1:0] VictimDirtyWay; logic [NUMWAYS-1:0] VictimDirtyWay;
logic [BLOCKLEN-1:0] VictimReadDataBlockM; logic [BLOCKLEN-1:0] VictimReadDataBlockM;
logic VictimDirty; logic VictimDirty;
logic SelAMOWrite;
logic SelUncached; logic SelUncached;
logic [6:0] Funct7W;
logic [2**LOGWPL-1:0] MemPAdrDecodedW; logic [2**LOGWPL-1:0] MemPAdrDecodedW;
logic [`PA_BITS-1:0] BasePAdrM; logic [`PA_BITS-1:0] BasePAdrM;
@ -150,10 +143,6 @@ module dcache
logic LRUWriteEn; logic LRUWriteEn;
logic CaptureDataM;
logic [`XLEN-1:0] SavedReadDataM;
typedef enum {STATE_READY, typedef enum {STATE_READY,
STATE_MISS_FETCH_WDV, STATE_MISS_FETCH_WDV,
@ -213,15 +202,6 @@ module dcache
statetype CurrState, NextState; statetype CurrState, NextState;
flopenr #(7) Funct7WReg(.clk(clk),
.reset(reset),
.en(~StallWtoDCache),
.d(Funct7M),
.q(Funct7W));
// data path // data path
mux3 #(INDEXLEN) mux3 #(INDEXLEN)
@ -354,17 +334,7 @@ module dcache
subwordread subwordread(.HRDATA(ReadDataWordMuxM), subwordread subwordread(.HRDATA(ReadDataWordMuxM),
.HADDRD(MemPAdrM[2:0]), .HADDRD(MemPAdrM[2:0]),
.HSIZED({Funct3M[2], 1'b0, Funct3M[1:0]}), .HSIZED({Funct3M[2], 1'b0, Funct3M[1:0]}),
.HRDATAMasked(LSUData)); .HRDATAMasked(ReadDataM));
assign CaptureDataM = ~SelPTW & MemRWM[1];
flopen #(`XLEN)
SavedReadDataReg(.clk,
.en(CaptureDataM),
.d(LSUData),
.q(SavedReadDataM));
assign ReadDataM = LSUData;
generate generate
if (`A_SUPPORTED) begin if (`A_SUPPORTED) begin
@ -443,13 +413,6 @@ module dcache
assign SRAMWriteEnable = SRAMBlockWriteEnableM | SRAMWordWriteEnableM; assign SRAMWriteEnable = SRAMBlockWriteEnableM | SRAMWordWriteEnableM;
flopr #(1)
SRAMWritePipeReg(.clk(clk),
.reset(reset),
.d({SRAMWordWriteEnableM}),
.q({SRAMWordWriteEnableW}));
always_ff @(posedge clk, posedge reset) always_ff @(posedge clk, posedge reset)
if (reset) CurrState <= #1 STATE_READY; if (reset) CurrState <= #1 STATE_READY;
else CurrState <= #1 NextState; else CurrState <= #1 NextState;
@ -464,14 +427,11 @@ module dcache
ClearValidM = 1'b0; ClearValidM = 1'b0;
SetDirtyM = 1'b0; SetDirtyM = 1'b0;
ClearDirtyM = 1'b0; ClearDirtyM = 1'b0;
SelMemWriteDataM = 1'b0;
SRAMWordWriteEnableM = 1'b0; SRAMWordWriteEnableM = 1'b0;
SRAMBlockWriteEnableM = 1'b0; SRAMBlockWriteEnableM = 1'b0;
SaveSRAMRead = 1'b1;
CntReset = 1'b0; CntReset = 1'b0;
AHBRead = 1'b0; AHBRead = 1'b0;
AHBWrite = 1'b0; AHBWrite = 1'b0;
SelAMOWrite = 1'b0;
CommittedM = 1'b0; CommittedM = 1'b0;
SelUncached = 1'b0; SelUncached = 1'b0;
SelEvict = 1'b0; SelEvict = 1'b0;

162
wally-pipelined/src/lsu/lsu.sv
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@ -93,37 +93,17 @@ module lsu
input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // *** this one especially has a large note attached to it in pmpchecker. input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // *** this one especially has a large note attached to it in pmpchecker.
// output logic [5:0] DHSELRegionsM
); );
logic SquashSCM; logic SquashSCM;
logic DTLBPageFaultM; logic DTLBPageFaultM;
logic MemAccessM;
/* -----\/----- EXCLUDED -----\/-----
logic preCommittedM;
-----/\----- EXCLUDED -----/\----- */
typedef enum {STATE_READY,
STATE_FETCH,
STATE_FETCH_AMO_1,
STATE_FETCH_AMO_2,
STATE_STALLED,
STATE_PTW_READY,
STATE_PTW_FETCH,
STATE_PTW_DONE} statetype;
statetype CurrState, NextState;
logic [`PA_BITS-1:0] MemPAdrM; // from mmu to dcache logic [`PA_BITS-1:0] MemPAdrM; // from mmu to dcache
logic DTLBMissM; logic DTLBMissM;
// logic [`XLEN-1:0] PTE;
logic DTLBWriteM; logic DTLBWriteM;
logic HPTWStall; logic HPTWStall;
logic [`XLEN-1:0] HPTWPAdrE;
// logic [`XLEN-1:0] HPTWPAdrM;
logic [`PA_BITS-1:0] TranslationPAdr; logic [`PA_BITS-1:0] TranslationPAdr;
logic HPTWRead; logic HPTWRead;
logic [1:0] MemRWMtoDCache; logic [1:0] MemRWMtoDCache;
@ -132,11 +112,9 @@ module lsu
logic [1:0] AtomicMtoDCache; logic [1:0] AtomicMtoDCache;
logic [`PA_BITS-1:0] MemPAdrMtoDCache; logic [`PA_BITS-1:0] MemPAdrMtoDCache;
logic [11:0] MemAdrEtoDCache; logic [11:0] MemAdrEtoDCache;
logic [`XLEN-1:0] ReadDataWfromDCache;
logic StallWtoDCache; logic StallWtoDCache;
logic MemReadM; logic MemReadM;
logic DataMisalignedMfromDCache; logic DataMisalignedMfromDCache;
logic HPTWReady;
logic DisableTranslation; // used to stop intermediate PTE physical addresses being saved to TLB. logic DisableTranslation; // used to stop intermediate PTE physical addresses being saved to TLB.
logic DCacheStall; logic DCacheStall;
@ -149,7 +127,6 @@ module lsu
logic FlushWtoDCache; logic FlushWtoDCache;
logic WalkerPageFaultM; logic WalkerPageFaultM;
logic [`XLEN-1:0] LSUData;
logic AnyCPUReqM; logic AnyCPUReqM;
logic MemAfterIWalkDone; logic MemAfterIWalkDone;
@ -167,7 +144,7 @@ module lsu
.PageType, .PageType,
.ITLBWriteF(ITLBWriteF), .ITLBWriteF(ITLBWriteF),
.DTLBWriteM(DTLBWriteM), .DTLBWriteM(DTLBWriteM),
.HPTWReadPTE(LSUData), .HPTWReadPTE(ReadDataM),
.HPTWStall(HPTWStall), .HPTWStall(HPTWStall),
.TranslationPAdr, .TranslationPAdr,
.HPTWRead(HPTWRead), .HPTWRead(HPTWRead),
@ -213,9 +190,6 @@ module lsu
.PendingInterruptMtoDCache(PendingInterruptMtoDCache), .PendingInterruptMtoDCache(PendingInterruptMtoDCache),
.DCacheStall(DCacheStall)); .DCacheStall(DCacheStall));
mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0)) mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0))
dmmu(.PAdr(MemPAdrMtoDCache), dmmu(.PAdr(MemPAdrMtoDCache),
.VAdr(MemAdrM), .VAdr(MemAdrM),
@ -268,28 +242,6 @@ module lsu
2'b11: DataMisalignedMfromDCache = |MemPAdrMtoDCache[2:0]; // ld, sd, fld, fsd 2'b11: DataMisalignedMfromDCache = |MemPAdrMtoDCache[2:0]; // ld, sd, fld, fsd
endcase endcase
// Squash unaligned data accesses and failed store conditionals
// *** this is also the place to squash if the cache is hit
// Changed DataMisalignedMfromDCache to a larger combination of trap sources
// NonBusTrapM is anything that the bus doesn't contribute to producing
// By contrast, using TrapM results in circular logic errors
/* -----\/----- EXCLUDED -----\/-----
// *** BUG for now leave this out. come back later after the d cache is working. July 09, 2021
assign MemReadM = MemRWMtoLRSC[1] & ~NonBusTrapM & ~DTLBMissM & CurrState != STATE_STALLED;
assign MemWriteM = MemRWMtoLRSC[0] & ~NonBusTrapM & ~DTLBMissM & ~SquashSCM & CurrState != STATE_STALLED;
assign AtomicMaskedM = CurrState != STATE_STALLED ? AtomicMtoDCache : 2'b00 ;
assign MemAccessM = MemReadM | MemWriteM;
// Determine if M stage committed
// Reset whenever unstalled. Set when access successfully occurs
flopr #(1) committedMreg(clk,reset,(CommittedMfromDCache | CommitM) & StallM,preCommittedM);
assign CommittedMfromDCache = preCommittedM | CommitM;
-----/\----- EXCLUDED -----/\----- */
// Determine if address is valid // Determine if address is valid
assign LoadMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoLRSC[1]; assign LoadMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoLRSC[1];
assign StoreMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoLRSC[0]; assign StoreMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoLRSC[0];
@ -309,7 +261,6 @@ module lsu
.VAdr(MemAdrM[11:0]), .VAdr(MemAdrM[11:0]),
.WriteDataM(WriteDataM), .WriteDataM(WriteDataM),
.ReadDataM(ReadDataM), .ReadDataM(ReadDataM),
.LSUData(LSUData),
.DCacheStall(DCacheStall), .DCacheStall(DCacheStall),
.CommittedM(CommittedMfromDCache), .CommittedM(CommittedMfromDCache),
.DCacheMiss, .DCacheMiss,
@ -335,116 +286,5 @@ module lsu
.HRDATA(DCfromAHBReadData) .HRDATA(DCfromAHBReadData)
); );
// assign AtomicMaskedM = 2'b00; // *** Remove from AHB
// Data stall
//assign LSUStall = (NextState == STATE_FETCH) || (NextState == STATE_FETCH_AMO_1) || (NextState == STATE_FETCH_AMO_2);
// BUG *** July 09, 2021
//assign HPTWReady = (CurrState == STATE_READY);
// Ross Thompson April 22, 2021
// for now we need to handle the issue where the data memory interface repeately
// requests data from memory rather than issuing a single request.
/* -----\/----- EXCLUDED -----\/-----
// *** BUG will need to modify this so we can handle the ptw. July 09, 2021
flopenl #(.TYPE(statetype)) stateReg(.clk(clk),
.load(reset),
.en(1'b1),
.d(NextState),
.val(STATE_READY),
.q(CurrState));
always_comb begin
case (CurrState)
STATE_READY:
if (DTLBMissM) begin
NextState = STATE_PTW_READY;
LSUStall = 1'b1;
end else if (AtomicMaskedM[1]) begin
NextState = STATE_FETCH_AMO_1; // *** should be some misalign check
LSUStall = 1'b1;
end else if((MemReadM & AtomicMtoDCache[0]) | (MemWriteM & AtomicMtoDCache[0])) begin
NextState = STATE_FETCH_AMO_2;
LSUStall = 1'b1;
end else if (MemAccessM & ~DataMisalignedMfromDCache) begin
NextState = STATE_FETCH;
LSUStall = 1'b1;
end else begin
NextState = STATE_READY;
LSUStall = 1'b0;
end
STATE_FETCH_AMO_1: begin
LSUStall = 1'b1;
if (DCfromAHBAck) begin
NextState = STATE_FETCH_AMO_2;
end else begin
NextState = STATE_FETCH_AMO_1;
end
end
STATE_FETCH_AMO_2: begin
LSUStall = 1'b1;
if (DCfromAHBAck & ~StallWtoDCache) begin
NextState = STATE_FETCH_AMO_2;
end else if (DCfromAHBAck & StallWtoDCache) begin
NextState = STATE_STALLED;
end else begin
NextState = STATE_FETCH_AMO_2;
end
end
STATE_FETCH: begin
LSUStall = 1'b1;
if (DCfromAHBAck & ~StallWtoDCache) begin
NextState = STATE_READY;
end else if (DCfromAHBAck & StallWtoDCache) begin
NextState = STATE_STALLED;
end else begin
NextState = STATE_FETCH;
end
end
STATE_STALLED: begin
LSUStall = 1'b0;
if (~StallWtoDCache) begin
NextState = STATE_READY;
end else begin
NextState = STATE_STALLED;
end
end
STATE_PTW_READY: begin
LSUStall = 1'b0;
if (DTLBWriteM) begin
NextState = STATE_READY;
LSUStall = 1'b1;
end else if (MemReadM & ~DataMisalignedMfromDCache) begin
NextState = STATE_PTW_FETCH;
end else begin
NextState = STATE_PTW_READY;
end
end
STATE_PTW_FETCH : begin
LSUStall = 1'b1;
if (DCfromAHBAck & ~DTLBWriteM) begin
NextState = STATE_PTW_READY;
end else if (DCfromAHBAck & DTLBWriteM) begin
NextState = STATE_READY;
end else begin
NextState = STATE_PTW_FETCH;
end
end
STATE_PTW_DONE: begin
NextState = STATE_READY;
end
default: begin
LSUStall = 1'b0;
NextState = STATE_READY;
end
endcase
end // always_comb
-----/\----- EXCLUDED -----/\----- */
endmodule endmodule