diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 3965ba5b9..9b66e879e 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -61,7 +61,6 @@ module dcache // from ptw input logic SelPTW, input logic WalkerPageFaultM, - output logic [`XLEN-1:0] LSUData, output logic MemAfterIWalkDone, // ahb side output logic [`PA_BITS-1:0] AHBPAdr, // to ahb @@ -79,7 +78,7 @@ module dcache localparam integer BLOCKLEN = `DCACHE_BLOCKLENINBITS; localparam integer NUMLINES = `DCACHE_WAYSIZEINBYTES*8/BLOCKLEN; localparam integer NUMWAYS = `DCACHE_NUMWAYS; - localparam integer NUMREPL_BITS = `DCACHE_REPLBITS; + localparam integer NUMREPL_BITS = `DCACHE_REPLBITS; // *** not used localparam integer BLOCKBYTELEN = BLOCKLEN/8; localparam integer OFFSETLEN = $clog2(BLOCKBYTELEN); @@ -113,25 +112,19 @@ module dcache logic [BLOCKLEN-1:0] FinalWriteDataWordsM; logic [LOGWPL-1:0] FetchCount, NextFetchCount; logic [WORDSPERLINE-1:0] SRAMWordEnable; - logic SelMemWriteDataM; - logic [2:0] Funct3W; - logic SRAMWordWriteEnableM, SRAMWordWriteEnableW; + logic SRAMWordWriteEnableM; logic SRAMBlockWriteEnableM; logic [NUMWAYS-1:0] SRAMBlockWayWriteEnableM; logic SRAMWriteEnable; logic [NUMWAYS-1:0] SRAMWayWriteEnable; - logic SaveSRAMRead; - logic [1:0] AtomicW; logic [NUMWAYS-1:0] VictimWay; logic [NUMWAYS-1:0] VictimDirtyWay; logic [BLOCKLEN-1:0] VictimReadDataBlockM; logic VictimDirty; - logic SelAMOWrite; logic SelUncached; - logic [6:0] Funct7W; logic [2**LOGWPL-1:0] MemPAdrDecodedW; logic [`PA_BITS-1:0] BasePAdrM; @@ -149,10 +142,6 @@ module dcache logic SelEvict; logic LRUWriteEn; - - logic CaptureDataM; - logic [`XLEN-1:0] SavedReadDataM; - typedef enum {STATE_READY, @@ -212,15 +201,6 @@ module dcache STATE_CPU_BUSY_FINISH_AMO} statetype; statetype CurrState, NextState; - - - flopenr #(7) Funct7WReg(.clk(clk), - .reset(reset), - .en(~StallWtoDCache), - .d(Funct7M), - .q(Funct7W)); - - // data path @@ -354,18 +334,8 @@ module dcache subwordread subwordread(.HRDATA(ReadDataWordMuxM), .HADDRD(MemPAdrM[2:0]), .HSIZED({Funct3M[2], 1'b0, Funct3M[1:0]}), - .HRDATAMasked(LSUData)); + .HRDATAMasked(ReadDataM)); - assign CaptureDataM = ~SelPTW & MemRWM[1]; - - flopen #(`XLEN) - SavedReadDataReg(.clk, - .en(CaptureDataM), - .d(LSUData), - .q(SavedReadDataM)); - - assign ReadDataM = LSUData; - generate if (`A_SUPPORTED) begin logic [`XLEN-1:0] AMOResult; @@ -443,13 +413,6 @@ module dcache assign SRAMWriteEnable = SRAMBlockWriteEnableM | SRAMWordWriteEnableM; - flopr #(1) - SRAMWritePipeReg(.clk(clk), - .reset(reset), - .d({SRAMWordWriteEnableM}), - .q({SRAMWordWriteEnableW})); - - always_ff @(posedge clk, posedge reset) if (reset) CurrState <= #1 STATE_READY; else CurrState <= #1 NextState; @@ -464,14 +427,11 @@ module dcache ClearValidM = 1'b0; SetDirtyM = 1'b0; ClearDirtyM = 1'b0; - SelMemWriteDataM = 1'b0; SRAMWordWriteEnableM = 1'b0; SRAMBlockWriteEnableM = 1'b0; - SaveSRAMRead = 1'b1; CntReset = 1'b0; AHBRead = 1'b0; AHBWrite = 1'b0; - SelAMOWrite = 1'b0; CommittedM = 1'b0; SelUncached = 1'b0; SelEvict = 1'b0; diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 040af6f58..3c17e9f95 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -93,38 +93,18 @@ module lsu input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // *** this one especially has a large note attached to it in pmpchecker. - - // output logic [5:0] DHSELRegionsM - ); logic SquashSCM; logic DTLBPageFaultM; - logic MemAccessM; -/* -----\/----- EXCLUDED -----\/----- - logic preCommittedM; - -----/\----- EXCLUDED -----/\----- */ - - typedef enum {STATE_READY, - STATE_FETCH, - STATE_FETCH_AMO_1, - STATE_FETCH_AMO_2, - STATE_STALLED, - STATE_PTW_READY, - STATE_PTW_FETCH, - STATE_PTW_DONE} statetype; - statetype CurrState, NextState; logic [`PA_BITS-1:0] MemPAdrM; // from mmu to dcache logic DTLBMissM; -// logic [`XLEN-1:0] PTE; logic DTLBWriteM; logic HPTWStall; - logic [`XLEN-1:0] HPTWPAdrE; -// logic [`XLEN-1:0] HPTWPAdrM; - logic [`PA_BITS-1:0] TranslationPAdr; + logic [`PA_BITS-1:0] TranslationPAdr; logic HPTWRead; logic [1:0] MemRWMtoDCache; logic [1:0] MemRWMtoLRSC; @@ -132,11 +112,9 @@ module lsu logic [1:0] AtomicMtoDCache; logic [`PA_BITS-1:0] MemPAdrMtoDCache; logic [11:0] MemAdrEtoDCache; - logic [`XLEN-1:0] ReadDataWfromDCache; logic StallWtoDCache; - logic MemReadM; + logic MemReadM; logic DataMisalignedMfromDCache; - logic HPTWReady; logic DisableTranslation; // used to stop intermediate PTE physical addresses being saved to TLB. logic DCacheStall; @@ -149,7 +127,6 @@ module lsu logic FlushWtoDCache; logic WalkerPageFaultM; - logic [`XLEN-1:0] LSUData; logic AnyCPUReqM; logic MemAfterIWalkDone; @@ -167,7 +144,7 @@ module lsu .PageType, .ITLBWriteF(ITLBWriteF), .DTLBWriteM(DTLBWriteM), - .HPTWReadPTE(LSUData), + .HPTWReadPTE(ReadDataM), .HPTWStall(HPTWStall), .TranslationPAdr, .HPTWRead(HPTWRead), @@ -213,9 +190,6 @@ module lsu .PendingInterruptMtoDCache(PendingInterruptMtoDCache), .DCacheStall(DCacheStall)); - - - mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0)) dmmu(.PAdr(MemPAdrMtoDCache), .VAdr(MemAdrM), @@ -268,28 +242,6 @@ module lsu 2'b11: DataMisalignedMfromDCache = |MemPAdrMtoDCache[2:0]; // ld, sd, fld, fsd endcase - // Squash unaligned data accesses and failed store conditionals - // *** this is also the place to squash if the cache is hit - // Changed DataMisalignedMfromDCache to a larger combination of trap sources - // NonBusTrapM is anything that the bus doesn't contribute to producing - // By contrast, using TrapM results in circular logic errors -/* -----\/----- EXCLUDED -----\/----- - - // *** BUG for now leave this out. come back later after the d cache is working. July 09, 2021 - - assign MemReadM = MemRWMtoLRSC[1] & ~NonBusTrapM & ~DTLBMissM & CurrState != STATE_STALLED; - assign MemWriteM = MemRWMtoLRSC[0] & ~NonBusTrapM & ~DTLBMissM & ~SquashSCM & CurrState != STATE_STALLED; - assign AtomicMaskedM = CurrState != STATE_STALLED ? AtomicMtoDCache : 2'b00 ; - assign MemAccessM = MemReadM | MemWriteM; - - // Determine if M stage committed - // Reset whenever unstalled. Set when access successfully occurs - flopr #(1) committedMreg(clk,reset,(CommittedMfromDCache | CommitM) & StallM,preCommittedM); - assign CommittedMfromDCache = preCommittedM | CommitM; - - - -----/\----- EXCLUDED -----/\----- */ - // Determine if address is valid assign LoadMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoLRSC[1]; assign StoreMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoLRSC[0]; @@ -309,7 +261,6 @@ module lsu .VAdr(MemAdrM[11:0]), .WriteDataM(WriteDataM), .ReadDataM(ReadDataM), - .LSUData(LSUData), .DCacheStall(DCacheStall), .CommittedM(CommittedMfromDCache), .DCacheMiss, @@ -334,117 +285,6 @@ module lsu .HWDATA(DCtoAHBWriteData), .HRDATA(DCfromAHBReadData) ); - -// assign AtomicMaskedM = 2'b00; // *** Remove from AHB - - - // Data stall - //assign LSUStall = (NextState == STATE_FETCH) || (NextState == STATE_FETCH_AMO_1) || (NextState == STATE_FETCH_AMO_2); - // BUG *** July 09, 2021 - //assign HPTWReady = (CurrState == STATE_READY); - - - // Ross Thompson April 22, 2021 - // for now we need to handle the issue where the data memory interface repeately - // requests data from memory rather than issuing a single request. - -/* -----\/----- EXCLUDED -----\/----- - // *** BUG will need to modify this so we can handle the ptw. July 09, 2021 - - flopenl #(.TYPE(statetype)) stateReg(.clk(clk), - .load(reset), - .en(1'b1), - .d(NextState), - .val(STATE_READY), - .q(CurrState)); - - always_comb begin - case (CurrState) - STATE_READY: - if (DTLBMissM) begin - NextState = STATE_PTW_READY; - LSUStall = 1'b1; - end else if (AtomicMaskedM[1]) begin - NextState = STATE_FETCH_AMO_1; // *** should be some misalign check - LSUStall = 1'b1; - end else if((MemReadM & AtomicMtoDCache[0]) | (MemWriteM & AtomicMtoDCache[0])) begin - NextState = STATE_FETCH_AMO_2; - LSUStall = 1'b1; - end else if (MemAccessM & ~DataMisalignedMfromDCache) begin - NextState = STATE_FETCH; - LSUStall = 1'b1; - end else begin - NextState = STATE_READY; - LSUStall = 1'b0; - end - STATE_FETCH_AMO_1: begin - LSUStall = 1'b1; - if (DCfromAHBAck) begin - NextState = STATE_FETCH_AMO_2; - end else begin - NextState = STATE_FETCH_AMO_1; - end - end - STATE_FETCH_AMO_2: begin - LSUStall = 1'b1; - if (DCfromAHBAck & ~StallWtoDCache) begin - NextState = STATE_FETCH_AMO_2; - end else if (DCfromAHBAck & StallWtoDCache) begin - NextState = STATE_STALLED; - end else begin - NextState = STATE_FETCH_AMO_2; - end - end - STATE_FETCH: begin - LSUStall = 1'b1; - if (DCfromAHBAck & ~StallWtoDCache) begin - NextState = STATE_READY; - end else if (DCfromAHBAck & StallWtoDCache) begin - NextState = STATE_STALLED; - end else begin - NextState = STATE_FETCH; - end - end - STATE_STALLED: begin - LSUStall = 1'b0; - if (~StallWtoDCache) begin - NextState = STATE_READY; - end else begin - NextState = STATE_STALLED; - end - end - STATE_PTW_READY: begin - LSUStall = 1'b0; - if (DTLBWriteM) begin - NextState = STATE_READY; - LSUStall = 1'b1; - end else if (MemReadM & ~DataMisalignedMfromDCache) begin - NextState = STATE_PTW_FETCH; - end else begin - NextState = STATE_PTW_READY; - end - end - STATE_PTW_FETCH : begin - LSUStall = 1'b1; - if (DCfromAHBAck & ~DTLBWriteM) begin - NextState = STATE_PTW_READY; - end else if (DCfromAHBAck & DTLBWriteM) begin - NextState = STATE_READY; - end else begin - NextState = STATE_PTW_FETCH; - end - end - STATE_PTW_DONE: begin - NextState = STATE_READY; - end - default: begin - LSUStall = 1'b0; - NextState = STATE_READY; - end - endcase - end // always_comb - -----/\----- EXCLUDED -----/\----- */ - endmodule