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Mostly enable riscv-arch-test zcf and zcd tests

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Some tests disabled pending riscv-arch-test issue 590
This commit is contained in:
Jordan Carlin 2024-12-31 02:17:49 -08:00
parent 89a3e3baa5
commit 67843e647a
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2 changed files with 34 additions and 2 deletions
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10
testbench/testbench.sv
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@ -145,7 +145,9 @@ module testbench;
"arch64i": tests = arch64i;
"arch64priv": tests = arch64priv;
"arch64c": if (P.ZCA_SUPPORTED)
if (P.ZICSR_SUPPORTED) tests = {arch64c, arch64cpriv};
if (P.ZICSR_SUPPORTED)
if (P.ZCD_SUPPORTED) tests = {arch64c, arch64cpriv, arch64zcd};
else tests = {arch64c, arch64cpriv};
else tests = {arch64c};
"arch64m": if (P.M_SUPPORTED) tests = arch64m;
"arch64a_amo": if (P.ZAAMO_SUPPORTED) tests = arch64a_amo;
@ -192,7 +194,11 @@ module testbench;
"arch32i": tests = arch32i;
"arch32priv": tests = arch32priv;
"arch32c": if (P.C_SUPPORTED)
if (P.ZICSR_SUPPORTED) tests = {arch32c, arch32cpriv};
if (P.ZICSR_SUPPORTED)
if (P.ZCF_SUPPORTED)
if (P.ZCD_SUPPORTED) tests = {arch32c, arch32cpriv, arch32zcf, arch32zcd};
else tests = {arch32c, arch32cpriv, arch32zcf};
else tests = {arch32c, arch32cpriv};
else tests = {arch32c};
"arch32m": if (P.M_SUPPORTED) tests = arch32m;
"arch32a_amo": if (P.ZAAMO_SUPPORTED) tests = arch32a_amo;

26
testbench/tests.vh
View File

@ -536,6 +536,15 @@ string arch64cpriv[] = '{
"rv64i_m/C/src/cebreak-01.S"
};
// Tests commented out pending riscv-arch-test issue #590
string arch64zcd[] = '{
// `RISCVARCHTEST,
"rv64i_m/D_Zcd/src/c.fld-01.S",
"rv64i_m/D_Zcd/src/c.fldsp-01.S",
"rv64i_m/D_Zcd/src/c.fsd-01.S",
"rv64i_m/D_Zcd/src/c.fsdsp-01.S"
};
string arch64i[] = '{
`RISCVARCHTEST,
"rv64i_m/I/src/add-01.S",
@ -3361,6 +3370,23 @@ string arch32cpriv[] = '{
"rv32i_m/C/src/cebreak-01.S"
};
// Tests commented out pending riscv-arch-test issue #590
string arch32zcf[] = '{
// `RISCVARCHTEST,
// "rv32i_m/F_Zcf/src/c.flw-01.S",
// "rv32i_m/F_Zcf/src/c.flwsp-01.S",
// "rv32i_m/F_Zcf/src/c.fsw-01.S",
"rv32i_m/F_Zcf/src/c.fswsp-01.S"
};
// Tests commented out pending riscv-arch-test issue #590
string arch32zcd[] = '{
// `RISCVARCHTEST,
"rv32i_m/D_Zcd/src/c.fld-01.S",
// "rv32i_m/D_Zcd/src/c.fldsp-01.S",
"rv32i_m/D_Zcd/src/c.fsd-01.S",
"rv32i_m/D_Zcd/src/c.fsdsp-01.S"
};
string arch32i[] = '{
`RISCVARCHTEST,