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Removed unused inputs to hptw.

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This commit is contained in:
Ross Thompson 2022-01-13 11:04:48 -06:00
parent a23e6efd5c
commit 66f3259984
2 changed files with 2 additions and 5 deletions
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4
pipelined/src/lsu/lsu.sv
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@ -142,9 +142,9 @@ module lsu
hptw hptw(.clk, .reset, .SATP_REGW, .PCF, .IEUAdrM, hptw hptw(.clk, .reset, .SATP_REGW, .PCF, .IEUAdrM,
.ITLBMissF(ITLBMissF & ~TrapM), .ITLBMissF(ITLBMissF & ~TrapM),
.DTLBMissM(DTLBMissM & ~TrapM), .DTLBMissM(DTLBMissM & ~TrapM),
.MemRWM, .PTE, .PageType, .ITLBWriteF, .DTLBWriteM, .PTE, .PageType, .ITLBWriteF, .DTLBWriteM,
.HPTWReadPTE(ReadDataM), .HPTWReadPTE(ReadDataM),
.DCacheStall, .HPTWAdr, .HPTWRead, .HPTWSize, .AnyCPUReqM); .DCacheStall, .HPTWAdr, .HPTWRead, .HPTWSize);
// arbiter between IEU and hptw // arbiter between IEU and hptw

3
pipelined/src/mmu/hptw.sv
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@ -36,10 +36,8 @@ module hptw
input logic [`XLEN-1:0] SATP_REGW, // includes SATP.MODE to determine number of levels in page table input logic [`XLEN-1:0] SATP_REGW, // includes SATP.MODE to determine number of levels in page table
input logic [`XLEN-1:0] PCF, IEUAdrM, // addresses to translate input logic [`XLEN-1:0] PCF, IEUAdrM, // addresses to translate
(* mark_debug = "true" *) input logic ITLBMissF, DTLBMissM, // TLB Miss (* mark_debug = "true" *) input logic ITLBMissF, DTLBMissM, // TLB Miss
input logic [1:0] MemRWM, // 10 = read, 01 = write
input logic [`XLEN-1:0] HPTWReadPTE, // page table entry from LSU input logic [`XLEN-1:0] HPTWReadPTE, // page table entry from LSU
input logic DCacheStall, // stall from LSU input logic DCacheStall, // stall from LSU
input logic AnyCPUReqM,
output logic [`XLEN-1:0] PTE, // page table entry to TLBs output logic [`XLEN-1:0] PTE, // page table entry to TLBs
output logic [1:0] PageType, // page type to TLBs output logic [1:0] PageType, // page type to TLBs
(* mark_debug = "true" *) output logic ITLBWriteF, DTLBWriteM, // write TLB with new entry (* mark_debug = "true" *) output logic ITLBWriteF, DTLBWriteM, // write TLB with new entry
@ -73,7 +71,6 @@ module hptw
// Extract bits from CSRs and inputs // Extract bits from CSRs and inputs
assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS]; assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS];
assign BasePageTablePPN = SATP_REGW[`PPN_BITS-1:0]; assign BasePageTablePPN = SATP_REGW[`PPN_BITS-1:0];
assign MemWrite = MemRWM[0];
assign TLBMiss = (DTLBMissM | ITLBMissF); assign TLBMiss = (DTLBMissM | ITLBMissF);
// Determine which address to translate // Determine which address to translate