diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index 9ac887fe7..321af023c 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -142,9 +142,9 @@ module lsu
     hptw hptw(.clk, .reset, .SATP_REGW, .PCF, .IEUAdrM,
         .ITLBMissF(ITLBMissF & ~TrapM),
         .DTLBMissM(DTLBMissM & ~TrapM),
-        .MemRWM, .PTE, .PageType, .ITLBWriteF, .DTLBWriteM,
+        .PTE, .PageType, .ITLBWriteF, .DTLBWriteM,
         .HPTWReadPTE(ReadDataM),
-        .DCacheStall, .HPTWAdr, .HPTWRead, .HPTWSize, .AnyCPUReqM);
+        .DCacheStall, .HPTWAdr, .HPTWRead, .HPTWSize);
 
     // arbiter between IEU and hptw
     
diff --git a/pipelined/src/mmu/hptw.sv b/pipelined/src/mmu/hptw.sv
index 157a80bcb..5c3724808 100644
--- a/pipelined/src/mmu/hptw.sv
+++ b/pipelined/src/mmu/hptw.sv
@@ -36,10 +36,8 @@ module hptw
    input logic [`XLEN-1:0] 	   SATP_REGW, // includes SATP.MODE to determine number of levels in page table
    input logic [`XLEN-1:0] 	   PCF, IEUAdrM, // addresses to translate
    (* mark_debug = "true" *) input logic 				   ITLBMissF, DTLBMissM, // TLB Miss
-   input logic [1:0] 		   MemRWM, // 10 = read, 01 = write
    input logic [`XLEN-1:0] 	   HPTWReadPTE, // page table entry from LSU
    input logic 				   DCacheStall, // stall from LSU
-   input logic 				   AnyCPUReqM,
    output logic [`XLEN-1:0]    PTE, // page table entry to TLBs
    output logic [1:0] 		   PageType, // page type to TLBs
    (* mark_debug = "true" *) output logic 			   ITLBWriteF, DTLBWriteM, // write TLB with new entry
@@ -73,7 +71,6 @@ module hptw
 	// Extract bits from CSRs and inputs
 	assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS];
 	assign BasePageTablePPN = SATP_REGW[`PPN_BITS-1:0];
-	assign MemWrite = MemRWM[0];
 	assign TLBMiss = (DTLBMissM | ITLBMissF);
 
 	// Determine which address to translate