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Merge pull request #1093 from AnonymousVikram/fflag_fix

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Fflag Fix
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David Harris 2024-11-14 04:33:58 -08:00 committed by GitHub
commit 669855ad25
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2 changed files with 4 additions and 2 deletions
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1
src/fpu/fcmp.sv
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@ -75,6 +75,7 @@ module fcmp import cvw::*; #(parameter cvw_t P) (
3'b0?1: if (P.ZFA_SUPPORTED)
CmpNV = Zfa ? EitherSNaN : EitherNaN; // fltq,fleq / flt,fle perform CompareQuietLess / CompareSignalingLess differing on when to set invalid
else CmpNV = EitherNaN; // flt, fle
3'b100: CmpNV = 1'b0;
default: CmpNV = 1'bx;
endcase
end

5
src/fpu/fround.sv
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@ -146,7 +146,8 @@ module fround import cvw::*; #(parameter cvw_t P) (
packoutput #(P) packoutput(W, Fmt, FRound); // pack and NaN-box based on selected format.
// Flags
assign FRoundNV = XSNaN; // invalid if input is signaling NaN
assign FRoundNX = ZfaFRoundNX & ~EgeNf & (Rp | Tp); // Inexact if Round or Sticky bit set for FRoundNX instruction
assign FRoundNV = XSNaN; // invalid if input is signaling NaN
assign FRoundNX = ZfaFRoundNX & ~EgeNf & (Rp | Tp) & ~XNaN; // Inexact if Round or Sticky bit set for FRoundNX instruction
// Note: NX must not be raised if input is invalid
endmodule