From 654c4d1148c4356bb9a4e00bac367261676e8916 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 10 Mar 2022 18:17:44 -0600 Subject: [PATCH] simplified uncore's name for HWDATA. --- pipelined/src/uncore/uncore.sv | 7 +------ pipelined/src/wally/wallypipelinedsoc.sv | 2 +- 2 files changed, 2 insertions(+), 7 deletions(-) diff --git a/pipelined/src/uncore/uncore.sv b/pipelined/src/uncore/uncore.sv index 16fa38df6..d90a30d7c 100644 --- a/pipelined/src/uncore/uncore.sv +++ b/pipelined/src/uncore/uncore.sv @@ -38,7 +38,7 @@ module uncore ( input logic HCLK, HRESETn, input logic TIMECLK, input logic [31:0] HADDR, - input logic [`AHBW-1:0] HWDATAIN, + input logic [`AHBW-1:0] HWDATA, input logic HWRITE, input logic [2:0] HSIZE, input logic [2:0] HBURST, @@ -68,7 +68,6 @@ module uncore ( output logic [63:0] MTIME_CLINT ); - logic [`XLEN-1:0] HWDATA; logic [`XLEN-1:0] HREADRam, HREADCLINT, HREADPLIC, HREADGPIO, HREADUART, HREADSDC; logic [8:0] HSELRegions; @@ -90,10 +89,6 @@ module uncore ( // unswizzle HSEL signals assign {HSELEXT, HSELBootRom, HSELRam, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC, HSELSDC} = HSELRegions[7:0]; - // subword accesses: converts HWDATAIN to HWDATA only if no dtim or cache. - assign HWDATA = HWDATAIN; - - // generate // on-chip RAM if (`RAM_SUPPORTED) begin : ram diff --git a/pipelined/src/wally/wallypipelinedsoc.sv b/pipelined/src/wally/wallypipelinedsoc.sv index a311d6c64..1b7f38311 100644 --- a/pipelined/src/wally/wallypipelinedsoc.sv +++ b/pipelined/src/wally/wallypipelinedsoc.sv @@ -92,7 +92,7 @@ module wallypipelinedsoc ( ); uncore uncore(.HCLK, .HRESETn, .TIMECLK, - .HADDR, .HWDATAIN(HWDATA), .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, + .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HADDRD, .HSIZED, .HWRITED, .TimerIntM, .SwIntM, .ExtIntM, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, .UARTSout, .MTIME_CLINT, .HSELEXT,