mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
This commit is contained in:
Skylar Litz
commit
64a537c59b
32
.gitignore
vendored
32
.gitignore
vendored
@ -71,3 +71,35 @@ synthDC/runs/
|
||||
synthDC/hdl
|
||||
/pipelined/regression/power.saif
|
||||
tests/fp/vectors/*.tv
|
||||
# Temporary configs produced for synthesis
|
||||
pipelined/config/rv32e_FPUoff
|
||||
pipelined/config/rv32e_PMP0
|
||||
pipelined/config/rv32e_PMP16
|
||||
pipelined/config/rv32e_noMulDiv
|
||||
pipelined/config/rv32e_noPriv
|
||||
pipelined/config/rv32e_orig
|
||||
pipelined/config/rv32gc_FPUoff
|
||||
pipelined/config/rv32gc_PMP0
|
||||
pipelined/config/rv32gc_PMP16
|
||||
pipelined/config/rv32gc_noMulDiv
|
||||
pipelined/config/rv32gc_noPriv
|
||||
pipelined/config/rv32gc_orig
|
||||
pipelined/config/rv32ic_FPUoff
|
||||
pipelined/config/rv32ic_PMP0
|
||||
pipelined/config/rv32ic_PMP16
|
||||
pipelined/config/rv32ic_noMulDiv
|
||||
pipelined/config/rv32ic_noPriv
|
||||
pipelined/config/rv32ic_orig
|
||||
pipelined/config/rv64gc_FPUoff
|
||||
pipelined/config/rv64gc_PMP0
|
||||
pipelined/config/rv64gc_PMP16
|
||||
pipelined/config/rv64gc_noMulDiv
|
||||
pipelined/config/rv64gc_noPriv
|
||||
pipelined/config/rv64gc_orig
|
||||
pipelined/config/rv64ic_FPUoff
|
||||
pipelined/config/rv64ic_PMP0
|
||||
pipelined/config/rv64ic_PMP16
|
||||
pipelined/config/rv64ic_noMulDiv
|
||||
pipelined/config/rv64ic_noPriv
|
||||
pipelined/config/rv64ic_orig
|
||||
synthDC/Summary.csv
|
||||
|
||||
@ -1 +1 @@
|
||||
Subproject commit be67c99bd461742aa1c100bcc0732657faae2230
|
||||
Subproject commit effd553a6a91ed9b0ba251796a8a44505a45174f
|
||||
File diff suppressed because one or more lines are too long
@ -10,14 +10,14 @@
|
||||
</db_ref_list>
|
||||
<zoom_setting>
|
||||
<ZoomStartTime time="0fs"></ZoomStartTime>
|
||||
<ZoomEndTime time="16385fs"></ZoomEndTime>
|
||||
<Cursor1Time time="6fs"></Cursor1Time>
|
||||
<ZoomEndTime time="168fs"></ZoomEndTime>
|
||||
<Cursor1Time time="0fs"></Cursor1Time>
|
||||
</zoom_setting>
|
||||
<column_width_setting>
|
||||
<NameColumnWidth column_width="452"></NameColumnWidth>
|
||||
<ValueColumnWidth column_width="145"></ValueColumnWidth>
|
||||
<ValueColumnWidth column_width="141"></ValueColumnWidth>
|
||||
</column_width_setting>
|
||||
<WVObjectSize size="29" />
|
||||
<WVObjectSize size="11" />
|
||||
<wave_markers>
|
||||
</wave_markers>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/core/PCM">
|
||||
@ -53,7 +53,6 @@
|
||||
<wvobject type="group" fp_name="group468">
|
||||
<obj_property name="label">CPU to LSU</obj_property>
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
<obj_property name="isExpanded"></obj_property>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/core/IEUAdrM">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/IEUAdrM[63:0]</obj_property>
|
||||
@ -111,7 +110,6 @@
|
||||
<wvobject type="group" fp_name="group470">
|
||||
<obj_property name="label">PLIC</obj_property>
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
<obj_property name="isExpanded"></obj_property>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/requests">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/requests[12:1]</obj_property>
|
||||
@ -140,7 +138,6 @@
|
||||
<wvobject type="group" fp_name="group471">
|
||||
<obj_property name="label">interrupts</obj_property>
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
<obj_property name="isExpanded"></obj_property>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW">
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[63:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">MEDELEG_REGW[63:0]</obj_property>
|
||||
@ -178,7 +175,6 @@
|
||||
<wvobject type="group" fp_name="group463">
|
||||
<obj_property name="label">LSU to Bus</obj_property>
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
<obj_property name="isExpanded"></obj_property>
|
||||
<wvobject type="logic" fp_name="wallypipelinedsoc/core/lsu/LSUBusRead">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUBusRead</obj_property>
|
||||
@ -312,7 +308,6 @@
|
||||
<wvobject type="group" fp_name="group487">
|
||||
<obj_property name="label">sdc</obj_property>
|
||||
<obj_property name="DisplayName">label</obj_property>
|
||||
<obj_property name="isExpanded"></obj_property>
|
||||
<wvobject type="logic" fp_name="wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_ERROR_Q">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_ERROR_Q</obj_property>
|
||||
@ -352,144 +347,4 @@
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[11:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">IP_REGW_writeable[11:0]</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/csr/csri/MExtIntM">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csri/MExtIntM</obj_property>
|
||||
<obj_property name="ObjectShortName">MExtIntM</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/csr/csri/SExtIntM">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csri/SExtIntM</obj_property>
|
||||
<obj_property name="ObjectShortName">SExtIntM</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/csr/csri/SwIntM">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csri/SwIntM</obj_property>
|
||||
<obj_property name="ObjectShortName">SwIntM</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/csr/csri/TimerIntM">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csri/TimerIntM</obj_property>
|
||||
<obj_property name="ObjectShortName">TimerIntM</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[63:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">MEDELEG_REGW[63:0]</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">MIDELEG_REGW[11:0]</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/uncore/clint.clint/MTIMECMP">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/uncore/clint.clint/MTIMECMP[63:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">MTIMECMP[63:0]</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/uncore/clint.clint/MTIME">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/uncore/clint.clint/MTIME[63:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">MTIME[63:0]</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/intEn[1]__0">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[10:1]</obj_property>
|
||||
<obj_property name="ObjectShortName">intEn[1]__0[10:1]</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/intPriority[10]">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/intPriority[10][2:0]</obj_property>
|
||||
<obj_property name="ObjectShortName">intPriority[10][2:0]</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1]">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][10:1]</obj_property>
|
||||
<obj_property name="ObjectShortName">irqMatrix[1][1][10:1]</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2]">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][10:1]</obj_property>
|
||||
<obj_property name="ObjectShortName">irqMatrix[1][2][10:1]</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3]">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][10:1]</obj_property>
|
||||
<obj_property name="ObjectShortName">irqMatrix[1][3][10:1]</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4]">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][10:1]</obj_property>
|
||||
<obj_property name="ObjectShortName">irqMatrix[1][4][10:1]</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5]">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][10:1]</obj_property>
|
||||
<obj_property name="ObjectShortName">irqMatrix[1][5][10:1]</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6]">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][10:1]</obj_property>
|
||||
<obj_property name="ObjectShortName">irqMatrix[1][6][10:1]</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
<wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7]">
|
||||
<obj_property name="DisplayName">FullPathName</obj_property>
|
||||
<obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][10:1]</obj_property>
|
||||
<obj_property name="ObjectShortName">irqMatrix[1][7][10:1]</obj_property>
|
||||
<obj_property name="Radix">HEXRADIX</obj_property>
|
||||
<obj_property name="LABELRADIX">true</obj_property>
|
||||
<obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
|
||||
</wvobject>
|
||||
</wave_config>
|
||||
|
||||
@ -2,8 +2,8 @@ echo "Hello this ~/.profile is meant to demonstrate running some basic commands
|
||||
echo "I am $(whoami)"
|
||||
echo "And I am on $(hostname)"
|
||||
touch myFile.txt
|
||||
echo "This is a line of text." > myFile.txt
|
||||
echo "A second line of text." >> myFile.txt
|
||||
echo "Hello World!" > myFile.txt
|
||||
echo "And farewell!" >> myFile.txt
|
||||
mkdir myDir
|
||||
mv myFile.txt myDir
|
||||
echo "Created myFile.txt and moved it to myDir. It contains:"
|
||||
@ -17,10 +17,7 @@ cd myDir
|
||||
ln -s ../myScript.sh symLinkToMyScript.sh
|
||||
echo "Created symLinkToMyScript.sh. Running it yields:"
|
||||
./symLinkToMyScript.sh
|
||||
ln ../myScript.sh hardLinkToMyScript.sh
|
||||
echo "Created hardLinkToMyScript.sh. Running it yields:"
|
||||
./hardLinkToMyScript.sh
|
||||
echo "Now let\'s remove all these example files and scripts"
|
||||
echo "Now let's remove all these example files and scripts"
|
||||
cd /
|
||||
rm -r myDir
|
||||
rm myScript.sh
|
||||
@ -28,10 +25,5 @@ echo "Here is disk usage:"
|
||||
df -h
|
||||
echo "And here are the current processes:"
|
||||
ps
|
||||
echo "We can create a user."
|
||||
cd /
|
||||
mkdir home
|
||||
echo "password\npassword\n" | adduser myUser
|
||||
su -c "cd ~; echo \"I am $(whoami) (a new user) and my home directory is $(pwd)\""
|
||||
echo "And finally a login prompt."
|
||||
login
|
||||
|
||||
@ -1,4 +1,5 @@
|
||||
IMAGES := ${RISCV}/buildroot/output/images
|
||||
BUILDROOT := ${RISCV}/buildroot
|
||||
IMAGES := ${BUILDROOT}/output/images
|
||||
DIS := ${IMAGES}/disassembly
|
||||
|
||||
all:
|
||||
@ -7,7 +8,7 @@ all:
|
||||
|
||||
generate:
|
||||
# generating device tree binary
|
||||
dtc -I dts -O dtb ../devicetree/wally-virt.dts > ${RISCV}/buildroot/output/images/wally-virt.dtb
|
||||
dtc -I dts -O dtb ../devicetree/wally-virt.dts > ${IMAGES}/wally-virt.dtb
|
||||
|
||||
disassemble:
|
||||
mkdir -p ${DIS}
|
||||
@ -21,6 +22,9 @@ disassemble:
|
||||
${DIS}/fw_jump.objdump: ${IMAGES}/fw_jump.elf
|
||||
riscv64-unknown-elf-objdump -S ${IMAGES}/fw_jump.elf >> ${DIS}/fw_jump.objdump
|
||||
|
||||
${IMAGES}/vmlinux: ${BUILDROOT}/output/build/linux-5.10.7/vmlinux
|
||||
cp ${BUILDROOT}/output/build/linux-5.10.7/vmlinux ${IMAGES}/vmlinux
|
||||
|
||||
${DIS}/vmlinux.objdump: ${IMAGES}/vmlinux
|
||||
riscv64-unknown-elf-objdump -S ${IMAGES}/vmlinux >> ${DIS}/vmlinux.objdump
|
||||
|
||||
|
||||
@ -29,7 +29,6 @@
|
||||
|
||||
`define FPGA 1
|
||||
`define QEMU 1
|
||||
`define LINUX_FIX_READ {'h10000005}
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
`define XLEN 64
|
||||
|
||||
@ -78,6 +77,9 @@
|
||||
// Address space
|
||||
`define RESET_VECTOR 64'h0000000000001000
|
||||
|
||||
// WFI Timeout Wait
|
||||
`define WFI_TIMEOUT_BIT 20
|
||||
|
||||
// Peripheral Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
@ -126,6 +128,8 @@
|
||||
`define BPRED_ENABLED 1
|
||||
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||
`define TESTSBP 0
|
||||
`define BPRED_SIZE 10
|
||||
|
||||
|
||||
`define REPLAY 0
|
||||
`define HPTW_WRITES_SUPPORTED 1
|
||||
|
||||
@ -79,6 +79,9 @@
|
||||
// Address space
|
||||
`define RESET_VECTOR 64'h0000000000001000
|
||||
|
||||
// WFI Timeout Wait
|
||||
`define WFI_TIMEOUT_BIT 20
|
||||
|
||||
// Peripheral Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
@ -134,6 +137,8 @@
|
||||
`define BPRED_ENABLED 1
|
||||
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||
`define TESTSBP 1
|
||||
`define BPRED_SIZE 10
|
||||
|
||||
|
||||
`define REPLAY 0
|
||||
`define HPTW_WRITES_SUPPORTED 1
|
||||
|
||||
@ -80,6 +80,9 @@
|
||||
// Address space
|
||||
`define RESET_VECTOR 32'h80000000
|
||||
|
||||
// WFI Timeout Wait
|
||||
`define WFI_TIMEOUT_BIT 20
|
||||
|
||||
// Peripheral Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
@ -131,6 +134,7 @@
|
||||
`define BPRED_ENABLED 0
|
||||
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||
`define TESTSBP 0
|
||||
`define BPRED_SIZE 10
|
||||
|
||||
`define REPLAY 0
|
||||
`define HPTW_WRITES_SUPPORTED 0
|
||||
|
||||
@ -78,6 +78,9 @@
|
||||
// Address space
|
||||
`define RESET_VECTOR 32'h80000000
|
||||
|
||||
// WFI Timeout Wait
|
||||
`define WFI_TIMEOUT_BIT 20
|
||||
|
||||
// Peripheral Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
@ -129,6 +132,7 @@
|
||||
`define BPRED_ENABLED 1
|
||||
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||
`define TESTSBP 0
|
||||
`define BPRED_SIZE 10
|
||||
|
||||
`define REPLAY 0
|
||||
`define HPTW_WRITES_SUPPORTED 0
|
||||
|
||||
@ -37,8 +37,8 @@
|
||||
// IEEE 754 compliance
|
||||
`define IEEE754 0
|
||||
|
||||
// IA
|
||||
`define MISA (32'h00000100 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 << 3 | 1 << 5)
|
||||
// I
|
||||
`define MISA (32'h00000100 | 1 << 20 | 1 << 18 )
|
||||
`define ZICSR_SUPPORTED 1
|
||||
`define ZIFENCEI_SUPPORTED 1
|
||||
`define COUNTERS 32
|
||||
@ -80,6 +80,9 @@
|
||||
// Address space
|
||||
`define RESET_VECTOR 32'h80000000
|
||||
|
||||
// WFI Timeout Wait
|
||||
`define WFI_TIMEOUT_BIT 5
|
||||
|
||||
// Peripheral Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
@ -92,10 +95,10 @@
|
||||
`define EXT_MEM_SUPPORTED 1'b0
|
||||
`define EXT_MEM_BASE 34'h80000000
|
||||
`define EXT_MEM_RANGE 34'h07FFFFFF
|
||||
`define CLINT_SUPPORTED 1'b0
|
||||
`define CLINT_SUPPORTED 1'b1
|
||||
`define CLINT_BASE 34'h02000000
|
||||
`define CLINT_RANGE 34'h0000FFFF
|
||||
`define GPIO_SUPPORTED 1'b0
|
||||
`define GPIO_SUPPORTED 1'b1
|
||||
`define GPIO_BASE 34'h10060000
|
||||
`define GPIO_RANGE 34'h000000FF
|
||||
`define UART_SUPPORTED 1'b1
|
||||
@ -126,11 +129,13 @@
|
||||
`define PLIC_GPIO_ID 3
|
||||
`define PLIC_UART_ID 10
|
||||
|
||||
`define TWO_BIT_PRELOAD "../config/rv32ia/twoBitPredictor.txt"
|
||||
`define BTB_PRELOAD "../config/rv32ia/BTBPredictor.txt"
|
||||
`define TWO_BIT_PRELOAD "../config/rv32i/twoBitPredictor.txt"
|
||||
`define BTB_PRELOAD "../config/rv32i/BTBPredictor.txt"
|
||||
`define BPRED_ENABLED 1
|
||||
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||
`define TESTSBP 0
|
||||
`define BPRED_SIZE 10
|
||||
|
||||
|
||||
`define REPLAY 0
|
||||
`define HPTW_WRITES_SUPPORTED 0
|
||||
@ -78,6 +78,9 @@
|
||||
// Address space
|
||||
`define RESET_VECTOR 32'h80000000
|
||||
|
||||
// WFI Timeout Wait
|
||||
`define WFI_TIMEOUT_BIT 20
|
||||
|
||||
// Peripheral Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
@ -129,6 +132,8 @@
|
||||
`define BPRED_ENABLED 1
|
||||
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||
`define TESTSBP 0
|
||||
`define BPRED_SIZE 10
|
||||
|
||||
|
||||
`define REPLAY 0
|
||||
`define HPTW_WRITES_SUPPORTED 0
|
||||
|
||||
@ -59,7 +59,7 @@
|
||||
|
||||
// TLB configuration. Entries should be a power of 2
|
||||
`define ITLB_ENTRIES 32
|
||||
`define DTLB_ENTRIES 32
|
||||
`define DTLB_ENTRIES 32
|
||||
|
||||
// Cache configuration. Sizes should be a power of two
|
||||
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
|
||||
@ -82,6 +82,9 @@
|
||||
// Bus Interface width
|
||||
`define AHBW 64
|
||||
|
||||
// WFI Timeout Wait
|
||||
`define WFI_TIMEOUT_BIT 20
|
||||
|
||||
// Peripheral Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
@ -132,6 +135,8 @@
|
||||
//`define BPTYPE "BPGSHARE" // BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||
`define BPTYPE "BPGSHARE" // BPTWOBIT or "BPGLOBAL" or BPLOCALPAg or BPGSHARE
|
||||
`define TESTSBP 1
|
||||
`define BPRED_SIZE 10
|
||||
|
||||
|
||||
`define REPLAY 0
|
||||
`define HPTW_WRITES_SUPPORTED 0
|
||||
|
||||
@ -84,6 +84,9 @@
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
|
||||
// WFI Timeout Wait
|
||||
`define WFI_TIMEOUT_BIT 20
|
||||
|
||||
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
|
||||
`define BOOTROM_SUPPORTED 1'b1
|
||||
`define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
|
||||
@ -130,6 +133,8 @@
|
||||
`define BPRED_ENABLED 1
|
||||
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||
`define TESTSBP 0
|
||||
`define BPRED_SIZE 10
|
||||
|
||||
|
||||
`define REPLAY 0
|
||||
`define HPTW_WRITES_SUPPORTED 0
|
||||
|
||||
@ -82,6 +82,9 @@
|
||||
// Bus Interface width
|
||||
`define AHBW 64
|
||||
|
||||
// WFI Timeout Wait
|
||||
`define WFI_TIMEOUT_BIT 20
|
||||
|
||||
// Peripheral Physiccal Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
@ -132,6 +135,7 @@
|
||||
`define BPRED_ENABLED 1
|
||||
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||
`define TESTSBP 0
|
||||
`define BPRED_SIZE 10
|
||||
|
||||
`define REPLAY 0
|
||||
`define HPTW_WRITES_SUPPORTED 0
|
||||
|
||||
@ -37,8 +37,8 @@
|
||||
// IEEE 754 compliance
|
||||
`define IEEE754 0
|
||||
|
||||
// MISA RISC-V configuration per specification IA
|
||||
`define MISA (32'h00000100 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 << 3 | 1 << 5)
|
||||
// MISA RISC-V configuration per specification I
|
||||
`define MISA (32'h00000100 | 1 << 20 | 1 << 18 )
|
||||
`define ZICSR_SUPPORTED 1
|
||||
`define ZIFENCEI_SUPPORTED 1
|
||||
`define COUNTERS 32
|
||||
@ -82,6 +82,9 @@
|
||||
// Bus Interface width
|
||||
`define AHBW 64
|
||||
|
||||
// WFI Timeout Wait
|
||||
`define WFI_TIMEOUT_BIT 5
|
||||
|
||||
// Peripheral Physiccal Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
@ -127,11 +130,12 @@
|
||||
`define PLIC_GPIO_ID 3
|
||||
`define PLIC_UART_ID 10
|
||||
|
||||
`define TWO_BIT_PRELOAD "../config/rv64ia/twoBitPredictor.txt"
|
||||
`define BTB_PRELOAD "../config/rv64ia/BTBPredictor.txt"
|
||||
`define TWO_BIT_PRELOAD "../config/rv64i/twoBitPredictor.txt"
|
||||
`define BTB_PRELOAD "../config/rv64i/BTBPredictor.txt"
|
||||
`define BPRED_ENABLED 1
|
||||
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||
`define TESTSBP 0
|
||||
`define BPRED_SIZE 10
|
||||
|
||||
`define REPLAY 0
|
||||
`define HPTW_WRITES_SUPPORTED 0
|
||||
@ -82,6 +82,9 @@
|
||||
// Bus Interface width
|
||||
`define AHBW 64
|
||||
|
||||
// WFI Timeout Wait
|
||||
`define WFI_TIMEOUT_BIT 20
|
||||
|
||||
// Peripheral Physiccal Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
@ -132,6 +135,7 @@
|
||||
`define BPRED_ENABLED 1
|
||||
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||
`define TESTSBP 0
|
||||
`define BPRED_SIZE 10
|
||||
|
||||
`define REPLAY 0
|
||||
`define HPTW_WRITES_SUPPORTED 0
|
||||
|
||||
@ -45,7 +45,7 @@ configs = [
|
||||
)
|
||||
]
|
||||
def getBuildrootTC(short):
|
||||
INSTR_LIMIT = 100000 # multiple of 100000
|
||||
INSTR_LIMIT = 4000000 # multiple of 100000; 4M is interesting because it gets into the kernel and enabling VM
|
||||
MAX_EXPECTED = 246000000
|
||||
if short:
|
||||
BRcmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do buildroot buildroot $RISCV "+str(INSTR_LIMIT)+" 1 0\n!"
|
||||
@ -80,21 +80,21 @@ for test in tests32gc:
|
||||
configs.append(tc)
|
||||
|
||||
|
||||
tests64ia = ["wally64priv"]
|
||||
for test in tests64ia:
|
||||
tests64i = ["wally64priv"]
|
||||
for test in tests64i:
|
||||
tc = TestCase(
|
||||
name=test,
|
||||
variant="rv64ia",
|
||||
cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv64ia "+test+"\n!",
|
||||
variant="rv64i",
|
||||
cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv64i "+test+"\n!",
|
||||
grepstr="All tests ran without failures")
|
||||
configs.append(tc)
|
||||
|
||||
tests32ia = ["wally32priv"]
|
||||
for test in tests32ia:
|
||||
tests32i = ["wally32priv"]
|
||||
for test in tests32i:
|
||||
tc = TestCase(
|
||||
name=test,
|
||||
variant="rv32ia",
|
||||
cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv32ia "+test+"\n!",
|
||||
variant="rv32i",
|
||||
cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv32i "+test+"\n!",
|
||||
grepstr="All tests ran without failures")
|
||||
configs.append(tc)
|
||||
|
||||
|
||||
@ -52,14 +52,14 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
|
||||
#vsim -coverage -lib work_$2 workopt_$2
|
||||
|
||||
# power add generates the logging necessary for saif generation.
|
||||
power add -r /dut/core/*
|
||||
# power add -r /dut/core/*
|
||||
run -all
|
||||
power off -r /dut/core/*
|
||||
# power off -r /dut/core/*
|
||||
}
|
||||
|
||||
#coverage report -file wally-pipelined-coverage.txt
|
||||
# These aren't doing anything helpful
|
||||
#coverage report -memory
|
||||
#profile report -calltree -file wally-pipelined-calltree.rpt -cutoff 2
|
||||
power report -all -bsaif power.saif
|
||||
#power report -all -bsaif power.saif
|
||||
quit
|
||||
|
||||
@ -48,17 +48,17 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
|
||||
} elseif {$2 eq "buildroot-no-trace"} {
|
||||
vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
|
||||
# start and run simulation
|
||||
vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=470350800 -G INSTR_WAVEON=470350800 -G CHECKPOINT=470350800 -G NO_IE_MTIME_CHECKPOINT=1 -o testbenchopt
|
||||
vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=0 -G INSTR_WAVEON=0 -G CHECKPOINT=0 -G NO_IE_MTIME_CHECKPOINT=1 -o testbenchopt
|
||||
vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829
|
||||
|
||||
#-- Run the Simulation
|
||||
echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"
|
||||
echo "Don't forget to change DEBUG_LEVEL = 0."
|
||||
echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"
|
||||
run 100 ns
|
||||
force -deposit testbench/dut/core/priv/priv/csr/csri/IE_REGW 16'h2aa
|
||||
force -deposit testbench/dut/uncore/clint/clint/MTIMECMP 64'h1000
|
||||
run 1200 ms
|
||||
echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"
|
||||
#run 100 ns
|
||||
#force -deposit testbench/dut/core/priv/priv/csr/csri/IE_REGW 16'h2aa
|
||||
#force -deposit testbench/dut/uncore/clint/clint/MTIMECMP 64'h1000
|
||||
run 14000 ms
|
||||
#add log -recursive /*
|
||||
#do linux-wave.do
|
||||
#run -all
|
||||
|
||||
4225
pipelined/src/fma/baby_torture.tv
Normal file
4225
pipelined/src/fma/baby_torture.tv
Normal file
File diff suppressed because it is too large
Load Diff
1057
pipelined/src/fma/baby_torture_rz.tv
Normal file
1057
pipelined/src/fma/baby_torture_rz.tv
Normal file
File diff suppressed because it is too large
Load Diff
86257
pipelined/src/fma/torture.tv
Normal file
86257
pipelined/src/fma/torture.tv
Normal file
File diff suppressed because it is too large
Load Diff
130
pipelined/src/fma/torturegen.pl
Executable file
130
pipelined/src/fma/torturegen.pl
Executable file
@ -0,0 +1,130 @@
|
||||
#!/usr/bin/perl -w
|
||||
# torturegen.pl
|
||||
# David_Harris@hmc.edu 19 April 2022
|
||||
# Convert TestFloat cases into format for fma16 project torture test
|
||||
# Strip out cases involving denorms
|
||||
|
||||
use strict;
|
||||
|
||||
my @basenames = ("add", "mul", "mulAdd");
|
||||
my @roundingmodes = ("rz", "rd", "ru", "rne");
|
||||
my @names = ();
|
||||
foreach my $name (@basenames) {
|
||||
foreach my $mode (@roundingmodes) {
|
||||
push(@names, "f16_${name}_$mode.tv");
|
||||
}
|
||||
}
|
||||
|
||||
open(TORTURE, ">work/torture.tv") || die("Can't write torture.tv");
|
||||
my $datestring = localtime();
|
||||
print(TORTURE "// Torture tests generated $datestring by $0\n");
|
||||
foreach my $tv (@names) {
|
||||
open(TV, "work/$tv") || die("Can't read $tv");
|
||||
my $type = &getType($tv); # is it mul, add, mulAdd
|
||||
my $rm = &getRm($tv); # rounding mode
|
||||
# if ($rm != 0) { next; } # only do rz
|
||||
print (TORTURE "\n////////// Testcases from $tv of type $type rounding mode $rm\n");
|
||||
print ("\n////////// Testcases from $tv of type $type rounding mode $rm\n");
|
||||
my $linecount = 0;
|
||||
my $babyTorture = 0;
|
||||
while (<TV>) {
|
||||
my $line = $_;
|
||||
$linecount++;
|
||||
my $density = 10;
|
||||
if ($type eq "mulAdd") {$density = 500;}
|
||||
if ($babyTorture) {
|
||||
$density = 100;
|
||||
if ($type eq "mulAdd") {$density = 50000;}
|
||||
}
|
||||
if ((($linecount + $rm) % $density) != 0) { next }; # too many tests to use
|
||||
chomp($line); # strip off newline
|
||||
my @parts = split(/_/, $line);
|
||||
my ($x, $y, $z, $op, $w, $flags);
|
||||
$x = $parts[0];
|
||||
if ($type eq "add") { $y = "0000"; } else {$y = $parts[1]};
|
||||
if ($type eq "mul") { $z = "3CFF"; } elsif ($type eq "add") {$z = $parts[1]} else { $z = $parts[2]};
|
||||
$op = $rm << 4;
|
||||
if ($type eq "mul" || $type eq "mulAdd") { $op = $op + 8; }
|
||||
if ($type eq "add" || $type eq "mulAdd") { $op = $op + 4; }
|
||||
my $opname = sprintf("%02x", $op);
|
||||
if ($type eq "mulAdd") {$w = $parts[3];} else {$w = $parts[2]};
|
||||
if ($type eq "mulAdd") {$flags = $parts[4];} else {$flags = $parts[3]};
|
||||
$flags = substr($flags, -1); # take last character
|
||||
if (&fpval($w) eq "NaN") { $w = "7e00"; }
|
||||
my $vec = "${x}_${y}_${z}_${opname}_${w}_${flags}";
|
||||
my $skip = "";
|
||||
if (&isdenorm($x) || &isdenorm($y) || &isdenorm($z) || &isdenorm($w)) {
|
||||
$skip = "Skipped denorm";
|
||||
}
|
||||
my $summary = &summary($x, $y, $z, $w, $type);
|
||||
if ($skip ne "") {
|
||||
print TORTURE "// $skip $tv line $linecount $line $summary\n"
|
||||
}
|
||||
else { print TORTURE "$vec // $tv line $linecount $line $summary\n";}
|
||||
}
|
||||
close(TV);
|
||||
}
|
||||
close(TORTURE);
|
||||
|
||||
sub fpval {
|
||||
my $val = shift;
|
||||
$val = hex($val); # convert hex string to number
|
||||
my $frac = $val & 0x3FF;
|
||||
my $exp = ($val >> 10) & 0x1F;
|
||||
my $sign = $val >> 15;
|
||||
|
||||
my $res;
|
||||
if ($exp == 31 && $frac != 0) { return "NaN"; }
|
||||
elsif ($exp == 31) { $res = "INF"; }
|
||||
elsif ($val == 0) { $res = 0; }
|
||||
elsif ($exp == 0) { $res = "Denorm"; }
|
||||
else { $res = sprintf("1.%011b x 2^%d", $frac, $exp-15); }
|
||||
|
||||
if ($sign == 1) { $res = "-$res"; }
|
||||
return $res;
|
||||
}
|
||||
|
||||
sub summary {
|
||||
my $x = shift; my $y = shift; my $z = shift; my $w = shift; my $type = shift;
|
||||
|
||||
my $xv = &fpval($x);
|
||||
my $yv = &fpval($y);
|
||||
my $zv = &fpval($z);
|
||||
my $wv = &fpval($w);
|
||||
|
||||
if ($type eq "add") { return "$xv + $zv = $wv"; }
|
||||
elsif ($type eq "mul") { return "$xv * $yv = $wv"; }
|
||||
else {return "$xv * $yv + $zv = $wv"; }
|
||||
}
|
||||
|
||||
sub getType {
|
||||
my $tv = shift;
|
||||
|
||||
if ($tv =~ /mulAdd/) { return("mulAdd"); }
|
||||
elsif ($tv =~ /mul/) { return "mul"; }
|
||||
else { return "add"; }
|
||||
}
|
||||
|
||||
sub getRm {
|
||||
my $tv = shift;
|
||||
|
||||
if ($tv =~ /rz/) { return 0; }
|
||||
elsif ($tv =~ /rne/) { return 1; }
|
||||
elsif ($tv =~ /rd/) {return 2; }
|
||||
elsif ($tv =~ /ru/) { return 3; }
|
||||
else { return "bad"; }
|
||||
}
|
||||
|
||||
sub isdenorm {
|
||||
my $fp = shift;
|
||||
my $val = hex($fp);
|
||||
my $expv = $val >> 10;
|
||||
$expv = $expv & 0x1F;
|
||||
my $denorm = 0;
|
||||
if ($expv == 0 && $val != 0) { $denorm = 1;}
|
||||
# my $e0 = ($expv == 0);
|
||||
# my $vn0 = ($val != 0);
|
||||
# my $denorm = 0; #($exp == 0 && $val != 0); # denorm exponent but not all zero
|
||||
# print("Num $fp Exp $expv Denorm $denorm Done\n");
|
||||
return $denorm;
|
||||
}
|
||||
@ -30,11 +30,17 @@ module cvtfp (
|
||||
logic [31:0] DSRes; // double to single precision result
|
||||
|
||||
|
||||
// add support for all formats
|
||||
// consider reordering code blocks so upconverting is in one region of the file
|
||||
// and downconverting is in the other region.
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// LZC
|
||||
// LZC: Leading Zero Counter
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// *** consider sharing this with fcvtint
|
||||
// *** emphasize parallel structure between the two
|
||||
// *** add a priorityencoder module to generic (similar to priorityonehot) and use it
|
||||
|
||||
// LZC - find the first 1 in the input's mantissa
|
||||
logic [8:0] i,NormCnt;
|
||||
|
||||
@ -61,6 +61,10 @@ module fcvt (
|
||||
// fcvt.d.l = 100
|
||||
// fcvt.d.lu = 110
|
||||
// {long, unsigned, to int}
|
||||
|
||||
// *** revisit this module, explain in more depth
|
||||
// should the int to fp and fp to int paths be separated?
|
||||
// add support for all formats
|
||||
|
||||
// calculate signals based off the input and output's size
|
||||
assign Res64 = (FOpCtrlE[0]&FOpCtrlE[2]) | (FmtE&~FOpCtrlE[0]);
|
||||
|
||||
@ -79,8 +79,8 @@ module hazard(
|
||||
|
||||
// Each stage flushes if the previous stage is the last one stalled (for cause) or the system has reason to flush
|
||||
assign FlushF = BPPredWrongE | InvalidateICacheM;
|
||||
assign FlushD = FirstUnstalledD | TrapM | RetM | BPPredWrongE | InvalidateICacheM;
|
||||
assign FlushE = FirstUnstalledE | TrapM | RetM | BPPredWrongE | InvalidateICacheM;
|
||||
assign FlushD = FirstUnstalledD | TrapM | RetM | BPPredWrongE | InvalidateICacheM; // *** does RetM only need to flush if the privilege changes?
|
||||
assign FlushE = FirstUnstalledE | TrapM | RetM | BPPredWrongE | InvalidateICacheM; // *** why is BPPredWrongE here, but not needed in simple processor
|
||||
assign FlushM = FirstUnstalledM | TrapM | RetM | InvalidateICacheM;
|
||||
// on Trap the memory stage should be flushed going into the W stage,
|
||||
// except if the instruction causing the Trap is an ecall or ebreak.
|
||||
|
||||
@ -40,9 +40,9 @@ module alu #(parameter WIDTH=32) (
|
||||
logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult;
|
||||
logic Carry, Neg;
|
||||
logic LT, LTU;
|
||||
logic Overflow;
|
||||
logic W64, SubArith, ALUOp;
|
||||
logic [2:0] ALUFunct;
|
||||
logic Asign, Bsign;
|
||||
|
||||
// Extract control signals
|
||||
// W64 indicates RV64 W-suffix instructions acting on lower 32-bit word
|
||||
@ -57,12 +57,13 @@ module alu #(parameter WIDTH=32) (
|
||||
// Shifts
|
||||
shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift));
|
||||
|
||||
// condition code flags based on subtract output
|
||||
// condition code flags based on subtract output Sum = A-B
|
||||
// Overflow occurs when the numbers being subtracted have the opposite sign
|
||||
// and the result has the opposite sign of A
|
||||
assign Overflow = (A[WIDTH-1] ^ B[WIDTH-1]) & (A[WIDTH-1] ^ Sum[WIDTH-1]);
|
||||
assign Neg = Sum[WIDTH-1];
|
||||
assign LT = Neg ^ Overflow;
|
||||
assign Asign = A[WIDTH-1];
|
||||
assign Bsign = B[WIDTH-1];
|
||||
assign LT = Asign & ~Bsign | Asign & Neg | ~Bsign & Neg; // simplified from Overflow = Asign & Bsign & Asign & Neg; LT = Neg ^ Overflow
|
||||
assign LTU = ~Carry;
|
||||
|
||||
// SLT
|
||||
|
||||
@ -36,9 +36,8 @@ module comparator #(parameter WIDTH=32) (
|
||||
|
||||
logic [WIDTH-1:0] bbar, diff;
|
||||
logic carry, eq, neg, overflow, lt, ltu;
|
||||
|
||||
// NOTE: This can be replaced by some faster logic optimized
|
||||
// to just compute flags and not the difference.
|
||||
/*
|
||||
// Subtractor implementation
|
||||
|
||||
// subtraction
|
||||
assign bbar = ~b;
|
||||
@ -53,5 +52,35 @@ module comparator #(parameter WIDTH=32) (
|
||||
assign lt = neg ^ overflow;
|
||||
assign ltu = ~carry;
|
||||
assign flags = {eq, lt, ltu};
|
||||
*/
|
||||
|
||||
/* verilator lint_off UNOPTFLAT */
|
||||
// prefix implementation
|
||||
localparam levels=$clog2(WIDTH);
|
||||
genvar i;
|
||||
genvar level;
|
||||
logic [WIDTH-1:0] e[levels:0];
|
||||
logic [WIDTH-1:0] l[levels:0];
|
||||
logic eq2, lt2, ltu2;
|
||||
|
||||
// Bitwise logic
|
||||
assign e[0] = a ~^ b; // bitwise equality
|
||||
assign l[0] = ~a & b; // bitwise less than unsigned: A=0 and B=1
|
||||
|
||||
// Recursion
|
||||
for (level = 1; level<=levels; level++) begin
|
||||
for (i=0; i<WIDTH/(2**level); i++) begin
|
||||
assign e[level][i] = e[level-1][i*2+1] & e[level-1][i*2]; // group equal if both parts equal
|
||||
assign l[level][i] = l[level-1][i*2+1] | e[level-1][i*2+1] & l[level-1][i*2]; // group less if upper is les or upper equal and lower less
|
||||
end
|
||||
end
|
||||
|
||||
// Output logic
|
||||
assign eq2 = e[levels][0]; // A = B if all bits are equal
|
||||
assign ltu2 = l[levels][0]; // A < B if group is less (unsigned)
|
||||
// A < B signed if less than unsigned and msb is not < unsigned, or if A negative and B positive
|
||||
assign lt2 = ltu2 & ~l[0][WIDTH-1] | a[WIDTH-1] & ~b[WIDTH-1];
|
||||
assign flags = {eq2, lt2, ltu2};
|
||||
/* verilator lint_on UNOPTFLAT */
|
||||
endmodule
|
||||
|
||||
|
||||
@ -31,10 +31,7 @@
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module gsharePredictor
|
||||
#(parameter int k = 10
|
||||
)
|
||||
(input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallE,
|
||||
@ -52,8 +49,8 @@ module gsharePredictor
|
||||
input logic [1:0] UpdateBPPredE
|
||||
|
||||
);
|
||||
logic [k+1:0] GHR, GHRNext;
|
||||
logic [k-1:0] PHTUpdateAdr, PHTUpdateAdr0, PHTUpdateAdr1;
|
||||
logic [`BPRED_SIZE+1:0] GHR, GHRNext;
|
||||
logic [`BPRED_SIZE-1:0] PHTUpdateAdr, PHTUpdateAdr0, PHTUpdateAdr1;
|
||||
logic PHTUpdateEN;
|
||||
logic BPClassWrongNonCFI;
|
||||
logic BPClassWrongCFI;
|
||||
@ -63,7 +60,7 @@ module gsharePredictor
|
||||
|
||||
logic [6:0] GHRMuxSel;
|
||||
logic GHRUpdateEN;
|
||||
logic [k-1:0] GHRLookup;
|
||||
logic [`BPRED_SIZE-1:0] GHRLookup;
|
||||
|
||||
assign BPClassRightNonCFI = ~BPInstrClassE[0] & ~InstrClassE[0];
|
||||
assign BPClassWrongCFI = ~BPInstrClassE[0] & InstrClassE[0];
|
||||
@ -85,18 +82,18 @@ module gsharePredictor
|
||||
// hoping this created a AND-OR mux.
|
||||
always_comb begin
|
||||
case (GHRMuxSel)
|
||||
7'b000_0001: GHRNext = GHR[k-1+2:0]; // no change
|
||||
7'b000_0010: GHRNext = {GHR[k-2+2:0], PCSrcE}; // branch update
|
||||
7'b000_0100: GHRNext = {1'b0, GHR[k+1:1]}; // repair 1
|
||||
7'b000_1000: GHRNext = {GHR[k-1+2:1], PCSrcE}; // branch update with mis prediction correction
|
||||
7'b001_0000: GHRNext = {2'b00, GHR[k+1:2]}; // repair 2
|
||||
7'b010_0000: GHRNext = {1'b0, GHR[k+1:2], PCSrcE}; // branch update + repair 1
|
||||
7'b100_0000: GHRNext = {GHR[k-2+2:0], BPPredF[1]}; // speculative update
|
||||
default: GHRNext = GHR[k-1+2:0];
|
||||
7'b000_0001: GHRNext = GHR[`BPRED_SIZE-1+2:0]; // no change
|
||||
7'b000_0010: GHRNext = {GHR[`BPRED_SIZE-2+2:0], PCSrcE}; // branch update
|
||||
7'b000_0100: GHRNext = {1'b0, GHR[`BPRED_SIZE+1:1]}; // repair 1
|
||||
7'b000_1000: GHRNext = {GHR[`BPRED_SIZE-1+2:1], PCSrcE}; // branch update with mis prediction correction
|
||||
7'b001_0000: GHRNext = {2'b00, GHR[`BPRED_SIZE+1:2]}; // repair 2
|
||||
7'b010_0000: GHRNext = {1'b0, GHR[`BPRED_SIZE+1:2], PCSrcE}; // branch update + repair 1
|
||||
7'b100_0000: GHRNext = {GHR[`BPRED_SIZE-2+2:0], BPPredF[1]}; // speculative update
|
||||
default: GHRNext = GHR[`BPRED_SIZE-1+2:0];
|
||||
endcase
|
||||
end
|
||||
|
||||
flopenr #(k+2) GlobalHistoryRegister(.clk(clk),
|
||||
flopenr #(`BPRED_SIZE+2) GlobalHistoryRegister(.clk(clk),
|
||||
.reset(reset),
|
||||
.en((GHRUpdateEN)),
|
||||
.d(GHRNext),
|
||||
@ -105,21 +102,21 @@ module gsharePredictor
|
||||
// if actively updating the GHR at the time of prediction we want to us
|
||||
// GHRNext as the lookup rather than GHR.
|
||||
|
||||
assign PHTUpdateAdr0 = InstrClassE[0] ? GHR[k:1] : GHR[k-1:0];
|
||||
assign PHTUpdateAdr1 = InstrClassE[0] ? GHR[k+1:2] : GHR[k:1];
|
||||
assign PHTUpdateAdr0 = InstrClassE[0] ? GHR[`BPRED_SIZE:1] : GHR[`BPRED_SIZE-1:0];
|
||||
assign PHTUpdateAdr1 = InstrClassE[0] ? GHR[`BPRED_SIZE+1:2] : GHR[`BPRED_SIZE:1];
|
||||
assign PHTUpdateAdr = BPInstrClassD[0] ? PHTUpdateAdr1 : PHTUpdateAdr0;
|
||||
assign PHTUpdateEN = InstrClassE[0] & ~StallE;
|
||||
|
||||
assign GHRLookup = |GHRMuxSel[6:1] ? GHRNext[k-1:0] : GHR[k-1:0];
|
||||
assign GHRLookup = |GHRMuxSel[6:1] ? GHRNext[`BPRED_SIZE-1:0] : GHR[`BPRED_SIZE-1:0];
|
||||
|
||||
// Make Prediction by reading the correct address in the PHT and also update the new address in the PHT
|
||||
SRAM2P1R1W #(k, 2) PHT(.clk(clk),
|
||||
SRAM2P1R1W #(`BPRED_SIZE, 2) PHT(.clk(clk),
|
||||
.reset(reset),
|
||||
//.RA1(GHR[k-1:0]),
|
||||
.RA1(GHRLookup ^ PCNextF[k:1]),
|
||||
//.RA1(GHR[`BPRED_SIZE-1:0]),
|
||||
.RA1(GHRLookup ^ PCNextF[`BPRED_SIZE:1]),
|
||||
.RD1(BPPredF),
|
||||
.REN1(~StallF),
|
||||
.WA1(PHTUpdateAdr ^ PCE[k:1]),
|
||||
.WA1(PHTUpdateAdr ^ PCE[`BPRED_SIZE:1]),
|
||||
.WD1(UpdateBPPredE),
|
||||
.WEN1(PHTUpdateEN),
|
||||
.BitWEN1(2'b11));
|
||||
|
||||
@ -65,7 +65,6 @@ module ifu (
|
||||
output logic InstrPageFaultF,
|
||||
output logic IllegalIEUInstrFaultD,
|
||||
output logic InstrMisalignedFaultM,
|
||||
output logic [`XLEN-1:0] InstrMisalignedAdrM,
|
||||
input logic ExceptionM,
|
||||
// mmu management
|
||||
input logic [1:0] PrivilegeModeW,
|
||||
@ -140,7 +139,7 @@ module ifu (
|
||||
// WFI
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
assign wfiD = (InstrD[6:0] == 7'b111011 && InstrD[31:20] == 12'b000100000101); // WFI in decode stage
|
||||
assign wfiD = (InstrD[6:0] == 7'b1110011 && InstrD[31:20] == 12'b000100000101); // WFI in decode stage
|
||||
assign InstrNextF = wfiD ? InstrD : PostSpillInstrRawF; // on WFI, keep replaying WFI
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
@ -330,7 +329,6 @@ module ifu (
|
||||
// Traps: Can’t happen. The bottom two bits of MTVEC are ignored so the trap always is to a multiple of 4. See 3.1.7 of the privileged spec.
|
||||
assign BranchMisalignedFaultE = (IEUAdrE[1] & ~`C_SUPPORTED) & PCSrcE;
|
||||
flopenr #(1) InstrMisalginedReg(clk, reset, ~StallM, BranchMisalignedFaultE, InstrMisalignedFaultM);
|
||||
flopenr #(`XLEN) InstrMisalignedAdrReg(clk, reset, ~StallM, PCNextF, InstrMisalignedAdrM);
|
||||
|
||||
// Instruction and PC/PCLink pipeline registers
|
||||
mux2 #(32) FlushInstrEMux(InstrD, nop, FlushE, NextInstrD);
|
||||
|
||||
@ -32,7 +32,7 @@
|
||||
|
||||
module atomic (
|
||||
input logic clk,
|
||||
input logic reset, FlushW, CPUBusy,
|
||||
input logic reset, FlushW, StallW,
|
||||
input logic [`XLEN-1:0] ReadDataM,
|
||||
input logic [`XLEN-1:0] LSUWriteDataM,
|
||||
input logic [`PA_BITS-1:0] LSUPAdrM,
|
||||
@ -41,7 +41,7 @@ module atomic (
|
||||
input logic [1:0] LSUAtomicM,
|
||||
input logic [1:0] PreLSURWM,
|
||||
input logic IgnoreRequest,
|
||||
output logic [`XLEN-1:0] FinalAMOWriteDataM,
|
||||
output logic [`XLEN-1:0] AMOWriteDataM,
|
||||
output logic SquashSCW,
|
||||
output logic [1:0] LSURWM);
|
||||
|
||||
@ -50,9 +50,9 @@ module atomic (
|
||||
|
||||
amoalu amoalu(.srca(ReadDataM), .srcb(LSUWriteDataM), .funct(LSUFunct7M), .width(LSUFunct3M[1:0]),
|
||||
.result(AMOResult));
|
||||
mux2 #(`XLEN) wdmux(LSUWriteDataM, AMOResult, LSUAtomicM[1], FinalAMOWriteDataM);
|
||||
mux2 #(`XLEN) wdmux(LSUWriteDataM, AMOResult, LSUAtomicM[1], AMOWriteDataM);
|
||||
assign MemReadM = PreLSURWM[1] & ~IgnoreRequest;
|
||||
lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .PreLSURWM, .LSUAtomicM, .LSUPAdrM,
|
||||
lrsc lrsc(.clk, .reset, .FlushW, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .LSUPAdrM,
|
||||
.SquashSCW, .LSURWM);
|
||||
|
||||
endmodule
|
||||
|
||||
@ -34,7 +34,7 @@
|
||||
module lrsc
|
||||
(
|
||||
input logic clk, reset,
|
||||
input logic FlushW, CPUBusy,
|
||||
input logic FlushW, StallW,
|
||||
input logic MemReadM,
|
||||
input logic [1:0] PreLSURWM,
|
||||
output logic [1:0] LSURWM,
|
||||
@ -55,10 +55,11 @@ module lrsc
|
||||
assign LSURWM = SquashSCM ? 2'b00 : PreLSURWM;
|
||||
always_comb begin // ReservationValidM (next value of valid reservation)
|
||||
if (lrM) ReservationValidM = 1; // set valid on load reserve
|
||||
else if (scM | WriteAdrMatchM) ReservationValidM = 0; // clear valid on store to same address or any sc
|
||||
// if we implement multiple harts invalidate reservation if another hart stores to this reservation.
|
||||
else if (scM) ReservationValidM = 0; // clear valid on store to same address or any sc
|
||||
else ReservationValidM = ReservationValidW; // otherwise don't change valid
|
||||
end
|
||||
flopenrc #(`PA_BITS-2) resadrreg(clk, reset, FlushW, lrM, LSUPAdrM[`PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid
|
||||
flopenrc #(1) resvldreg(clk, reset, FlushW, lrM, ReservationValidM, ReservationValidW);
|
||||
flopenrc #(1) squashreg(clk, reset, FlushW, ~CPUBusy, SquashSCM, SquashSCW);
|
||||
flopenr #(`PA_BITS-2) resadrreg(clk, reset, lrM & ~StallW, LSUPAdrM[`PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid
|
||||
flopenr #(1) resvldreg(clk, reset, ~StallW, ReservationValidM, ReservationValidW);
|
||||
flopenr #(1) squashreg(clk, reset, ~StallW, SquashSCM, SquashSCW);
|
||||
endmodule
|
||||
|
||||
@ -145,6 +145,7 @@ module lsu (
|
||||
assign CommittedM = SelHPTW | DCacheCommittedM | BusCommittedM;
|
||||
|
||||
// MMU and Misalignment fault logic required if privileged unit exists
|
||||
// *** DH: This is too strong a requirement. Separate MMU in `VIRTMEM_SUPPORTED from simpler faults in `ZICSR_SUPPORTED
|
||||
if(`ZICSR_SUPPORTED == 1) begin : dmmu
|
||||
logic DisableTranslation;
|
||||
assign DisableTranslation = SelHPTW | FlushDCacheM;
|
||||
@ -181,7 +182,7 @@ module lsu (
|
||||
// Memory System
|
||||
// Either Data Cache or Data Tightly Integrated Memory or just bus interface
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
logic [`XLEN-1:0] FinalAMOWriteDataM, FinalWriteDataM;
|
||||
logic [`XLEN-1:0] AMOWriteDataM, FinalWriteDataM;
|
||||
logic [`XLEN-1:0] ReadDataWordM;
|
||||
logic [`XLEN-1:0] ReadDataWordMuxM;
|
||||
logic IgnoreRequest;
|
||||
@ -253,15 +254,15 @@ module lsu (
|
||||
// Atomic operations
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
if (`A_SUPPORTED) begin:atomic
|
||||
atomic atomic(.clk, .reset, .FlushW, .CPUBusy, .ReadDataM, .LSUWriteDataM, .LSUPAdrM,
|
||||
atomic atomic(.clk, .reset, .FlushW, .StallW, .ReadDataM, .LSUWriteDataM, .LSUPAdrM,
|
||||
.LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest,
|
||||
.FinalAMOWriteDataM, .SquashSCW, .LSURWM);
|
||||
.AMOWriteDataM, .SquashSCW, .LSURWM);
|
||||
end else begin:lrsc
|
||||
assign SquashSCW = 0; assign LSURWM = PreLSURWM; assign FinalAMOWriteDataM = LSUWriteDataM;
|
||||
assign SquashSCW = 0; assign LSURWM = PreLSURWM; assign AMOWriteDataM = LSUWriteDataM;
|
||||
end
|
||||
|
||||
subwordwrite subwordwrite(.LSUPAdrM(LSUPAdrM[2:0]),
|
||||
.LSUFunct3M, .FinalAMOWriteDataM, .FinalWriteDataM, .ByteMaskM);
|
||||
.LSUFunct3M, .AMOWriteDataM, .FinalWriteDataM, .ByteMaskM);
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
@ -33,55 +33,30 @@
|
||||
module subwordwrite (
|
||||
input logic [2:0] LSUPAdrM,
|
||||
input logic [2:0] LSUFunct3M,
|
||||
input logic [`XLEN-1:0] FinalAMOWriteDataM,
|
||||
input logic [`XLEN-1:0] AMOWriteDataM,
|
||||
output logic [`XLEN-1:0] FinalWriteDataM,
|
||||
output logic [`XLEN/8-1:0] ByteMaskM
|
||||
);
|
||||
|
||||
logic [`XLEN-1:0] WriteDataSubwordDuplicated;
|
||||
);
|
||||
|
||||
swbytemask swbytemask(.HSIZED({LSUFunct3M[2], 1'b0, LSUFunct3M[1:0]}), .HADDRD(LSUPAdrM),
|
||||
.ByteMask(ByteMaskM));
|
||||
// Compute byte masks
|
||||
swbytemask swbytemask(.Size(LSUFunct3M[1:0]), .Adr(LSUPAdrM), .ByteMask(ByteMaskM));
|
||||
|
||||
// Replicate data for subword writes
|
||||
if (`XLEN == 64) begin:sww
|
||||
// Handle subword writes
|
||||
always_comb
|
||||
case(LSUFunct3M[1:0])
|
||||
2'b00: WriteDataSubwordDuplicated = {8{FinalAMOWriteDataM[7:0]}}; // sb
|
||||
2'b01: WriteDataSubwordDuplicated = {4{FinalAMOWriteDataM[15:0]}}; // sh
|
||||
2'b10: WriteDataSubwordDuplicated = {2{FinalAMOWriteDataM[31:0]}}; // sw
|
||||
2'b11: WriteDataSubwordDuplicated = FinalAMOWriteDataM; // sw
|
||||
2'b00: FinalWriteDataM = {8{AMOWriteDataM[7:0]}}; // sb
|
||||
2'b01: FinalWriteDataM = {4{AMOWriteDataM[15:0]}}; // sh
|
||||
2'b10: FinalWriteDataM = {2{AMOWriteDataM[31:0]}}; // sw
|
||||
2'b11: FinalWriteDataM = AMOWriteDataM; // sw
|
||||
endcase
|
||||
|
||||
always_comb begin
|
||||
FinalWriteDataM='0;
|
||||
if (ByteMaskM[0]) FinalWriteDataM[7:0] = WriteDataSubwordDuplicated[7:0];
|
||||
if (ByteMaskM[1]) FinalWriteDataM[15:8] = WriteDataSubwordDuplicated[15:8];
|
||||
if (ByteMaskM[2]) FinalWriteDataM[23:16] = WriteDataSubwordDuplicated[23:16];
|
||||
if (ByteMaskM[3]) FinalWriteDataM[31:24] = WriteDataSubwordDuplicated[31:24];
|
||||
if (ByteMaskM[4]) FinalWriteDataM[39:32] = WriteDataSubwordDuplicated[39:32];
|
||||
if (ByteMaskM[5]) FinalWriteDataM[47:40] = WriteDataSubwordDuplicated[47:40];
|
||||
if (ByteMaskM[6]) FinalWriteDataM[55:48] = WriteDataSubwordDuplicated[55:48];
|
||||
if (ByteMaskM[7]) FinalWriteDataM[63:56] = WriteDataSubwordDuplicated[63:56];
|
||||
end
|
||||
|
||||
end else begin:sww // 32-bit
|
||||
// Handle subword writes
|
||||
always_comb
|
||||
case(LSUFunct3M[1:0])
|
||||
2'b00: WriteDataSubwordDuplicated = {4{FinalAMOWriteDataM[7:0]}}; // sb
|
||||
2'b01: WriteDataSubwordDuplicated = {2{FinalAMOWriteDataM[15:0]}}; // sh
|
||||
2'b10: WriteDataSubwordDuplicated = FinalAMOWriteDataM; // sw
|
||||
default: WriteDataSubwordDuplicated = FinalAMOWriteDataM; // shouldn't happen
|
||||
2'b00: FinalWriteDataM = {4{AMOWriteDataM[7:0]}}; // sb
|
||||
2'b01: FinalWriteDataM = {2{AMOWriteDataM[15:0]}}; // sh
|
||||
2'b10: FinalWriteDataM = AMOWriteDataM; // sw
|
||||
default: FinalWriteDataM = AMOWriteDataM; // shouldn't happen
|
||||
endcase
|
||||
|
||||
always_comb begin
|
||||
FinalWriteDataM='0;
|
||||
if (ByteMaskM[0]) FinalWriteDataM[7:0] = WriteDataSubwordDuplicated[7:0];
|
||||
if (ByteMaskM[1]) FinalWriteDataM[15:8] = WriteDataSubwordDuplicated[15:8];
|
||||
if (ByteMaskM[2]) FinalWriteDataM[23:16] = WriteDataSubwordDuplicated[23:16];
|
||||
if (ByteMaskM[3]) FinalWriteDataM[31:24] = WriteDataSubwordDuplicated[31:24];
|
||||
end
|
||||
|
||||
end
|
||||
endmodule
|
||||
|
||||
@ -31,32 +31,32 @@
|
||||
`include "wally-config.vh"
|
||||
|
||||
module swbytemask (
|
||||
input logic [3:0] HSIZED,
|
||||
input logic [2:0] HADDRD,
|
||||
input logic [1:0] Size,
|
||||
input logic [2:0] Adr,
|
||||
output logic [`XLEN/8-1:0] ByteMask);
|
||||
|
||||
|
||||
if(`XLEN == 64) begin
|
||||
always_comb begin
|
||||
case(HSIZED[1:0])
|
||||
2'b00: begin ByteMask = 8'b00000000; ByteMask[HADDRD[2:0]] = 1; end // sb
|
||||
2'b01: case (HADDRD[2:1])
|
||||
case(Size[1:0])
|
||||
2'b00: begin ByteMask = 8'b00000000; ByteMask[Adr[2:0]] = 1; end // sb
|
||||
2'b01: case (Adr[2:1])
|
||||
2'b00: ByteMask = 8'b0000_0011;
|
||||
2'b01: ByteMask = 8'b0000_1100;
|
||||
2'b10: ByteMask = 8'b0011_0000;
|
||||
2'b11: ByteMask = 8'b1100_0000;
|
||||
endcase
|
||||
2'b10: if (HADDRD[2]) ByteMask = 8'b11110000;
|
||||
else ByteMask = 8'b00001111;
|
||||
2'b10: if (Adr[2]) ByteMask = 8'b11110000;
|
||||
else ByteMask = 8'b00001111;
|
||||
2'b11: ByteMask = 8'b1111_1111;
|
||||
endcase
|
||||
end
|
||||
end else begin
|
||||
always_comb begin
|
||||
case(HSIZED[1:0])
|
||||
2'b00: begin ByteMask = 4'b0000; ByteMask[HADDRD[1:0]] = 1; end // sb
|
||||
2'b01: if (HADDRD[1]) ByteMask = 4'b1100;
|
||||
else ByteMask = 4'b0011;
|
||||
case(Size[1:0])
|
||||
2'b00: begin ByteMask = 4'b0000; ByteMask[Adr[1:0]] = 1; end // sb
|
||||
2'b01: if (Adr[1]) ByteMask = 4'b1100;
|
||||
else ByteMask = 4'b0011;
|
||||
2'b10: ByteMask = 4'b1111;
|
||||
default: ByteMask = 4'b1111;
|
||||
endcase
|
||||
|
||||
@ -81,7 +81,7 @@ module csr #(parameter
|
||||
logic [`XLEN-1:0] CSRRWM, CSRRSM, CSRRCM;
|
||||
(* mark_debug = "true" *) logic [`XLEN-1:0] CSRWriteValM;
|
||||
|
||||
(* mark_debug = "true" *) logic [`XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW;
|
||||
(* mark_debug = "true" *) logic [`XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, MSTATUSH_REGW;
|
||||
logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW;
|
||||
logic WriteMSTATUSM, WriteSSTATUSM;
|
||||
logic CSRMWriteM, CSRSWriteM, CSRUWriteM;
|
||||
@ -139,7 +139,7 @@ module csr #(parameter
|
||||
.WriteMSTATUSM, .WriteSSTATUSM,
|
||||
.TrapM, .FRegWriteM, .NextPrivilegeModeM, .PrivilegeModeW,
|
||||
.mretM, .sretM, .WriteFRMM, .WriteFFLAGSM, .CSRWriteValM,
|
||||
.MSTATUS_REGW, .SSTATUS_REGW,
|
||||
.MSTATUS_REGW, .SSTATUS_REGW, .MSTATUSH_REGW,
|
||||
.STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TW,
|
||||
.STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TVM);
|
||||
csrc counters(.clk, .reset,
|
||||
@ -152,7 +152,7 @@ module csr #(parameter
|
||||
.MTIME_CLINT, .CSRCReadValM, .IllegalCSRCAccessM);
|
||||
csrm csrm(.clk, .reset, .InstrValidNotFlushedM, .StallW,
|
||||
.CSRMWriteM, .MTrapM, .CSRAdrM,
|
||||
.NextEPCM, .NextCauseM, .NextMtvalM, .MSTATUS_REGW,
|
||||
.NextEPCM, .NextCauseM, .NextMtvalM, .MSTATUS_REGW, .MSTATUSH_REGW,
|
||||
.CSRWriteValM, .CSRMReadValM, .MTVEC_REGW,
|
||||
.MEPC_REGW, .MCOUNTEREN_REGW, .MCOUNTINHIBIT_REGW,
|
||||
.MEDELEG_REGW, .MIDELEG_REGW,.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
|
||||
|
||||
@ -64,12 +64,8 @@ module csrc #(parameter
|
||||
);
|
||||
|
||||
if (`ZICOUNTERS_SUPPORTED) begin:counters
|
||||
(* mark_debug = "true" *) logic [63:0] CYCLE_REGW, INSTRET_REGW;
|
||||
logic [63:0] CYCLEPlusM, INSTRETPlusM;
|
||||
logic [`XLEN-1:0] NextCYCLEM, NextINSTRETM;
|
||||
logic WriteCYCLEM, WriteINSTRETM;
|
||||
logic [4:0] CounterNumM;
|
||||
logic [`XLEN-1:0] HPMCOUNTER_REGW[`COUNTERS-1:0];
|
||||
(* mark_debug = "true" *) logic [`XLEN-1:0] HPMCOUNTER_REGW[`COUNTERS-1:0];
|
||||
logic [`XLEN-1:0] HPMCOUNTERH_REGW[`COUNTERS-1:0];
|
||||
logic InstrValidNotFlushedM;
|
||||
logic LoadStallE, LoadStallM;
|
||||
|
||||
@ -52,6 +52,7 @@ module csrm #(parameter
|
||||
MCAUSE = 12'h342,
|
||||
MTVAL = 12'h343,
|
||||
MIP = 12'h344,
|
||||
MTINST = 12'h34A,
|
||||
PMPCFG0 = 12'h3A0,
|
||||
// .. up to 15 more at consecutive addresses
|
||||
PMPADDR0 = 12'h3B0,
|
||||
@ -73,7 +74,7 @@ module csrm #(parameter
|
||||
input logic InstrValidNotFlushedM, StallW,
|
||||
input logic CSRMWriteM, MTrapM,
|
||||
input logic [11:0] CSRAdrM,
|
||||
input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, MSTATUS_REGW,
|
||||
input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, MSTATUS_REGW, MSTATUSH_REGW,
|
||||
input logic [`XLEN-1:0] CSRWriteValM,
|
||||
output logic [`XLEN-1:0] CSRMReadValM, MTVEC_REGW,
|
||||
(* mark_debug = "true" *) output logic [`XLEN-1:0] MEPC_REGW,
|
||||
@ -133,6 +134,7 @@ module csrm #(parameter
|
||||
|
||||
// Write machine Mode CSRs
|
||||
assign WriteMSTATUSM = CSRMWriteM & (CSRAdrM == MSTATUS) & InstrValidNotFlushedM;
|
||||
// writes to MSTATUSH are not yet supported because the register is always 0
|
||||
assign WriteMTVECM = CSRMWriteM & (CSRAdrM == MTVEC) & InstrValidNotFlushedM;
|
||||
assign WriteMEDELEGM = CSRMWriteM & (CSRAdrM == MEDELEG) & InstrValidNotFlushedM;
|
||||
assign WriteMIDELEGM = CSRMWriteM & (CSRAdrM == MIDELEG) & InstrValidNotFlushedM;
|
||||
@ -160,7 +162,6 @@ module csrm #(parameter
|
||||
flopenr #(32) MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], MCOUNTEREN_REGW);
|
||||
flopenr #(32) MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, CSRWriteValM[31:0], MCOUNTINHIBIT_REGW);
|
||||
|
||||
|
||||
// Read machine mode CSRs
|
||||
// verilator lint_off WIDTH
|
||||
logic [5:0] entry;
|
||||
@ -186,7 +187,7 @@ module csrm #(parameter
|
||||
MIMPID: CSRMReadValM = `XLEN'h100; // pipelined implementation
|
||||
MHARTID: CSRMReadValM = MHARTID_REGW; // hardwired to 0
|
||||
MSTATUS: CSRMReadValM = MSTATUS_REGW;
|
||||
MSTATUSH: CSRMReadValM = 0; // flush this out later if MBE and SBE fields are supported
|
||||
MSTATUSH: CSRMReadValM = MSTATUSH_REGW;
|
||||
MTVEC: CSRMReadValM = MTVEC_REGW;
|
||||
MEDELEG: CSRMReadValM = MEDELEG_REGW;
|
||||
MIDELEG: CSRMReadValM = {{(`XLEN-12){1'b0}}, MIDELEG_REGW};
|
||||
@ -196,6 +197,7 @@ module csrm #(parameter
|
||||
MEPC: CSRMReadValM = MEPC_REGW;
|
||||
MCAUSE: CSRMReadValM = MCAUSE_REGW;
|
||||
MTVAL: CSRMReadValM = MTVAL_REGW;
|
||||
MTINST: CSRMReadValM = 0; // implemented as trivial zero
|
||||
MCOUNTEREN:CSRMReadValM = {{(`XLEN-32){1'b0}}, MCOUNTEREN_REGW};
|
||||
MCOUNTINHIBIT:CSRMReadValM = {{(`XLEN-32){1'b0}}, MCOUNTINHIBIT_REGW};
|
||||
|
||||
|
||||
@ -39,7 +39,7 @@ module csrsr (
|
||||
input logic mretM, sretM,
|
||||
input logic WriteFRMM, WriteFFLAGSM,
|
||||
input logic [`XLEN-1:0] CSRWriteValM,
|
||||
output logic [`XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW,
|
||||
output logic [`XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, MSTATUSH_REGW,
|
||||
output logic [1:0] STATUS_MPP,
|
||||
output logic STATUS_SPP, STATUS_TSR, STATUS_TW,
|
||||
output logic STATUS_MIE, STATUS_SIE,
|
||||
@ -49,33 +49,34 @@ module csrsr (
|
||||
|
||||
logic STATUS_SD, STATUS_TW_INT, STATUS_TSR_INT, STATUS_TVM_INT, STATUS_MXR_INT, STATUS_SUM_INT, STATUS_MPRV_INT;
|
||||
logic [1:0] STATUS_SXL, STATUS_UXL, STATUS_XS, STATUS_FS, STATUS_FS_INT, STATUS_MPP_NEXT;
|
||||
logic STATUS_MPIE, STATUS_SPIE, STATUS_UPIE, STATUS_UIE;
|
||||
logic STATUS_MPIE, STATUS_SPIE, STATUS_UBE, STATUS_SBE, STATUS_MBE;
|
||||
|
||||
// STATUS REGISTER FIELD
|
||||
// See Privileged Spec Section 3.1.6
|
||||
// Lower privilege status registers are a subset of the full status register
|
||||
// *** consider adding MBE, SBE, UBE fields later from 20210108 draft spec
|
||||
// *** consider adding MBE, SBE, UBE fields, parameterized to be fixed or adjustable
|
||||
if (`XLEN==64) begin: csrsr64 // RV64
|
||||
assign MSTATUS_REGW = {STATUS_SD, 27'b0, STATUS_SXL, STATUS_UXL, 9'b0,
|
||||
assign MSTATUS_REGW = {STATUS_SD, 25'b0, STATUS_MBE, STATUS_UBE, STATUS_SXL, STATUS_UXL, 9'b0,
|
||||
STATUS_TSR, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_MPRV,
|
||||
STATUS_XS, STATUS_FS, STATUS_MPP, 2'b0,
|
||||
STATUS_SPP, STATUS_MPIE, 1'b0, STATUS_SPIE, STATUS_UPIE,
|
||||
STATUS_MIE, 1'b0, STATUS_SIE, STATUS_UIE};
|
||||
STATUS_SPP, STATUS_MPIE, STATUS_UBE, STATUS_SPIE, 1'b0,
|
||||
STATUS_MIE, 1'b0, STATUS_SIE, 1'b0};
|
||||
assign SSTATUS_REGW = {STATUS_SD, /*27'b0, */ 29'b0, /*STATUS_SXL, */ {`QEMU ? 2'b0 : STATUS_UXL}, /*9'b0, */ 12'b0,
|
||||
/*STATUS_TSR, STATUS_TW, STATUS_TVM, */STATUS_MXR, STATUS_SUM, /* STATUS_MPRV, */ 1'b0,
|
||||
STATUS_XS, STATUS_FS, /*STATUS_MPP, 2'b0*/ 4'b0,
|
||||
STATUS_SPP, /*STATUS_MPIE, 1'b0*/ 2'b0, STATUS_SPIE, STATUS_UPIE,
|
||||
/*STATUS_MIE, 1'b0*/ 2'b0, STATUS_SIE, STATUS_UIE};
|
||||
STATUS_SPP, /*STATUS_MPIE*/ 1'b0, STATUS_UBE, STATUS_SPIE,
|
||||
/*1'b0, STATUS_MIE, 1'b0*/ 3'b0, STATUS_SIE, 1'b0};
|
||||
end else begin: csrsr32 // RV32
|
||||
assign MSTATUS_REGW = {STATUS_SD, 8'b0,
|
||||
STATUS_TSR, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_MPRV,
|
||||
STATUS_XS, STATUS_FS, STATUS_MPP, 2'b0,
|
||||
STATUS_SPP, STATUS_MPIE, 1'b0, STATUS_SPIE, STATUS_UPIE, STATUS_MIE, 1'b0, STATUS_SIE, STATUS_UIE};
|
||||
STATUS_SPP, STATUS_MPIE, STATUS_UBE, STATUS_SPIE, 1'b0, STATUS_MIE, 1'b0, STATUS_SIE, 1'b0};
|
||||
assign MSTATUSH_REGW = {26'b0, STATUS_MBE, STATUS_SBE, 4'b0};
|
||||
assign SSTATUS_REGW = {STATUS_SD, 11'b0,
|
||||
/*STATUS_TSR, STATUS_TW, STATUS_TVM, */STATUS_MXR, STATUS_SUM, /* STATUS_MPRV, */ 1'b0,
|
||||
STATUS_XS, STATUS_FS, /*STATUS_MPP, 2'b0*/ 4'b0,
|
||||
STATUS_SPP, /*STATUS_MPIE, 1'b0*/ 2'b0, STATUS_SPIE, STATUS_UPIE,
|
||||
/*STATUS_MIE, 1'b0*/ 2'b0, STATUS_SIE, STATUS_UIE};
|
||||
STATUS_SPP, /*STATUS_MPIE*/ 1'b0, STATUS_UBE, STATUS_SPIE,
|
||||
/*1'b0, STATUS_MIE, 1'b0*/ 3'b0, STATUS_SIE, 1'b0};
|
||||
end
|
||||
|
||||
// harwired STATUS bits
|
||||
@ -83,6 +84,9 @@ module csrsr (
|
||||
assign STATUS_TW = (`S_SUPPORTED | `U_SUPPORTED) & STATUS_TW_INT; // override reigster with 0 if only machine mode supported
|
||||
assign STATUS_TVM = `S_SUPPORTED & STATUS_TVM_INT; // override reigster with 0 if supervisor mode not supported
|
||||
assign STATUS_MXR = `S_SUPPORTED & STATUS_MXR_INT; // override reigster with 0 if supervisor mode not supported
|
||||
assign STATUS_UBE = 0; // little-endian
|
||||
assign STATUS_SBE = 0; // little-endian
|
||||
assign STATUS_MBE = 0; // little-endian
|
||||
// SXL and UXL bits only matter for RV64. Set to 10 for RV64 if mode is supported, or 0 if not
|
||||
assign STATUS_SXL = `S_SUPPORTED ? 2'b10 : 2'b00; // 10 if supervisor mode supported
|
||||
assign STATUS_UXL = `U_SUPPORTED ? 2'b10 : 2'b00; // 10 if user mode supported
|
||||
@ -107,17 +111,15 @@ module csrsr (
|
||||
STATUS_MXR_INT <= #1 0;
|
||||
STATUS_SUM_INT <= #1 0;
|
||||
STATUS_MPRV_INT <= #1 0; // Per Priv 3.3
|
||||
STATUS_FS_INT <= #1 0;
|
||||
STATUS_FS_INT <= #1 `F_SUPPORTED ? 2'b01 : 2'b00;
|
||||
STATUS_MPP <= #1 0; //`M_MODE;
|
||||
STATUS_SPP <= #1 0; //1'b1;
|
||||
STATUS_MPIE <= #1 0; //1;
|
||||
STATUS_SPIE <= #1 0; //`S_SUPPORTED;
|
||||
STATUS_UPIE <= #1 0; // `U_SUPPORTED;
|
||||
STATUS_MIE <= #1 0; // Per Priv 3.3
|
||||
STATUS_SIE <= #1 0; //`S_SUPPORTED;
|
||||
STATUS_UIE <= #1 0; //`U_SUPPORTED;
|
||||
end else if (~StallW) begin
|
||||
if (FRegWriteM | WriteFRMM | WriteFFLAGSM) STATUS_FS_INT <= #12'b11; // mark Float State dirty *** this should happen in M stage, be part of if/else;
|
||||
if (FRegWriteM | WriteFRMM | WriteFFLAGSM) STATUS_FS_INT <= #1 2'b11; // mark Float State dirty *** this should happen in M stage, be part of if/else;
|
||||
|
||||
if (TrapM) begin
|
||||
// Update interrupt enables per Privileged Spec p. 21
|
||||
@ -128,24 +130,22 @@ module csrsr (
|
||||
STATUS_MPIE <= #1 STATUS_MIE;
|
||||
STATUS_MIE <= #1 0;
|
||||
STATUS_MPP <= #1 PrivilegeModeW;
|
||||
end else if (NextPrivilegeModeM == `S_MODE) begin
|
||||
end else begin // supervisor mode
|
||||
STATUS_SPIE <= #1 STATUS_SIE;
|
||||
STATUS_SIE <= #1 0;
|
||||
STATUS_SPP <= #1 PrivilegeModeW[0]; // *** seems to disagree with P. 56
|
||||
end else begin // user mode
|
||||
STATUS_UPIE <= #1 STATUS_UIE;
|
||||
STATUS_UIE <= #1 0;
|
||||
end
|
||||
STATUS_SPP <= #1 PrivilegeModeW[0];
|
||||
end
|
||||
end else if (mretM) begin // Privileged 3.1.6.1
|
||||
STATUS_MIE <= #1 STATUS_MPIE;
|
||||
STATUS_MPIE <= #1 1;
|
||||
STATUS_MPP <= #1 `U_SUPPORTED ? `U_MODE : `M_MODE; // per spec, not sure why
|
||||
STATUS_MPRV_INT <= #1 (STATUS_MPP == `M_MODE & STATUS_MPRV_INT); //0; // per 20210108 draft spec
|
||||
STATUS_MIE <= #1 STATUS_MPIE; // restore global interrupt enable
|
||||
STATUS_MPIE <= #1 1; //
|
||||
STATUS_MPP <= #1 `U_SUPPORTED ? `U_MODE : `M_MODE; // set MPP to lowest supported privilege level
|
||||
// STATUS_MPRV_INT <= #1 0; // changed to this by Ross to solve Linux bug; might have been s spurious disagreement with QEMU
|
||||
STATUS_MPRV_INT <= #1 STATUS_MPRV_INT & (STATUS_MPP == `M_MODE); // Seems to be given by page 21 of spec.
|
||||
end else if (sretM) begin
|
||||
STATUS_SIE <= #1 STATUS_SPIE;
|
||||
STATUS_SPIE <= #1 `S_SUPPORTED;
|
||||
STATUS_SPP <= #1 0; // Privileged 4.1.1
|
||||
STATUS_MPRV_INT <= #1 0; // per 20210108 draft spec
|
||||
STATUS_SIE <= #1 STATUS_SPIE; // restore global interrupt enable
|
||||
STATUS_SPIE <= #1 `S_SUPPORTED;
|
||||
STATUS_SPP <= #1 0; // set SPP to lowest supported privilege level to catch bugs
|
||||
STATUS_MPRV_INT <= #1 0; // always clear MPRV
|
||||
end else if (WriteMSTATUSM) begin
|
||||
STATUS_TSR_INT <= #1 CSRWriteValM[22];
|
||||
STATUS_TW_INT <= #1 CSRWriteValM[21];
|
||||
@ -158,19 +158,15 @@ module csrsr (
|
||||
STATUS_SPP <= #1 `S_SUPPORTED & CSRWriteValM[8];
|
||||
STATUS_MPIE <= #1 CSRWriteValM[7];
|
||||
STATUS_SPIE <= #1 `S_SUPPORTED & CSRWriteValM[5];
|
||||
STATUS_UPIE <= #1 `U_SUPPORTED & CSRWriteValM[4];
|
||||
STATUS_MIE <= #1 CSRWriteValM[3];
|
||||
STATUS_SIE <= #1 `S_SUPPORTED & CSRWriteValM[1];
|
||||
STATUS_UIE <= #1 `U_SUPPORTED & CSRWriteValM[0];
|
||||
end else if (WriteSSTATUSM) begin // write a subset of the STATUS bits
|
||||
STATUS_MXR_INT <= #1 CSRWriteValM[19];
|
||||
STATUS_SUM_INT <= #1 CSRWriteValM[18];
|
||||
STATUS_FS_INT <= #1 CSRWriteValM[14:13];
|
||||
STATUS_SPP <= #1 `S_SUPPORTED & CSRWriteValM[8];
|
||||
STATUS_SPIE <= #1 `S_SUPPORTED & CSRWriteValM[5];
|
||||
STATUS_UPIE <= #1 `U_SUPPORTED & CSRWriteValM[4];
|
||||
STATUS_SIE <= #1 `S_SUPPORTED & CSRWriteValM[1];
|
||||
STATUS_UIE <= #1 `U_SUPPORTED & CSRWriteValM[0];
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
@ -33,7 +33,8 @@
|
||||
|
||||
module privdec (
|
||||
input logic [31:20] InstrM,
|
||||
input logic PrivilegedM, IllegalIEUInstrFaultM, IllegalCSRAccessM, IllegalFPUInstrM, TrappedSRETM,
|
||||
input logic PrivilegedM, IllegalIEUInstrFaultM, IllegalCSRAccessM, IllegalFPUInstrM,
|
||||
input logic TrappedSRETM, WFITimeoutM,
|
||||
input logic [1:0] PrivilegeModeW,
|
||||
input logic STATUS_TSR,
|
||||
output logic IllegalInstrFaultM,
|
||||
@ -51,7 +52,6 @@ module privdec (
|
||||
assign wfiM = PrivilegedM & (InstrM[31:20] == 12'b000100000101);
|
||||
assign sfencevmaM = PrivilegedM & (InstrM[31:25] == 7'b0001001); // *** & (PrivilegedModeW == `M_MODE | ~STATUS_TVM); // *** does this work in U mode?
|
||||
assign IllegalPrivilegedInstrM = PrivilegedM & ~(sretM|mretM|ecallM|ebreakM|wfiM|sfencevmaM);
|
||||
assign IllegalInstrFaultM = (IllegalIEUInstrFaultM & IllegalFPUInstrM) | IllegalPrivilegedInstrM | IllegalCSRAccessM | TrappedSRETM; // *** generalize this for other instructions
|
||||
|
||||
// *** initially, wfi is nop
|
||||
assign IllegalInstrFaultM = (IllegalIEUInstrFaultM & IllegalFPUInstrM) | IllegalPrivilegedInstrM | IllegalCSRAccessM |
|
||||
TrappedSRETM | WFITimeoutM; // *** generalize this for other instructions
|
||||
endmodule
|
||||
|
||||
@ -57,7 +57,7 @@ module privileged (
|
||||
input logic StoreAmoMisalignedFaultM,
|
||||
input logic TimerIntM, MExtIntM, SExtIntM, SwIntM,
|
||||
input logic [63:0] MTIME_CLINT,
|
||||
input logic [`XLEN-1:0] InstrMisalignedAdrM, IEUAdrM,
|
||||
input logic [`XLEN-1:0] IEUAdrM,
|
||||
input logic [4:0] SetFflagsM,
|
||||
|
||||
// Trap signals from pmp/pma in mmu
|
||||
@ -104,6 +104,7 @@ module privileged (
|
||||
logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW;
|
||||
logic md;
|
||||
logic StallMQ;
|
||||
logic WFITimeoutM;
|
||||
|
||||
|
||||
///////////////////////////////////////////
|
||||
@ -114,24 +115,6 @@ module privileged (
|
||||
assign md = CauseM[`XLEN-1] ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM[`LOG_XLEN-1:0]];
|
||||
|
||||
// PrivilegeMode FSM
|
||||
/* -----\/----- EXCLUDED -----\/-----
|
||||
always_comb begin
|
||||
TrappedSRETM = 0;
|
||||
if (mretM) NextPrivilegeModeM = STATUS_MPP;
|
||||
else if (sretM)
|
||||
if (STATUS_TSR & PrivilegeModeW == `S_MODE) begin
|
||||
TrappedSRETM = 1;
|
||||
NextPrivilegeModeM = PrivilegeModeW;
|
||||
end else NextPrivilegeModeM = {1'b0, STATUS_SPP};
|
||||
else if (TrapM) begin // Change privilege based on DELEG registers (see 3.1.8)
|
||||
if (`S_SUPPORTED & md & (PrivilegeModeW == `U_MODE | PrivilegeModeW == `S_MODE))
|
||||
NextPrivilegeModeM = `S_MODE;
|
||||
else NextPrivilegeModeM = `M_MODE;
|
||||
end else NextPrivilegeModeM = PrivilegeModeW;
|
||||
end
|
||||
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
|
||||
always_comb begin
|
||||
if (TrapM) begin // Change privilege based on DELEG registers (see 3.1.8)
|
||||
if (`S_SUPPORTED & md & (PrivilegeModeW == `U_MODE | PrivilegeModeW == `S_MODE))
|
||||
@ -149,14 +132,22 @@ module privileged (
|
||||
|
||||
flopenl #(2) privmodereg(clk, reset, ~StallW, NextPrivilegeModeM, `M_MODE, PrivilegeModeW);
|
||||
|
||||
// *** WFI could be implemented here and depends on TW
|
||||
///////////////////////////////////////////
|
||||
// WFI timeout Privileged Spec 3.1.6.5
|
||||
///////////////////////////////////////////
|
||||
if (`U_SUPPORTED) begin
|
||||
logic [`WFI_TIMEOUT_BIT:0] WFICount, WFICountPlus1;
|
||||
assign WFICountPlus1 = WFICount + 1;
|
||||
floprc #(`WFI_TIMEOUT_BIT+1) wficountreg(clk, reset, ~wfiM, WFICountPlus1, WFICount); // count while in WFI
|
||||
assign WFITimeoutM = ((STATUS_TW & PrivilegeModeW != `M_MODE) | (`S_SUPPORTED & PrivilegeModeW == `U_MODE)) & WFICount[`WFI_TIMEOUT_BIT];
|
||||
end else assign WFITimeoutM = 0;
|
||||
|
||||
///////////////////////////////////////////
|
||||
// decode privileged instructions
|
||||
///////////////////////////////////////////
|
||||
|
||||
privdec pmd(.InstrM(InstrM[31:20]),
|
||||
.PrivilegedM, .IllegalIEUInstrFaultM, .IllegalCSRAccessM, .IllegalFPUInstrM, .TrappedSRETM,
|
||||
.PrivilegedM, .IllegalIEUInstrFaultM, .IllegalCSRAccessM, .IllegalFPUInstrM, .TrappedSRETM, .WFITimeoutM,
|
||||
.PrivilegeModeW, .STATUS_TSR, .IllegalInstrFaultM,
|
||||
.sretM, .mretM, .ecallM, .ebreakM, .wfiM, .sfencevmaM);
|
||||
|
||||
@ -231,9 +222,9 @@ module privileged (
|
||||
.MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .MIDELEG_REGW,
|
||||
.STATUS_MIE, .STATUS_SIE,
|
||||
.PCM,
|
||||
.InstrMisalignedAdrM, .IEUAdrM,
|
||||
.IEUAdrM,
|
||||
.InstrM,
|
||||
.InstrValidM, .CommittedM, .DivE,
|
||||
.InstrValidM, .CommittedM, .DivE,
|
||||
.TrapM, .MTrapM, .STrapM, .UTrapM, .RetM,
|
||||
.InterruptM,
|
||||
.ExceptionM,
|
||||
|
||||
@ -44,9 +44,9 @@ module trap (
|
||||
(* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW, MIDELEG_REGW,
|
||||
input logic STATUS_MIE, STATUS_SIE,
|
||||
input logic [`XLEN-1:0] PCM,
|
||||
input logic [`XLEN-1:0] InstrMisalignedAdrM, IEUAdrM,
|
||||
input logic [`XLEN-1:0] IEUAdrM,
|
||||
input logic [31:0] InstrM,
|
||||
input logic InstrValidM, CommittedM, DivE,
|
||||
input logic InstrValidM, CommittedM, DivE,
|
||||
output logic TrapM, MTrapM, STrapM, UTrapM, RetM,
|
||||
output logic InterruptM,
|
||||
output logic ExceptionM,
|
||||
@ -130,8 +130,8 @@ module trap (
|
||||
else if (SPendingIntsM[5]) CauseM = (1 << (`XLEN-1)) + 5; // Supervisor Timer Int handled by S-mode
|
||||
else if (InstrPageFaultM) CauseM = 12;
|
||||
else if (InstrAccessFaultM) CauseM = 1;
|
||||
else if (InstrMisalignedFaultM) CauseM = 0;
|
||||
else if (IllegalInstrFaultM) CauseM = 2;
|
||||
else if (InstrMisalignedFaultM) CauseM = 0;
|
||||
else if (BreakpointFaultM) CauseM = 3;
|
||||
else if (EcallFaultM) CauseM = {{(`XLEN-2){1'b0}}, PrivilegeModeW} + 8;
|
||||
else if (LoadMisalignedFaultM) CauseM = 4;
|
||||
@ -152,13 +152,17 @@ module trap (
|
||||
// Technically
|
||||
|
||||
always_comb
|
||||
if (InstrMisalignedFaultM) NextFaultMtvalM = InstrMisalignedAdrM;
|
||||
if (InstrPageFaultM) NextFaultMtvalM = PCM;
|
||||
else if (InstrAccessFaultM) NextFaultMtvalM = PCM;
|
||||
else if (IllegalInstrFaultM) NextFaultMtvalM = {{(`XLEN-32){1'b0}}, InstrM};
|
||||
else if (InstrMisalignedFaultM) NextFaultMtvalM = IEUAdrM;
|
||||
else if (EcallFaultM) NextFaultMtvalM = 0;
|
||||
else if (BreakpointFaultM) NextFaultMtvalM = PCM;
|
||||
else if (LoadMisalignedFaultM) NextFaultMtvalM = IEUAdrM;
|
||||
else if (StoreAmoMisalignedFaultM) NextFaultMtvalM = IEUAdrM;
|
||||
else if (BreakpointFaultM) NextFaultMtvalM = PCM;
|
||||
else if (InstrPageFaultM) NextFaultMtvalM = PCM;
|
||||
else if (LoadPageFaultM) NextFaultMtvalM = IEUAdrM;
|
||||
else if (StoreAmoPageFaultM) NextFaultMtvalM = IEUAdrM;
|
||||
else if (IllegalInstrFaultM) NextFaultMtvalM = {{(`XLEN-32){1'b0}}, InstrM};
|
||||
else if (LoadAccessFaultM) NextFaultMtvalM = IEUAdrM;
|
||||
else if (StoreAmoAccessFaultM) NextFaultMtvalM = IEUAdrM;
|
||||
else NextFaultMtvalM = 0;
|
||||
endmodule
|
||||
|
||||
@ -66,8 +66,7 @@ module clint (
|
||||
if (`XLEN==64) assign #2 entry = {HADDR[15:3], 3'b000};
|
||||
else assign #2 entry = {HADDR[15:2], 2'b00};
|
||||
|
||||
swbytemask swbytemask(.HSIZED, .HADDRD(entryd[2:0]), .ByteMask(ByteMaskM));
|
||||
|
||||
swbytemask swbytemask(.Size(HSIZED[1:0]), .Adr(entryd[2:0]), .ByteMask(ByteMaskM));
|
||||
|
||||
// DH 2/20/21: Eventually allow MTIME to run off a separate clock
|
||||
// This will require synchronizing MTIME to the system clock
|
||||
|
||||
@ -146,8 +146,8 @@ module gpio (
|
||||
|
||||
// chip i/o
|
||||
// connect OUT to IN for loopback testing
|
||||
if (`GPIO_LOOPBACK_TEST) assign input0d = GPIOPinsOut & input_en & output_en;
|
||||
else assign input0d = GPIOPinsIn & input_en;
|
||||
if (`GPIO_LOOPBACK_TEST) assign input0d = ((output_en & GPIOPinsOut) | (~output_en & GPIOPinsIn)) & input_en;
|
||||
else assign input0d = GPIOPinsIn & input_en;
|
||||
flop #(32) sync1(HCLK,input0d,input1d);
|
||||
flop #(32) sync2(HCLK,input1d,input2d);
|
||||
flop #(32) sync3(HCLK,input2d,input3d);
|
||||
|
||||
@ -56,7 +56,7 @@ module ram #(parameter BASE=0, RANGE = 65535) (
|
||||
logic memwrite;
|
||||
logic [3:0] busycount;
|
||||
|
||||
swbytemask swbytemask(.HSIZED, .HADDRD(HWADDR[2:0]), .ByteMask(ByteMaskM));
|
||||
swbytemask swbytemask(.Size(HSIZED[1:0]), .Adr(HWADDR[2:0]), .ByteMask(ByteMaskM));
|
||||
|
||||
assign initTrans = HREADY & HSELRam & (HTRANS != 2'b00);
|
||||
|
||||
|
||||
@ -54,14 +54,22 @@ module uartPC16550D(
|
||||
output logic SOUT, RTSb, DTRb, OUT1b, OUT2b
|
||||
);
|
||||
|
||||
// signal to watch
|
||||
// rxparityerr, RXBR[upper 3 bits]
|
||||
// LSR bits 1 to 4 are based on parity, overrun, and framing errors
|
||||
// txstate, rxstate
|
||||
// loop, fifoenabled
|
||||
// IER, RCR, MCR, LSR, MSR, DLL, DLM, RBR
|
||||
|
||||
|
||||
// transmit and receive states // *** neeed to work on synth warning -- it wants to make enums 32 bits by default
|
||||
typedef enum logic [1:0] {UART_IDLE, UART_ACTIVE, UART_DONE, UART_BREAK} statetype;
|
||||
|
||||
// Registers
|
||||
logic [10:0] RBR;
|
||||
logic [7:0] FCR, LCR, LSR, SCR, DLL, DLM;
|
||||
logic [3:0] IER, MSR;
|
||||
logic [4:0] MCR;
|
||||
(* mark_debug = "true" *) logic [10:0] RBR;
|
||||
(* mark_debug = "true" *) logic [7:0] FCR, LCR, LSR, SCR, DLL, DLM;
|
||||
(* mark_debug = "true" *) logic [3:0] IER, MSR;
|
||||
(* mark_debug = "true" *) logic [4:0] MCR;
|
||||
|
||||
// Syncrhonized and delayed UART signals
|
||||
logic SINd, DSRbd, DCDbd, CTSbd, RIbd;
|
||||
@ -78,7 +86,7 @@ module uartPC16550D(
|
||||
logic [16+`UART_PRESCALE-1:0] baudcount;
|
||||
logic [3:0] rxoversampledcnt, txoversampledcnt; // count oversampled-by-16
|
||||
logic [3:0] rxbitsreceived, txbitssent;
|
||||
statetype rxstate, txstate;
|
||||
(* mark_debug = "true" *) statetype rxstate, txstate;
|
||||
|
||||
// shift registrs and FIFOs
|
||||
logic [9:0] rxshiftreg;
|
||||
@ -90,11 +98,11 @@ module uartPC16550D(
|
||||
logic [3:0] rxbitsexpected, txbitsexpected;
|
||||
|
||||
// receive data
|
||||
logic [10:0] RXBR;
|
||||
(* mark_debug = "true" *) logic [10:0] RXBR;
|
||||
logic [6:0] rxtimeoutcnt;
|
||||
logic rxcentered;
|
||||
logic rxparity, rxparitybit, rxstopbit;
|
||||
logic rxparityerr, rxoverrunerr, rxframingerr, rxbreak, rxfifohaserr;
|
||||
(* mark_debug = "true" *) logic rxparityerr, rxoverrunerr, rxframingerr, rxbreak, rxfifohaserr;
|
||||
logic rxdataready;
|
||||
logic rxfifoempty, rxfifotriggered, rxfifotimeout;
|
||||
logic rxfifodmaready;
|
||||
@ -145,7 +153,8 @@ module uartPC16550D(
|
||||
if (`FPGA) begin
|
||||
//DLL <= #1 8'd38; // 35Mhz
|
||||
//DLL <= #1 8'd11; // 10 Mhz
|
||||
DLL <= #1 8'd33; // 30 Mhz
|
||||
//DLL <= #1 8'd33; // 30 Mhz
|
||||
DLL <= #1 8'd8; // 30 Mhz 230400
|
||||
DLM <= #1 8'b0;
|
||||
end else begin
|
||||
DLL <= #1 8'd1; // this cannot be zero with DLM also zer0.
|
||||
@ -162,10 +171,13 @@ module uartPC16550D(
|
||||
3'b001: if (DLAB) DLM <= #1 Din; else IER <= #1 Din[3:0];
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
// *** BUG FIX ME for now for the divider to be 38. Our clock is 35 Mhz. 35Mhz /(38 * 16) ~= 57600 baud, which is close enough to 57600 baud
|
||||
// dll = freq / (baud * 16)
|
||||
// 30Mhz / (57600 * 16) = 32.5
|
||||
// 30Mhz / (230400 * 16) = 8.13
|
||||
// freq /baud / 16 = div
|
||||
//3'b000: if (DLAB) DLL <= #1 8'd38; //else TXHR <= #1 Din; // TX handled in TX register/FIFO section
|
||||
//3'b000: if (DLAB) DLL <= #1 8'd11; //else TXHR <= #1 Din; // TX handled in
|
||||
3'b000: if (DLAB) DLL <= #1 8'd33; //else TXHR <= #1 Din; // TX handled in
|
||||
3'b000: if (DLAB) DLL <= #1 8'd8; //else TXHR <= #1 Din; // TX handled in
|
||||
3'b001: if (DLAB) DLM <= #1 8'b0; else IER <= #1 Din[3:0];
|
||||
|
||||
3'b010: FCR <= #1 {Din[7:6], 2'b0, Din[3], 2'b0, Din[0]}; // Write only FIFO Control Register; 4:5 reserved and 2:1 self-clearing
|
||||
@ -304,6 +316,9 @@ module uartPC16550D(
|
||||
end else begin
|
||||
if (rxstate == UART_DONE) begin
|
||||
RXBR <= #1 {rxoverrunerr, rxparityerr, rxframingerr, rxdata}; // load recevive buffer register
|
||||
if (rxoverrunerr) $warning("UART RX Overrun Error\n");
|
||||
if (rxparityerr) $warning("UART RX Parity Error\n");
|
||||
if (rxframingerr) $warning("UART RX Framing Error\n");
|
||||
if (fifoenabled) begin
|
||||
rxfifo[rxfifohead] <= #1 {rxoverrunerr, rxparityerr, rxframingerr, rxdata};
|
||||
rxfifohead <= #1 rxfifohead + 1;
|
||||
|
||||
@ -82,7 +82,6 @@ module wallypipelinedcore (
|
||||
logic InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM;
|
||||
logic LoadMisalignedFaultM, LoadAccessFaultM;
|
||||
logic StoreAmoMisalignedFaultM, StoreAmoAccessFaultM;
|
||||
logic [`XLEN-1:0] InstrMisalignedAdrM;
|
||||
logic InvalidateICacheM, FlushDCacheM;
|
||||
logic PCSrcE;
|
||||
logic CSRWritePendingDEM;
|
||||
@ -190,7 +189,6 @@ module wallypipelinedcore (
|
||||
// Faults
|
||||
.IllegalBaseInstrFaultD, .InstrPageFaultF,
|
||||
.IllegalIEUInstrFaultD, .InstrMisalignedFaultM,
|
||||
.InstrMisalignedAdrM,
|
||||
|
||||
// mmu management
|
||||
.PrivilegeModeW, .PTE, .PageType, .SATP_REGW,
|
||||
@ -332,7 +330,7 @@ module wallypipelinedcore (
|
||||
.LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
|
||||
.TimerIntM, .MExtIntM, .SExtIntM, .SwIntM,
|
||||
.MTIME_CLINT,
|
||||
.InstrMisalignedAdrM, .IEUAdrM,
|
||||
.IEUAdrM,
|
||||
.SetFflagsM,
|
||||
// Trap signals from pmp/pma in mmu
|
||||
// *** do these need to be split up into one for dmem and one for ifu?
|
||||
|
||||
@ -27,7 +27,7 @@
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
`define DEBUG_TRACE 2
|
||||
`define DEBUG_TRACE 0
|
||||
// Debug Levels
|
||||
// 0: don't check against QEMU
|
||||
// 1: print disagreements with QEMU, but only halt on PCW disagreements
|
||||
@ -173,10 +173,8 @@ module testbench;
|
||||
`define STATUS_SPP `CSR_BASE.csrsr.STATUS_SPP
|
||||
`define STATUS_MPIE `CSR_BASE.csrsr.STATUS_MPIE
|
||||
`define STATUS_SPIE `CSR_BASE.csrsr.STATUS_SPIE
|
||||
`define STATUS_UPIE `CSR_BASE.csrsr.STATUS_UPIE
|
||||
`define STATUS_MIE `CSR_BASE.csrsr.STATUS_MIE
|
||||
`define STATUS_SIE `CSR_BASE.csrsr.STATUS_SIE
|
||||
`define STATUS_UIE `CSR_BASE.csrsr.STATUS_UIE
|
||||
`define UART dut.uncore.uart.uart.u
|
||||
`define UART_IER `UART.IER
|
||||
`define UART_LCR `UART.LCR
|
||||
@ -446,8 +444,10 @@ module testbench;
|
||||
force {`STATUS_TSR,`STATUS_TW,`STATUS_TVM,`STATUS_MXR,`STATUS_SUM,`STATUS_MPRV} = initMSTATUS[0][22:17];
|
||||
force {`STATUS_FS,`STATUS_MPP} = initMSTATUS[0][14:11];
|
||||
force {`STATUS_SPP,`STATUS_MPIE} = initMSTATUS[0][8:7];
|
||||
force {`STATUS_SPIE,`STATUS_UPIE,`STATUS_MIE} = initMSTATUS[0][5:3];
|
||||
force {`STATUS_SIE,`STATUS_UIE} = initMSTATUS[0][1:0];
|
||||
// force {`STATUS_SPIE,`STATUS_UPIE,`STATUS_MIE} = initMSTATUS[0][5:3]; // dh removed UPIE and UIE 4/25/22 from depricated n-mode
|
||||
force {`STATUS_SPIE} = initMSTATUS[0][5];
|
||||
force {`STATUS_MIE} = initMSTATUS[0][3];
|
||||
force {`STATUS_SIE} = initMSTATUS[0][1];
|
||||
force `PLIC_INT_ENABLE = {initPLIC_INT_ENABLE[1][`PLIC_NUM_SRC:1],initPLIC_INT_ENABLE[0][`PLIC_NUM_SRC:1]}; // would need to expand into a generate loop to cover an arbitrary number of contexts
|
||||
force `INSTRET = CHECKPOINT;
|
||||
while (reset!==1) #1;
|
||||
@ -456,8 +456,8 @@ module testbench;
|
||||
release {`STATUS_TSR,`STATUS_TW,`STATUS_TVM,`STATUS_MXR,`STATUS_SUM,`STATUS_MPRV};
|
||||
release {`STATUS_FS,`STATUS_MPP};
|
||||
release {`STATUS_SPP,`STATUS_MPIE};
|
||||
release {`STATUS_SPIE,`STATUS_UPIE,`STATUS_MIE};
|
||||
release {`STATUS_SIE,`STATUS_UIE};
|
||||
release {`STATUS_SPIE,`STATUS_MIE};
|
||||
release {`STATUS_SIE};
|
||||
release `PLIC_INT_ENABLE;
|
||||
release `INSTRET;
|
||||
end
|
||||
@ -547,9 +547,10 @@ module testbench;
|
||||
if(`"STAGE`"=="M") begin \
|
||||
// override on special conditions \
|
||||
if ((dut.core.lsu.LSUPAdrM == 'h10000002) | (dut.core.lsu.LSUPAdrM == 'h10000005) | (dut.core.lsu.LSUPAdrM == 'h10000006)) begin \
|
||||
$display("%tns, %d instrs: Overwrite UART's LSR in memory stage.", $time, AttemptedInstructionCount); \
|
||||
if(!NO_IE_MTIME_CHECKPOINT) \
|
||||
if(!NO_IE_MTIME_CHECKPOINT) begin \
|
||||
$display("%tns, %d instrs: Overwrite UART's LSR in memory stage.", $time, AttemptedInstructionCount); \
|
||||
force dut.core.ieu.dp.ReadDataM = ExpectedMemReadDataM; \
|
||||
end \
|
||||
end else \
|
||||
if(!NO_IE_MTIME_CHECKPOINT) \
|
||||
release dut.core.ieu.dp.ReadDataM; \
|
||||
@ -661,7 +662,7 @@ module testbench;
|
||||
`checkEQ("PCW",PCW,ExpectedPCW)
|
||||
//`checkEQ("InstrW",InstrW,ExpectedInstrW) <-- not viable because of
|
||||
// compressed to uncompressed conversion
|
||||
`checkEQ("Instr Count",dut.core.priv.priv.csr.counters.counters.INSTRET_REGW,InstrCountW)
|
||||
`checkEQ("Instr Count",dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2],InstrCountW)
|
||||
#2; // delay 2 ns.
|
||||
if(`DEBUG_TRACE >= 5) begin
|
||||
$display("%tns, %d instrs: Reg Write Address %02d ? expected value: %02d", $time, AttemptedInstructionCount, dut.core.ieu.dp.regf.a3, ExpectedRegAdrW);
|
||||
|
||||
@ -361,8 +361,8 @@ module riscvassertions;
|
||||
// assert (`MEM_DCACHE == 0 | `MEM_DTIM == 0) else $error("Can't simultaneously have a data cache and TIM");
|
||||
assert (`DMEM == `MEM_CACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache");
|
||||
assert (`IMEM == `MEM_CACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache");
|
||||
assert (`DMEM == `MEM_CACHE | `DBUS ==0) else $error("Dcache rquires DBUS.");
|
||||
assert (`IMEM == `MEM_CACHE | `IBUS ==0) else $error("Icache rquires IBUS.");
|
||||
//assert (`DMEM == `MEM_CACHE | `DBUS ==0) else $error("Dcache rquires DBUS.");
|
||||
//assert (`IMEM == `MEM_CACHE | `IBUS ==0) else $error("Icache rquires IBUS.");
|
||||
end
|
||||
endmodule
|
||||
|
||||
|
||||
@ -47,7 +47,8 @@ string tvpaths[] = '{
|
||||
string wally64a[] = '{
|
||||
`WALLYTEST,
|
||||
"rv64i_m/privilege/WALLY-AMO", "2210",
|
||||
"rv64i_m/privilege/WALLY-LRSC", "2410"
|
||||
"rv64i_m/privilege/WALLY-LRSC", "2410",
|
||||
"rv64i_m/privilege/WALLY-status-fp-enabled-01", "50a0"
|
||||
};
|
||||
|
||||
string wally32a[] = '{
|
||||
@ -1467,11 +1468,22 @@ string imperas32f[] = '{
|
||||
"rv64i_m/privilege/WALLY-MTVEC", "002090",
|
||||
"rv64i_m/privilege/WALLY-MVENDORID", "004090", */
|
||||
"rv64i_m/privilege/WALLY-PMA", "0050a0",
|
||||
"rv64i_m/privilege/WALLY-PMP", "0050a0"
|
||||
"rv64i_m/privilege/WALLY-PMP", "0050a0",
|
||||
// "rv64i_m/privilege/WALLY-SCAUSE", "002090",
|
||||
// "rv64i_m/privilege/WALLY-scratch-01", "0040a0",
|
||||
// "rv64i_m/privilege/WALLY-sscratch-s-01", "0040a0",
|
||||
// "rv64i_m/privilege/WALLY-trap-01", "0050a0"
|
||||
"rv64i_m/privilege/WALLY-trap-01", "0050a0",
|
||||
"rv64i_m/privilege/WALLY-trap-s-01", "0050a0",
|
||||
"rv64i_m/privilege/WALLY-trap-u-01", "0050a0",
|
||||
"rv64i_m/privilege/WALLY-MIE-01", "0050a0",
|
||||
"rv64i_m/privilege/WALLY-mtvec-01", "0050a0",
|
||||
"rv64i_m/privilege/WALLY-stvec-01", "0050a0",
|
||||
"rv64i_m/privilege/WALLY-PIE-stack-01", "0050a0",
|
||||
"rv64i_m/privilege/WALLY-PIE-stack-s-01", "0050a0",
|
||||
"rv64i_m/privilege/WALLY-trap-sret-01", "0050a0",
|
||||
// "rv64i_m/privilege/WALLY-status-tw-01", "0050a0",
|
||||
"rv64i_m/privilege/WALLY-WFI-01", "0050a0",
|
||||
"rv64i_m/privilege/WALLY-status-fp-disabled-01", "50a0"
|
||||
// "rv64i_m/privilege/WALLY-STVEC", "002090",
|
||||
// "rv64i_m/privilege/WALLY-UCAUSE", "002090",
|
||||
|
||||
@ -1534,15 +1546,23 @@ string wally32i[] = '{
|
||||
|
||||
string wally32priv[] = '{
|
||||
`WALLYTEST,
|
||||
"rv32i_m/privilege/WALLY-CSR-permission-s-01", "004060",
|
||||
"rv32i_m/privilege/WALLY-CSR-permission-u-01", "004060",
|
||||
"rv32i_m/privilege/WALLY-minfo-01", "004060",
|
||||
"rv32i_m/privilege/WALLY-misa-01", "004060",
|
||||
"rv32i_m/privilege/WALLY-MMU-SV32", "004060",
|
||||
"rv32i_m/privilege/WALLY-PMA", "004060",
|
||||
"rv32i_m/privilege/WALLY-PMP", "004060",
|
||||
"rv32i_m/privilege/WALLY-scratch-01", "004060",
|
||||
"rv32i_m/privilege/WALLY-sscratch-s-01", "004060"
|
||||
"rv32i_m/privilege/WALLY-CSR-permission-s-01", "006080",
|
||||
"rv32i_m/privilege/WALLY-CSR-permission-u-01", "006080",
|
||||
"rv32i_m/privilege/WALLY-minfo-01", "005080",
|
||||
"rv32i_m/privilege/WALLY-misa-01", "005080",
|
||||
"rv32i_m/privilege/WALLY-MMU-SV32", "005080",
|
||||
"rv32i_m/privilege/WALLY-PMA", "005080",
|
||||
"rv32i_m/privilege/WALLY-PMP", "005080",
|
||||
"rv32i_m/privilege/WALLY-trap-01", "005080",
|
||||
"rv32i_m/privilege/WALLY-trap-s-01", "005080",
|
||||
"rv32i_m/privilege/WALLY-trap-u-01", "005080",
|
||||
"rv32i_m/privilege/WALLY-MIE-01", "005080",
|
||||
"rv32i_m/privilege/WALLY-mtvec-01", "005080",
|
||||
"rv32i_m/privilege/WALLY-stvec-01", "005080",
|
||||
"rv32i_m/privilege/WALLY-PIE-stack-01", "005080",
|
||||
"rv32i_m/privilege/WALLY-PIE-stack-s-01", "005080",
|
||||
"rv32i_m/privilege/WALLY-trap-sret-01", "005080"
|
||||
|
||||
};
|
||||
|
||||
string wally32periph[] = '{
|
||||
|
||||
@ -24,9 +24,19 @@ export SAIFPOWER ?= 0
|
||||
CONFIGDIR ?= ${WALLY}/pipelined/config
|
||||
CONFIGFILES ?= $(shell find $(CONFIGDIR) -name rv*_*)
|
||||
CONFIGFILESTRIM = $(notdir $(CONFIGFILES))
|
||||
# FREQS = 25 50 100 150 200 250 300 350 400
|
||||
k = 3 6
|
||||
|
||||
ifeq ($(TECH), sky130)
|
||||
FREQS = 25 50 100 150 200 250 300 350 400
|
||||
else
|
||||
FREQS = 500 550 600 650 700 750 800 850 900 950 1000
|
||||
endif
|
||||
|
||||
print:
|
||||
echo $(CONFIGFILESTRIM)
|
||||
echo $(DIRS)
|
||||
@echo $(FREQS)
|
||||
@echo $(CONFIGFILESTRIM)
|
||||
|
||||
|
||||
default:
|
||||
@echo "Basic synthesis procedure for Wally:"
|
||||
@ -39,24 +49,25 @@ rv%.log: rv%
|
||||
echo $<
|
||||
|
||||
|
||||
DIRS = rv32e #rv32gc rv64ic rv64gc rv32ic
|
||||
DIRS = rv64gc rv32e rv32gc rv64ic rv32ic
|
||||
# DELDIRS = rv32e rv32gc rv64ic rv64gc rv32ic
|
||||
# CONFIGSUBDIRS = _FPUoff _noMulDiv _noVirtMem _PMP0 _PMP16 _orig
|
||||
|
||||
# bpred:
|
||||
# @$(foreach kval, $(k), rm -rf $(CONFIGDIR)/rv64gc_bpred_$(kval);)
|
||||
# @$(foreach kval, $(k), cp -r $(CONFIGDIR)/rv64gc $(CONFIGDIR)/rv64gc_bpred_$(kval);)
|
||||
# @$(foreach kval, $(k), sed -i 's/BPRED_SIZE.*/BPRED_SIZE $(kval)/g' $(CONFIGDIR)/rv64gc_bpred_$(kval)/wally-config.vh;)
|
||||
# @$(foreach kval, $(k), make synth DESIGN=wallypipelinedcore CONFIG=rv64gc_bpred_$(kval) TECH=sky90 FREQ=500 MAXCORES=4 --jobs;)
|
||||
copy:
|
||||
@$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_orig;)
|
||||
@$(foreach dir, $(DIRS), cp -r $(CONFIGDIR)/$(dir) $(CONFIGDIR)/$(dir)_orig;)
|
||||
@$(foreach dir, $(DIRS), sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;)
|
||||
@$(foreach dir, $(DIRS), sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;)
|
||||
@$(foreach dir, $(DIRS), sed -i "s/RAM_RANGE.*/RAM_RANGE 34\'h01FF/g" $(CONFIGDIR)/$(dir)_orig/wally-config.vh ;)
|
||||
@$(foreach dir, $(DIRS), sed -i 's/BPRED_SIZE.*/BPRED_SIZE 5/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;)
|
||||
|
||||
|
||||
del:
|
||||
@$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_orig;)
|
||||
@$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_FPUoff;)
|
||||
@$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_PMP16;)
|
||||
@$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_PMP0;)
|
||||
@$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_noVirtMem;)
|
||||
@$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_noMulDiv;)
|
||||
rm -rf $(CONFIGDIR)/*_*
|
||||
|
||||
configs: $(DIRS)
|
||||
$(DIRS):
|
||||
@ -76,23 +87,25 @@ $(DIRS):
|
||||
cp -r $(CONFIGDIR)/$@_FPUoff $(CONFIGDIR)/$@_PMP0
|
||||
sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/$@_PMP0/wally-config.vh
|
||||
|
||||
# No Virtual Memory
|
||||
rm -rf $(CONFIGDIR)/$@_noVirtMem
|
||||
cp -r $(CONFIGDIR)/$@_PMP0 $(CONFIGDIR)/$@_noVirtMem
|
||||
sed -i 's/VIRTMEM_SUPPORTED 1/VIRTMEM_SUPPORTED 0/' $(CONFIGDIR)/$@_noVirtMem/wally-config.vh
|
||||
|
||||
#no muldiv
|
||||
rm -rf $(CONFIGDIR)/$@_noMulDiv
|
||||
cp -r $(CONFIGDIR)/$@_noVirtMem $(CONFIGDIR)/$@_noMulDiv
|
||||
cp -r $(CONFIGDIR)/$@_PMP0 $(CONFIGDIR)/$@_noMulDiv
|
||||
sed -i 's/1 *<< *12/0 << 12/' $(CONFIGDIR)/$@_noMulDiv/wally-config.vh
|
||||
|
||||
#no priv
|
||||
rm -rf $(CONFIGDIR)/$@_noPriv
|
||||
cp -r $(CONFIGDIR)/$@_noMulDiv $(CONFIGDIR)/$@_noPriv
|
||||
sed -i 's/ZICSR_SUPPORTED *1/ZICSR_SUPPORTED 0/' $(CONFIGDIR)/$@_noPriv/wally-config.vh
|
||||
|
||||
freqs:
|
||||
@$(foreach freq, $(FREQS), make synth DESIGN=wallypipelinedcore CONFIG=rv32e FREQ=$(freq) MAXCORES=1;)
|
||||
|
||||
allsynth: $(CONFIGFILESTRIM)
|
||||
|
||||
$(CONFIGFILESTRIM):
|
||||
make synth DESIGN=wallypipelinedcore CONFIG=$@ TECH=sky90 FREQ=500 MAXCORES=1
|
||||
make synth DESIGN=wallypipelinedcore CONFIG=$@ TECH=sky90 FREQ=1000 MAXCORES=1
|
||||
|
||||
|
||||
|
||||
synth:
|
||||
@echo "DC Synthesis"
|
||||
@mkdir -p hdl/
|
||||
|
||||
@ -1,99 +0,0 @@
|
||||
//////////////////////////////////////////
|
||||
// wally-shared.vh
|
||||
//
|
||||
// Written: david_harris@hmc.edu 7 June 2021
|
||||
//
|
||||
// Purpose: Shared and default configuration values common to all designs
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
// include shared constants
|
||||
`include "wally-constants.vh"
|
||||
|
||||
// macros to define supported modes
|
||||
// NOTE: No hardware support fo Q yet
|
||||
|
||||
`define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
|
||||
`define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
|
||||
`define D_SUPPORTED ((`MISA >> 3) % 2 == 1)
|
||||
`define E_SUPPORTED ((`MISA >> 4) % 2 == 1)
|
||||
`define F_SUPPORTED ((`MISA >> 5) % 2 == 1)
|
||||
`define I_SUPPORTED ((`MISA >> 8) % 2 == 1)
|
||||
`define M_SUPPORTED ((`MISA >> 12) % 2 == 1)
|
||||
`define Q_SUPPORTED ((`MISA >> 16) % 2 == 1)
|
||||
`define S_SUPPORTED ((`MISA >> 18) % 2 == 1)
|
||||
`define U_SUPPORTED ((`MISA >> 20) % 2 == 1)
|
||||
|
||||
// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
|
||||
//`define N_SUPPORTED ((MISA >> 13) % 2 == 1)
|
||||
`define N_SUPPORTED 0
|
||||
|
||||
|
||||
// logarithm of XLEN, used for number of index bits to select
|
||||
`define LOG_XLEN (`XLEN == 32 ? 5 : 6)
|
||||
|
||||
// Number of 64 bit PMP Configuration Register entries (or pairs of 32 bit entries)
|
||||
`define PMPCFG_ENTRIES (`PMP_ENTRIES/8)
|
||||
|
||||
|
||||
// Floating-point half-precision
|
||||
`define ZFH_SUPPORTED 0
|
||||
|
||||
// Floating point constants for Quad, Double, Single, and Half precisions
|
||||
`define Q_LEN 128
|
||||
`define Q_NE 15
|
||||
`define Q_NF 112
|
||||
`define Q_BIAS 16383
|
||||
`define D_LEN 64
|
||||
`define D_NE 11
|
||||
`define D_NF 52
|
||||
`define D_BIAS 1023
|
||||
`define S_LEN 32
|
||||
`define S_NE 8
|
||||
`define S_NF 23
|
||||
`define S_BIAS 127
|
||||
`define H_LEN 16
|
||||
`define H_NE 5
|
||||
`define H_NF 10
|
||||
`define H_BIAS 15
|
||||
|
||||
// Floating point length FLEN and number of exponent (NE) and fraction (NF) bits
|
||||
`define FLEN (`Q_SUPPORTED ? `Q_LEN : `D_SUPPORTED ? `D_LEN : `F_SUPPORTED ? `S_LEN : `H_LEN)
|
||||
`define NE (`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `F_SUPPORTED ? `S_NE : `H_NE)
|
||||
`define NF (`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `F_SUPPORTED ? `S_NF : `H_NF)
|
||||
`define FMT (`Q_SUPPORTED ? 3 : `D_SUPPORTED ? 1 : `F_SUPPORTED ? 0 : 2)
|
||||
`define BIAS (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `F_SUPPORTED ? `S_BIAS : `H_BIAS)
|
||||
|
||||
// Floating point constants needed for FPU paramerterization
|
||||
`define FPSIZES (`Q_SUPPORTED+`D_SUPPORTED+`F_SUPPORTED+`ZFH_SUPPORTED)
|
||||
`define LEN1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_LEN : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_LEN : `H_LEN)
|
||||
`define NE1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NE : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NE : `H_NE)
|
||||
`define NF1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NF : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NF : `H_NF)
|
||||
`define FMT1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? 1 : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? 0 : 2)
|
||||
`define BIAS1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_BIAS : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_BIAS : `H_BIAS)
|
||||
`define LEN2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_LEN : `H_LEN)
|
||||
`define NE2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NE : `H_NE)
|
||||
`define NF2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NF : `H_NF)
|
||||
`define FMT2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? 0 : 2)
|
||||
`define BIAS2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_BIAS : `H_BIAS)
|
||||
|
||||
// Disable spurious Verilator warnings
|
||||
|
||||
/* verilator lint_off STMTDLY */
|
||||
/* verilator lint_off ASSIGNDLY */
|
||||
/* verilator lint_off PINCONNECTEMPTY */
|
||||
9
synthDC/runConfigsSynth.sh
Executable file
9
synthDC/runConfigsSynth.sh
Executable file
@ -0,0 +1,9 @@
|
||||
#!/usr/bin/bash
|
||||
rm -r runs/*
|
||||
make clean
|
||||
make del
|
||||
make copy
|
||||
make configs
|
||||
make allsynth
|
||||
scripts/extractSummary.py
|
||||
make del
|
||||
7
synthDC/runFrequencySynth.sh
Executable file
7
synthDC/runFrequencySynth.sh
Executable file
@ -0,0 +1,7 @@
|
||||
#!/usr/bin/bash
|
||||
rm -r runs/*
|
||||
make clean
|
||||
make del
|
||||
make freqs TECH=$1
|
||||
scripts/extractSummary.py
|
||||
make del
|
||||
50
synthDC/scripts/extractSummary.py
Executable file
50
synthDC/scripts/extractSummary.py
Executable file
@ -0,0 +1,50 @@
|
||||
#!/usr/bin/python3
|
||||
# Shreya Sanghai (ssanghai@hmc.edu) 2/28/2022
|
||||
import glob
|
||||
import re
|
||||
import csv
|
||||
import linecache
|
||||
import os
|
||||
|
||||
|
||||
def main():
|
||||
data = []
|
||||
curr_dir = os.path.dirname(os.path.abspath(__file__))
|
||||
output_file = os.path.join(curr_dir,"..","Summary.csv")
|
||||
runs_dir = os.path.join(curr_dir,"..","runs/*/reports/wallypipelinedcore_qor.rep")
|
||||
# cruns_dir = "/home/ssanghai/Desktop/cleanRun/*/reports/wallypipelinedcore_qor.rep"
|
||||
search_strings = [
|
||||
"Critical Path Length:", "Cell Area:", "Overall Compile Time:",
|
||||
"Critical Path Clk Period:", "Critical Path Slack:"
|
||||
]
|
||||
for name in glob.glob(runs_dir):
|
||||
f = open(name, 'r')
|
||||
trimName = re.search("wallypipelinedcore_(.*?)_sky",name).group(1)
|
||||
|
||||
output = {'Name':trimName}
|
||||
num_lines = len(f.readlines())
|
||||
curr_line_index = 0
|
||||
|
||||
while curr_line_index < num_lines:
|
||||
line = linecache.getline(name, curr_line_index)
|
||||
for search_string in search_strings:
|
||||
if search_string in line:
|
||||
val = getVal(name,search_string,line,curr_line_index)
|
||||
output[search_string] = val
|
||||
curr_line_index +=1
|
||||
data += [output]
|
||||
|
||||
with open(output_file, 'w') as csvfile:
|
||||
writer = csv.DictWriter(csvfile, fieldnames=['Name'] + search_strings)
|
||||
writer.writeheader()
|
||||
writer.writerows(data)
|
||||
|
||||
def getVal(filename, search_string, line, line_index):
|
||||
data = re.search(f"{search_string} *(.*?)\\n", line).group(1)
|
||||
if data == '': #sometimes data is stored in two line
|
||||
data = linecache.getline(filename, line_index+1).strip()
|
||||
return data
|
||||
|
||||
if __name__=="__main__":
|
||||
main()
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
#!/bin/sh
|
||||
|
||||
mkdir -p vectors
|
||||
./create_vectors.sh
|
||||
./remove_spaces.sh
|
||||
./append_ctrlSig.sh
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
include ../../Makefile.include
|
||||
|
||||
RVTEST_DEFINES += -march=rv$(XLEN)ia # KMG: removed compressed instructions from privileged tests
|
||||
RVTEST_DEFINES += -march=rv$(XLEN)iaf # KMG: removed compressed instructions from privileged tests
|
||||
|
||||
$(eval $(call compile_template,-march=rv32iac -mabi=ilp32 -Drvtest_mtrap_routine=True -DXLEN=$(XLEN)))
|
||||
$(eval $(call compile_template,-march=rv32iaf -mabi=ilp32 -Drvtest_mtrap_routine=True -DXLEN=$(XLEN)))
|
||||
|
||||
@ -34,12 +34,22 @@ rv32i_sc_tests = \
|
||||
WALLY-CSR-permission-u-01 \
|
||||
WALLY-minfo-01 \
|
||||
WALLY-misa-01 \
|
||||
WALLY-scratch-01 \
|
||||
WALLY-sscratch-s-01 \
|
||||
WALLY-AMO \
|
||||
WALLY-LRSC
|
||||
WALLY-LRSC \
|
||||
# WALLY-scratch-01 \
|
||||
# WALLY-sscratch-s-01 \
|
||||
|
||||
target_tests_nosim = WALLY-PMA \
|
||||
target_tests_nosim = \
|
||||
WALLY-PMA \
|
||||
WALLY-mtvec-01 \
|
||||
WALLY-stvec-01 \
|
||||
WALLY-MIE-01 \
|
||||
WALLY-PIE-stack-01 \
|
||||
WALLY-PIE-stack-s-01 \
|
||||
WALLY-trap-sret-01 \
|
||||
WALLY-trap-01 \
|
||||
WALLY-trap-s-01 \
|
||||
WALLY-trap-u-01 \
|
||||
|
||||
rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests))
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,10 +1,6 @@
|
||||
beef00b5
|
||||
00000007 # write access fault with 16 bit write to CLINT
|
||||
00000005 # read access fault with 16 bit write to CLINT
|
||||
00000bad
|
||||
00000007 # write access fault with 8 bit write to CLINT
|
||||
00000005 # read access fault with 8 bit write to CLINT
|
||||
00000bad
|
||||
beef00b5
|
||||
000000b6
|
||||
ffffffb7
|
||||
00000001
|
||||
00000bad
|
||||
00000002
|
||||
|
||||
@ -1,11 +1,10 @@
|
||||
000000
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
00000aaa # Test 5.3.1.5: readback value of SIE after enabling all interrupts.
|
||||
80000007 # mcause from m time interrupt
|
||||
00000000 # mtval for mtime interrupt (0x0)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
0000000b # mcause from M mode ecall from test termination
|
||||
00000000 # mtval of ecall (*** defined to be zero for now)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
00000111 # Test 5.3.2.3: successful read the 0x111 written to mscratch
|
||||
00000000
|
||||
0000000b # ecall from ending tests in machine mode
|
||||
deadbeef
|
||||
deadbeef
|
||||
00000000
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
|
||||
@ -1,11 +1,11 @@
|
||||
00000111 # Test 5.3.2.3: successful read of the 0x111 written to sscratch
|
||||
00000000
|
||||
0000000b # ecall from going to s mode from m mode
|
||||
00000000
|
||||
00000aaa # successful read of 0xAAA written to sscratch
|
||||
00000000
|
||||
00000009 # ecall from ending tests in supervisor mode
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
00000000
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
|
||||
@ -1,23 +1,23 @@
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
00000aaa # Test 5.3.1.5: readback value of MIE after enabling all interrupts.
|
||||
00000222 # readback value of mideleg after attempting to delegate all interrupts.
|
||||
0000000b # mcause from ecall for going from M mode to S mode
|
||||
00000000 # mtval of ecall (*** defined to be zero for now)
|
||||
00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
80000001 # mcause from s soft interrupt
|
||||
00000000 # mtval for ssoft interrupt (0x0)
|
||||
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000009 # mcause from ecall for going from S mode to M mode
|
||||
00000000 # mtval of ecall (*** defined to be zero for now)
|
||||
00000800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
0000000b # mcause from ecall for going from M mode to U mode
|
||||
00000000 # mtval of ecall (*** defined to be zero for now)
|
||||
00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
80000001 # mcause from s soft interrupt from user mode this time
|
||||
00000000 # mtval for mtime interrupt (0x0)
|
||||
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000008 # mcause from U mode ecall from test termination
|
||||
00000000 # mtval of ecall (*** defined to be zero for now)
|
||||
00000000 # masked out mstatus.MPP = 00, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
|
||||
@ -1,4 +1,7 @@
|
||||
00000aaa # Test 5.3.1.4: readback value from writing mie to enable interrupts
|
||||
00000aaa # Test 5.3.1.4: readback value from writing mie to enable interrupts
|
||||
00000000 # mcause from instruction addr misaligned fault
|
||||
8000013a # mtval of faulting instruction adress
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000001 # mcause from an instruction access fault
|
||||
00000000 # mtval of faulting instruction address (0x0)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
@ -6,21 +9,21 @@
|
||||
00000000 # mtval of faulting instruction (0x0)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000003 # mcause from Breakpoint
|
||||
800003ec # mtval of breakpoint instruction adress (0x800003ec)
|
||||
8000016c # mtval of breakpoint instruction adress
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000004 # mcause from load address misaligned
|
||||
800003f5 # mtval of misaligned address (0x800003f5)
|
||||
80000175 # mtval of misaligned address
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000005 # mcause from load access
|
||||
00000000 # mtval of accessed adress (0x0)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000006 # mcause from store misaligned
|
||||
80000411 # mtval of address with misaligned store instr (0x80000410)
|
||||
80000191 # mtval of address with misaligned store instr
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000007 # mcause from store access
|
||||
00000000 # mtval of accessed address (0x0)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
0000000b # mcause from M mode ecall
|
||||
0000000b # mcause from M mode ecall
|
||||
00000000 # mtval of ecall (*** defined to be zero for now)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000008 # mcause from U mode ecall
|
||||
@ -29,54 +32,69 @@
|
||||
00000009 # mcause from S mode ecall
|
||||
00000000 # mtval of ecall (*** defined to be zero for now)
|
||||
00000880 # masked out mstatus.MPP = 01 (from S mode), mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
000007ec # value to indicate a vectored interrupts
|
||||
0007ec01 # value to indicate successful vectoring on s soft interrupt
|
||||
80000001 # mcause value from s soft interrupt
|
||||
00000000 # mtval for ssoft interrupt (0x0)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
0007ec03 # value to indicate successful vectoring on m soft interrupt
|
||||
80000003 # mcause value from m soft interrupt
|
||||
00000000 # mtval for msoft interrupt (0x0)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
0007ec05 # value to indicate successful vectoring on s time interrupt
|
||||
80000005 # mcause value from s time interrupt
|
||||
00000000 # mtval for stime interrupt (0x0)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
0007ec07 # value to indicate successful vectoring on m time interrupt
|
||||
80000007 # mcause value from m time interrupt
|
||||
00000000 # mtval for mtime interrupt (0x0)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
000007ec # value to indicate a vectored interrupts
|
||||
80000001 # mcause value from m soft interrupt
|
||||
00000000 # mtval for msoft interrupt (0x0)
|
||||
0007ec09 # value to indicate successful vectoring on s ext interrupt
|
||||
80000009 # mcause value from s ext interrupt
|
||||
00000000 # mtval for sext interrupt (0x0)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
000007ec # value to indicate a vectored interrupts
|
||||
0007ec0b # value to indicate successful vectoring on m ext interrupt
|
||||
8000000b # mcause value from m ext interrupt
|
||||
00000000 # mtval for mext interrupt (0x0)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
0000b309 # medeleg after attempted write of all 1's (only some bits are writeable)
|
||||
fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable)
|
||||
00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
|
||||
00000001 # Test 5.3.1.4: mcause from an instruction access fault
|
||||
00000000 # mcause from instruction addr misaligned fault
|
||||
8000013a # mtval of faulting instruction adress
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000001 # mcause from an instruction access fault
|
||||
00000000 # mtval of faulting instruction address (0x0)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000002 # mcause from an Illegal instruction
|
||||
00000000 # mtval of faulting instruction (0x0)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000003 # mcause from Breakpoint
|
||||
800003ec # mtval of breakpoint instruction adress (0x800003ec)
|
||||
8000016c # mtval of breakpoint instruction adress
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000004 # mcause from load address misaligned
|
||||
800003f5 # mtval of misaligned address (0x800003f5)
|
||||
80000175 # mtval of misaligned address
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000005 # mcause from load access
|
||||
00000000 # mtval of accessed adress (0x0)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000006 # mcause from store misaligned
|
||||
80000411 # mtval of address with misaligned store instr (0x80000410)
|
||||
80000191 # mtval of address with misaligned store instr
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000007 # mcause from store access
|
||||
00000000 # mtval of accessed address (0x0)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
0000000b # mcause from M mode ecall
|
||||
0000000b # mcause from M mode ecall
|
||||
00000000 # mtval of ecall (*** defined to be zero for now)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
000007ec # value to indicate a vectored interrupts
|
||||
80000007 # mcause value from time interrupt
|
||||
00000000 # mtval for mtime interrupt (0x0)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
000007ec # value to indicate a vectored interrupts
|
||||
80000001 # mcause value from m soft interrupt
|
||||
0007ec03 # value to indicate successful vectoring on m soft interrupt
|
||||
80000003 # mcause value from m soft interrupt
|
||||
00000000 # mtval for msoft interrupt (0x0)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
000007ec # value to indicate a vectored interrupts
|
||||
0000000b # mcause value from m ext interrupt
|
||||
0007ec07 # value to indicate successful vectoring on m time interrupt
|
||||
80000007 # mcause value from m time interrupt
|
||||
00000000 # mtval for mtime interrupt (0x0)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
0007ec0b # value to indicate successful vectoring on m ext interrupt
|
||||
8000000b # mcause value from m ext interrupt
|
||||
00000000 # mtval for mext interrupt (0x0)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
0000000b # mcause from M mode ecall from test termination
|
||||
@ -988,3 +1006,19 @@ deadbeef
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
|
||||
@ -1,106 +1,106 @@
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
00000aaa # readback value from writing mie to enable interrupts
|
||||
0000000b # Test 5.3.1.4: mcause from ecall going from M mode to S mode
|
||||
00000000 # mtval of ecall (*** defined to be zero for now)
|
||||
00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000000 # scause from instruction addr misaligned fault
|
||||
8000013a # stval of faulting instruction adress
|
||||
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000001 # scause from an instruction access fault
|
||||
00000000 # stval of faulting instruction address (0x0)
|
||||
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000002 # scause from an Illegal instruction
|
||||
00000000 # stval of faulting instruction (0x0)
|
||||
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000003 # scause from Breakpoint
|
||||
8000016c # stval of breakpoint instruction adress
|
||||
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000004 # scause from load address misaligned
|
||||
80000175 # stval of misaligned address
|
||||
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000005 # scause from load access
|
||||
00000000 # stval of accessed adress (0x0)
|
||||
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000006 # scause from store misaligned
|
||||
80000191 # stval of address with misaligned store instr
|
||||
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000007 # scause from store access
|
||||
00000000 # stval of accessed address (0x0)
|
||||
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000009 # scause from S mode ecall
|
||||
00000000 # stval of ecall (*** defined to be zero for now)
|
||||
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000008 # scause from U mode ecall
|
||||
00000000 # stval of ecall (*** defined to be zero for now)
|
||||
00000000 # masked out mstatus.mpp = 0 (from U mode), mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
0007ec01 # value to indicate successful vectoring on s soft interrupt
|
||||
80000001 # scause value from s soft interrupt
|
||||
00000000 # stval for ssoft interrupt (0x0)
|
||||
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
0007ec03 # value to indicate successful vectoring on m soft interrupt
|
||||
80000003 # scause value from m soft interrupt
|
||||
00000000 # stval for msoft interrupt (0x0)
|
||||
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
0007ec07 # value to indicate successful vectoring on m time interrupt
|
||||
80000007 # scause value from m time interrupt
|
||||
00000000 # stval for mtime interrupt (0x0)
|
||||
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
0007ec09 # value to indicate successful vectoring on s ext interrupt
|
||||
80000009 # scause value from s ext interrupt
|
||||
00000000 # stval for sext interrupt (0x0)
|
||||
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
0007ec0b # value to indicate successful vectoring on m ext interrupt
|
||||
8000000b # scause value from m ext interrupt
|
||||
00000000 # stval for mext interrupt (0x0)
|
||||
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000009 # scause from S mode ecall
|
||||
00000000 # stval of ecall (*** defined to be zero for now)
|
||||
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable)
|
||||
00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
|
||||
0000000b # scause from M mode ecall
|
||||
00000000 # stval of ecall (*** defined to be zero for now)
|
||||
00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000000 # scause from instruction addr misaligned fault
|
||||
8000013a # stval of faulting instruction adress
|
||||
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000001 # scause from an instruction access fault
|
||||
00000000 # stval of faulting instruction address (0x0)
|
||||
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000002 # scause from an Illegal instruction
|
||||
00000000 # stval of faulting instruction (0x0)
|
||||
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000003 # scause from Breakpoint
|
||||
8000016c # stval of breakpoint instruction adress
|
||||
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000004 # scause from load address misaligned
|
||||
80000175 # stval of misaligned address
|
||||
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000005 # scause from load access
|
||||
00000000 # stval of accessed adress (0x0)
|
||||
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000006 # scause from store misaligned
|
||||
80000191 # stval of address with misaligned store instr
|
||||
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000007 # scause from store access
|
||||
00000000 # stval of accessed address (0x0)
|
||||
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000009 # scause from S mode ecall
|
||||
00000000 # stval of ecall (*** defined to be zero for now)
|
||||
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000008 # scause from U mode ecall
|
||||
00000000 # stval of ecall (*** defined to be zero for now)
|
||||
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
0007ec01 # value to indicate successful vectoring on s soft interrupt
|
||||
80000001 # scause value from s soft interrupt
|
||||
00000000 # stval for ssoft interrupt (0x0)
|
||||
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
0007ec09 # value to indicate successful vectoring on s ext interrupt
|
||||
80000009 # scause value from s ext interrupt
|
||||
00000000 # stval for sext interrupt (0x0)
|
||||
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000009 # scause from S mode ecall from test termination
|
||||
00000000 # stval of ecall (*** defined to be zero for now)
|
||||
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,92 +1,92 @@
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
00000aaa # readback value from writing mie to enable interrupts
|
||||
0000000b # Test 5.3.1.4: mcause from ecall going from M mode to U mode
|
||||
00000000 # mtval of ecall (*** defined to be zero for now)
|
||||
00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000000 # scause from instruction addr misaligned fault
|
||||
8000013a # stval of faulting instruction adress
|
||||
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000001 # scause from an instruction access fault
|
||||
00000000 # stval of faulting instruction address (0x0)
|
||||
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000002 # scause from an Illegal instruction
|
||||
00000000 # stval of faulting instruction (0x0)
|
||||
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000003 # scause from Breakpoint
|
||||
8000016c # stval of breakpoint instruction adress
|
||||
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000004 # scause from load address misaligned
|
||||
80000175 # stval of misaligned address
|
||||
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000005 # scause from load access
|
||||
00000000 # stval of accessed adress (0x0)
|
||||
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000006 # scause from store misaligned
|
||||
80000191 # stval of address with misaligned store instr
|
||||
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000007 # scause from store access
|
||||
00000000 # stval of accessed address (0x0)
|
||||
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000008 # scause from U mode ecall
|
||||
00000000 # stval of ecall (*** defined to be zero for now)
|
||||
00000000 # masked out mstatus.mpp = 0 (from U mode), mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
0007ec03 # value to indicate successful vectoring on m soft interrupt
|
||||
80000003 # scause value from m soft interrupt
|
||||
00000000 # stval for msoft interrupt (0x0)
|
||||
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
0007ec07 # value to indicate successful vectoring on m time interrupt
|
||||
80000007 # scause value from m time interrupt
|
||||
00000000 # stval for mtime interrupt (0x0)
|
||||
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
0007ec09 # value to indicate successful vectoring on s ext interrupt
|
||||
80000009 # scause value from s ext interrupt
|
||||
00000000 # stval for sext interrupt (0x0)
|
||||
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
0007ec0b # value to indicate successful vectoring on m ext interrupt
|
||||
8000000b # scause value from m ext interrupt
|
||||
00000000 # stval for mext interrupt (0x0)
|
||||
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000008 # scause from U mode ecall
|
||||
00000000 # stval of ecall (*** defined to be zero for now)
|
||||
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable)
|
||||
00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
|
||||
0000000b # scause from M mode ecall
|
||||
00000000 # stval of ecall (*** defined to be zero for now)
|
||||
00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000000 # scause from instruction addr misaligned fault
|
||||
8000013a # stval of faulting instruction adress
|
||||
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000001 # scause from an instruction access fault
|
||||
00000000 # stval of faulting instruction address (0x0)
|
||||
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000002 # scause from an Illegal instruction
|
||||
00000000 # stval of faulting instruction (0x0)
|
||||
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000003 # scause from Breakpoint
|
||||
8000016c # stval of breakpoint instruction adress
|
||||
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000004 # scause from load address misaligned
|
||||
80000175 # stval of misaligned address
|
||||
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000005 # scause from load access
|
||||
00000000 # stval of accessed adress (0x0)
|
||||
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000006 # scause from store misaligned
|
||||
80000191 # stval of address with misaligned store instr
|
||||
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000007 # scause from store access
|
||||
00000000 # stval of accessed address (0x0)
|
||||
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000008 # scause from U mode ecall
|
||||
00000000 # stval of ecall (*** defined to be zero for now)
|
||||
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
0007ec09 # value to indicate successful vectoring on s ext interrupt
|
||||
80000009 # scause value from s ext interrupt
|
||||
00000000 # stval for sext interrupt (0x0)
|
||||
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000008 # scause from U mode ecall from test termination
|
||||
00000000 # stval of ecall (*** defined to be zero for now)
|
||||
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
|
||||
@ -0,0 +1,53 @@
|
||||
///////////////////////////////////////////
|
||||
//
|
||||
// WALLY-MIE
|
||||
//
|
||||
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
|
||||
//
|
||||
// Created 2022-04-10
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
#include "WALLY-TEST-LIB-32.h"
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
|
||||
|
||||
TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps
|
||||
|
||||
li x28, 0x8
|
||||
csrs mstatus, x28 // set mstatus.MIE bit to 1.
|
||||
WRITE_READ_CSR mie, 0x0 // force zeroing out mie CSR.
|
||||
|
||||
// test 5.3.1.6 Interrupt enabling and priority tests
|
||||
// testing with MIE bits set already tested in WALLY-trap
|
||||
// note that none of these interrupts should be caught or handled.
|
||||
|
||||
jal cause_s_soft_interrupt
|
||||
jal cause_m_soft_interrupt
|
||||
jal cause_s_time_interrupt
|
||||
jal cause_m_time_interrupt
|
||||
li a3, 0x40 // these interrupts involve a time loop waiting for the interrupt to go off.
|
||||
// since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3
|
||||
jal cause_s_ext_interrupt_GPIO
|
||||
li a3, 0x40
|
||||
jal cause_m_ext_interrupt
|
||||
|
||||
END_TESTS
|
||||
|
||||
TEST_STACK_AND_DATA
|
||||
|
||||
@ -0,0 +1,49 @@
|
||||
///////////////////////////////////////////
|
||||
//
|
||||
// WALLY-privilege-interrupt-enable-stack
|
||||
//
|
||||
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
|
||||
//
|
||||
// Created 2022-04-10
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
#include "WALLY-TEST-LIB-32.h"
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
|
||||
|
||||
TRAP_HANDLER m, DEBUG=1
|
||||
|
||||
li x28, 0x8
|
||||
csrs mstatus, x28 // set mstatus.MIE bit to 1
|
||||
WRITE_READ_CSR mie, 0xFFF
|
||||
|
||||
// test 5.3.1.6 Interrupt enabling and priority tests
|
||||
|
||||
// Cause interrupt, ensuring that status.mie = 0 , status.mpie = 1, and status.mpp = 11 during trap handling
|
||||
jal cause_m_soft_interrupt // *** only cause one interrupt because we just want to test the status stack
|
||||
|
||||
li x28, 0x8
|
||||
csrc mstatus, x28 // set mstatus.MIE bit to 0. interrupts from M mode should not happen
|
||||
|
||||
// attempt to cause interrupt, it should not go through
|
||||
jal cause_m_soft_interrupt
|
||||
|
||||
END_TESTS
|
||||
|
||||
TEST_STACK_AND_DATA
|
||||
@ -0,0 +1,53 @@
|
||||
///////////////////////////////////////////
|
||||
//
|
||||
// WALLY-privilege-interrupt-enable-stack
|
||||
//
|
||||
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
|
||||
//
|
||||
// Created 2022-04-10
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
#include "WALLY-TEST-LIB-32.h"
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
|
||||
|
||||
TRAP_HANDLER m, DEBUG=1 // necessary so we can go to S mode
|
||||
TRAP_HANDLER s, DEBUG=1 // neccessary to handle s mode interrupts.
|
||||
|
||||
li x28, 0x2
|
||||
csrs sstatus, x28 // set sstatus.SIE bit to 1
|
||||
WRITE_READ_CSR mie, 0xFFF // enable all interrupts, including supervisor ones
|
||||
WRITE_READ_CSR mideleg 0xFFFF // delegate all interrupts to S mode.
|
||||
|
||||
// test 5.3.1.6 Interrupt enabling and priority tests
|
||||
|
||||
GOTO_S_MODE
|
||||
|
||||
// Cause interrupt, ensuring that status.sie = 0 , status.spie = 1, and status.spp = 1 during trap handling
|
||||
jal cause_s_soft_interrupt // *** only cause one interrupt because we just want to test the status stack
|
||||
|
||||
li x28, 0x2
|
||||
csrc sstatus, x28 // set sstatus.SIE bit to 0. interrupts from S mode should not happen
|
||||
|
||||
// attempt to cause interrupt, it should not go through
|
||||
jal cause_s_soft_interrupt
|
||||
|
||||
END_TESTS
|
||||
|
||||
TEST_STACK_AND_DATA
|
||||
@ -81,14 +81,14 @@ test_cases:
|
||||
# ----------------- CLINT ---------------------
|
||||
|
||||
# Use timecmp register as readable and writable section of the CLINT
|
||||
.4byte CLINT_BASE + 0x4000, 0xBEEF00B5, write32_test # 32-bit write: success
|
||||
.4byte CLINT_BASE + 0x4000, 0xBEEF00B5, read32_test # 32-bit read: success
|
||||
.4byte CLINT_BASE + 0x4000, 0xBEEF00B6, write16_test# 16-bit write: failure *** Due to non-native access length in CLINT
|
||||
.4byte CLINT_BASE + 0x4000, 0xBEEF00B6, read16_test# 16-bit read: failure
|
||||
.4byte CLINT_BASE + 0x4000, 0xBEEF00B7, write08_test# 08-bit write: failure
|
||||
.4byte CLINT_BASE + 0x4000, 0xBEEF00B7, read08_test# 08-bit read: failure
|
||||
.4byte CLINT_BASE + 0x4000, 0xBEEF00B5, write32_test # 32-bit write: success
|
||||
.4byte CLINT_BASE + 0x4000, 0xBEEF00B5, read32_test # 32-bit read: success
|
||||
.4byte CLINT_BASE + 0x4000, 0xBEEF00B6, write16_test # 16-bit write: success
|
||||
.4byte CLINT_BASE + 0x4000, 0xBEEF00B6, read16_test # 16-bit read: success
|
||||
.4byte CLINT_BASE + 0x4000, 0xBEEF00B7, write08_test # 08-bit write: success
|
||||
.4byte CLINT_BASE + 0x4000, 0xBEEF00B7, read08_test # 08-bit read: success
|
||||
|
||||
.4byte CLINT_BASE, 0xbad, executable_test# execute: instruction access fault
|
||||
.4byte CLINT_BASE, 0xbad, executable_test # execute: instruction access fault
|
||||
|
||||
# ----------------- PLIC ---------------------
|
||||
|
||||
|
||||
@ -39,8 +39,7 @@ RVTEST_CODE_BEGIN
|
||||
//
|
||||
// Initialize x6 as a virtual pointer to the test results
|
||||
// Initialize x16 as a physical pointer to the test results
|
||||
// Set up stack pointer (sp = x2)
|
||||
// Set up the exception Handler, keeping the original handler in x4.
|
||||
// Set up stack pointer, mscratch, sscratch
|
||||
//
|
||||
// ---------------------------------------------------------------------------------------------
|
||||
|
||||
@ -49,8 +48,12 @@ RVTEST_CODE_BEGIN
|
||||
la x16, test_1_res // x16 reserved for the physical address equivalent of x6 to be used in trap handlers
|
||||
// any time either is used, both must be updated.
|
||||
|
||||
// address for stack
|
||||
la sp, top_of_stack
|
||||
// address for normal user stack, mscratch stack, and sscratch stack
|
||||
la sp, mscratch_top
|
||||
csrw mscratch, sp
|
||||
la sp, sscratch_top
|
||||
csrw sscratch, sp
|
||||
la sp, stack_top
|
||||
|
||||
.endm
|
||||
|
||||
@ -61,11 +64,13 @@ j end_trap_triggers
|
||||
|
||||
// The following tests involve causing many of the interrupts and exceptions that are easily done in a few lines
|
||||
// This effectively includes everything that isn't to do with page faults (virtual memory)
|
||||
|
||||
//
|
||||
// INPUTS: a3 (x13): the number of times one of the infinitely looping interrupt causes should loop before giving up and continuing without the interrupt firing.
|
||||
//
|
||||
cause_instr_addr_misaligned:
|
||||
// cause a misaligned address trap
|
||||
auipc x28, 0 // get current PC, which is aligned
|
||||
addi x28, x28, 0x3 // add 1 to pc to create misaligned address
|
||||
addi x28, x28, 0x2 // add 2 to pc to create misaligned address (Assumes compressed instructions are disabled)
|
||||
jr x28 // cause instruction address midaligned trap
|
||||
ret
|
||||
|
||||
@ -79,10 +84,10 @@ cause_instr_access:
|
||||
ret
|
||||
|
||||
cause_illegal_instr:
|
||||
.word 0x00000000 // a 32 bit zros is an illegal instruction
|
||||
.word 0x00000000 // 32 bit zero is an illegal instruction
|
||||
ret
|
||||
|
||||
cause_breakpnt: // ****
|
||||
cause_breakpnt:
|
||||
ebreak
|
||||
ret
|
||||
|
||||
@ -113,10 +118,11 @@ cause_ecall:
|
||||
ecall
|
||||
ret
|
||||
|
||||
cause_time_interrupt:
|
||||
cause_m_time_interrupt:
|
||||
// The following code works for both RV32 and RV64.
|
||||
// RV64 alone would be easier using double-word adds and stores
|
||||
li x28, 0x30 // Desired offset from the present time
|
||||
mv a3, x28 // copy value in to know to stop waiting for interrupt after this many cycles
|
||||
la x29, 0x02004000 // MTIMECMP register in CLINT
|
||||
la x30, 0x0200BFF8 // MTIME register in CLINT
|
||||
lw x7, 0(x30) // low word of MTIME
|
||||
@ -127,21 +133,101 @@ cause_time_interrupt:
|
||||
sw x31,4(x29) // store into most significant word of MTIMECMP
|
||||
nowrap:
|
||||
sw x28, 0(x29) // store into least significant word of MTIMECMP
|
||||
loop: j loop // wait until interrupt occurs
|
||||
time_loop:
|
||||
//wfi // *** this may now spin us forever in the loop???
|
||||
addi a3, a3, -1
|
||||
bnez a3, time_loop // go through this loop for [a3 value] iterations before returning without performing interrupt
|
||||
ret
|
||||
|
||||
cause_soft_interrupt:
|
||||
cause_s_time_interrupt:
|
||||
li x28, 0x20
|
||||
csrs mip, x28 // set supervisor time interrupt pending. SIP is a subset of MIP, so writing this should also change MIP.
|
||||
nop // added extra nops in so the csrs can get through the pipeline before returning.
|
||||
ret
|
||||
|
||||
cause_m_soft_interrupt:
|
||||
la x28, 0x02000000 // MSIP register in CLINT
|
||||
li x29, 1 // 1 in the lsb
|
||||
sw x29, 0(x28) // Write MSIP bit
|
||||
ret
|
||||
|
||||
cause_ext_interrupt:
|
||||
cause_s_soft_interrupt:
|
||||
li x28, 0x2
|
||||
csrs sip, x28 // set supervisor software interrupt pending. SIP is a subset of MIP, so writing this should also change MIP.
|
||||
ret
|
||||
|
||||
cause_m_ext_interrupt:
|
||||
# ========== Configure PLIC ==========
|
||||
# m priority threshold = 0
|
||||
li x28, 0xC200000
|
||||
li x29, 0
|
||||
sw x29, 0(x28)
|
||||
# s priority threshold = 7
|
||||
li x28, 0xC201000
|
||||
li x29, 7
|
||||
sw x29, 0(x28)
|
||||
# source 3 (GPIO) priority = 1
|
||||
li x28, 0xC000000
|
||||
li x29, 1
|
||||
sw x29, 0x0C(x28)
|
||||
# enable source 3 in M Mode
|
||||
li x28, 0x0C002000
|
||||
li x29, 0b1000
|
||||
sw x29, 0(x28)
|
||||
|
||||
li x28, 0x10060000 // load base GPIO memory location
|
||||
li x29, 0x1
|
||||
sw x29, 8(x28) // enable the first pin as an output
|
||||
sw x29, 28(x28) // set first pin to high interrupt enable
|
||||
sw x29, 40(x28) // write a 1 to the first output pin (cause interrupt)
|
||||
sw x29, 0x08(x28) // enable the first pin as an output
|
||||
sw x29, 0x04(x28) // enable the first pin as an input as well to cause the interrupt to fire
|
||||
|
||||
sw x0, 0x1C(x28) // clear rise_ip
|
||||
sw x0, 0x24(x28) // clear fall_ip
|
||||
sw x0, 0x2C(x28) // clear high_ip
|
||||
sw x0, 0x34(x28) // clear low_ip
|
||||
|
||||
sw x29, 0x28(x28) // set first pin to interrupt on a rising value
|
||||
sw x29, 0x0C(x28) // write a 1 to the first output pin (cause interrupt)
|
||||
m_ext_loop:
|
||||
//wfi
|
||||
addi a3, a3, -1
|
||||
bnez a3, m_ext_loop // go through this loop for [a3 value] iterations before returning without performing interrupt
|
||||
ret
|
||||
|
||||
cause_s_ext_interrupt_GPIO:
|
||||
# ========== Configure PLIC ==========
|
||||
# s priority threshold = 0
|
||||
li x28, 0xC201000
|
||||
li x29, 0
|
||||
sw x29, 0(x28)
|
||||
# m priority threshold = 7
|
||||
li x28, 0xC200000
|
||||
li x29, 7
|
||||
sw x29, 0(x28)
|
||||
# source 3 (GPIO) priority = 1
|
||||
li x28, 0xC000000
|
||||
li x29, 1
|
||||
sw x29, 0x0C(x28)
|
||||
# enable source 3 in S mode
|
||||
li x28, 0x0C002080
|
||||
li x29, 0b1000
|
||||
sw x29, 0(x28)
|
||||
|
||||
li x28, 0x10060000 // load base GPIO memory location
|
||||
li x29, 0x1
|
||||
sw x29, 0x08(x28) // enable the first pin as an output
|
||||
sw x29, 0x04(x28) // enable the first pin as an input as well to cause the interrupt to fire
|
||||
|
||||
sw x0, 0x1C(x28) // clear rise_ip
|
||||
sw x0, 0x24(x28) // clear fall_ip
|
||||
sw x0, 0x2C(x28) // clear high_ip
|
||||
sw x0, 0x34(x28) // clear low_ip
|
||||
|
||||
sw x29, 0x28(x28) // set first pin to interrupt on a rising value
|
||||
sw x29, 0x0C(x28) // write a 1 to the first output pin (cause interrupt)
|
||||
s_ext_loop:
|
||||
//wfi
|
||||
addi a3, a3, -1
|
||||
bnez a3, s_ext_loop // go through this loop for [a3 value] iterations before returning without performing interrupt
|
||||
ret
|
||||
|
||||
end_trap_triggers:
|
||||
@ -149,7 +235,7 @@ end_trap_triggers:
|
||||
|
||||
.macro TRAP_HANDLER MODE, VECTORED=1, DEBUG=0
|
||||
// MODE decides which mode this trap handler will be taken in (M or S mode)
|
||||
// Vectored decides whether interrumpts are handled with the vector table at trap_handler_MODE (1)
|
||||
// Vectored decides whether interrupts are handled with the vector table at trap_handler_MODE (1)
|
||||
// vs Using the non-vector approach the rest of the trap handler takes (0)
|
||||
// DEBUG decides whether we will print mtval a string with status.mpie, status.mie, and status.mpp to the signature (1)
|
||||
// vs not saving that info to the signature (0)
|
||||
@ -214,24 +300,28 @@ trap_handler_\MODE\():
|
||||
// *** ASSUMES that a cause value of 0 for an interrupt is unimplemented
|
||||
// otherwise, a vectored interrupt handler should jump to trap_handler_\MODE\() + 4 * Interrupt cause code
|
||||
// No matter the value of VECTORED, exceptions (not interrupts) are handled in an unvecotred way
|
||||
j soft_interrupt_\MODE\() // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table.
|
||||
j s_soft_vector_\MODE\() // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table.
|
||||
j segfault_\MODE\() // 2: reserved
|
||||
j soft_interrupt_\MODE\() // 3: breakpoint
|
||||
j m_soft_vector_\MODE\() // 3: breakpoint
|
||||
j segfault_\MODE\() // 4: reserved
|
||||
j time_interrupt_\MODE\() // 5: load access fault
|
||||
j s_time_vector_\MODE\() // 5: load access fault
|
||||
j segfault_\MODE\() // 6: reserved
|
||||
j time_interrupt_\MODE\() // 7: store access fault
|
||||
j m_time_vector_\MODE\() // 7: store access fault
|
||||
j segfault_\MODE\() // 8: reserved
|
||||
j ext_interrupt_\MODE\() // 9: ecall from S-mode
|
||||
j s_ext_vector_\MODE\() // 9: ecall from S-mode
|
||||
j segfault_\MODE\() // 10: reserved
|
||||
j ext_interrupt_\MODE\() // 11: ecall from M-mode
|
||||
j m_ext_vector_\MODE\() // 11: ecall from M-mode
|
||||
// 12 through >=16 are reserved or designated for platform use
|
||||
|
||||
trap_unvectored_\MODE\():
|
||||
// The processor is always in machine mode when a trap takes us here
|
||||
csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
|
||||
// *** NOTE: this means that nested traps will be screwed up but they shouldn't happen in any of these tests
|
||||
|
||||
trap_stack_saved_\MODE\(): // jump here after handling vectored interupt since we already switch sp and scratch there
|
||||
// save registers on stack before using
|
||||
sw x1, -4(sp)
|
||||
sw x5, -8(sp)
|
||||
sw x5, -8(sp)
|
||||
sw x7, -12(sp)
|
||||
|
||||
// Record trap
|
||||
csrr x1, \MODE\()cause // record the mcause
|
||||
@ -261,49 +351,36 @@ trap_unvectored_\MODE\():
|
||||
// Respond to trap based on cause
|
||||
// All interrupts should return after being logged
|
||||
csrr x1, \MODE\()cause
|
||||
li x5, 0x8000000000000000 // if msb is set, it is an interrupt
|
||||
li x5, 0x80000000 // if msb is set, it is an interrupt
|
||||
and x5, x5, x1
|
||||
bnez x5, trapreturn_\MODE\() // return from interrupt
|
||||
bnez x5, interrupt_handler_\MODE\()
|
||||
// Other trap handling is specified in the vector Table
|
||||
slli x1, x1, 2 // multiply cause by 4 to get offset in vector Table
|
||||
la x5, exception_vector_table_\MODE\()
|
||||
slli x1, x1, 2 // multiply cause by 4 to get offset in vector Table
|
||||
add x5, x5, x1 // compute address of vector in Table
|
||||
lw x5, 0(x5) // fectch address of handler from vector Table
|
||||
jr x5 // and jump to the handler
|
||||
|
||||
|
||||
interrupt_handler_\MODE\():
|
||||
la x5, interrupt_vector_table_\MODE\() // NOTE THIS IS NOT THE SAME AS VECTORED INTERRUPTS!!!
|
||||
slli x1, x1, 2 // multiply cause by 4 to get offset in vector Table
|
||||
add x5, x5, x1 // compute address of vector in Table
|
||||
lw x5, 0(x5) // fectch address of handler from vector Table
|
||||
jr x5 // and jump to the handler
|
||||
|
||||
segfault_\MODE\():
|
||||
lw x5, -8(sp) // restore registers from stack before faulting
|
||||
lw x7, -12(sp) // restore registers from stack before faulting
|
||||
lw x5, -8(sp)
|
||||
lw x1, -4(sp)
|
||||
j terminate_test // halt program.
|
||||
|
||||
trapreturn_\MODE\():
|
||||
// look at the instruction to figure out whether to add 2 or 4 bytes to PC, or go to address specified in a1
|
||||
csrr x1, \MODE\()epc // get the mepc
|
||||
addi x1, x1, 4 // *** should be 2 for compressed instructions, see note.
|
||||
|
||||
|
||||
// ****** KMG: the following is no longer as easy to determine. mepc gets the virtual address of the trapped instruction,
|
||||
// ******** but in the handler, we work in M mode with physical addresses
|
||||
// This means the address in mepc is suddenly pointing somewhere else.
|
||||
// to get this to work, We could either retranslate the vaddr back into a paddr (probably on the scale of difficult to intractible)
|
||||
// or we could come up with some other ingenious way to stay in M mode and see if the instruction was compressed.
|
||||
|
||||
// lw x5, 0(x1) // read the faulting instruction
|
||||
// li x1, 3 // check bottom 2 bits of instruction to see if compressed
|
||||
// and x5, x5, x1 // mask the other bits
|
||||
// beq x5, x1, trapreturn_uncompressed // if 11, the instruction is return_uncompressed
|
||||
|
||||
// trapreturn_compressed:
|
||||
// csrr x1, mepc // get the mepc again
|
||||
// addi x1, x1, 2 // add 2 to find the next instruction
|
||||
// j trapreturn_specified // and return
|
||||
|
||||
// trapreturn_uncompressed:
|
||||
// csrr x1, mepc // get the mepc again
|
||||
// addi x1, x1, 4 // add 4 to find the next instruction
|
||||
addi x1, x1, 4
|
||||
|
||||
trapreturn_specified_\MODE\():
|
||||
// reset the necessary pointers and registers (x1, x5, x6, and the return address going to mepc)
|
||||
// note that we don't need to change x7 since it was a temporary register with no important address in it.
|
||||
// so that when we return to a new virtual address, they're all in the right spot as well.
|
||||
|
||||
beqz a1, trapreturn_finished_\MODE\() // either update values, of go to default return address.
|
||||
@ -333,7 +410,7 @@ trapreturn_specified_\MODE\():
|
||||
and x7, x5, x6 // x7 = offset for x6
|
||||
add x6, x7, a1 // x6 = new address for the result pointer
|
||||
|
||||
// set return address, stored temporarily in x1, to the next instruction, but in the new virtual page.
|
||||
// reset x1, which temporarily holds the return address that will be written to mepc.
|
||||
and x1, x5, x1 // x1 = offset for the return address
|
||||
add x1, x1, a1 // x1 = new return address.
|
||||
|
||||
@ -342,13 +419,16 @@ trapreturn_specified_\MODE\():
|
||||
|
||||
trapreturn_finished_\MODE\():
|
||||
csrw \MODE\()epc, x1 // update the mepc with address of next instruction
|
||||
lw x5, -8(sp) // restore registers from stack before returning
|
||||
lw x7, -12(sp) // restore registers from stack before returning
|
||||
lw x5, -8(sp)
|
||||
lw x1, -4(sp)
|
||||
csrrw sp, \MODE\()scratch, sp // switch sp and scratch stack back to restore the non-trap stack pointer
|
||||
\MODE\()ret // return from trap
|
||||
|
||||
// specific exception handlers
|
||||
|
||||
ecallhandler_\MODE\():
|
||||
// Check input parameter a0. encoding above.
|
||||
// *** ASSUMES: that this trap is being handled in machine mode. in other words, that nothing odd has been written to the medeleg or mideleg csrs.
|
||||
li x5, 2 // case 2: change to machine mode
|
||||
beq a0, x5, ecallhandler_changetomachinemode_\MODE\()
|
||||
li x5, 3 // case 3: change to supervisor mode
|
||||
@ -359,22 +439,23 @@ ecallhandler_\MODE\():
|
||||
j segfault_\MODE\()
|
||||
|
||||
ecallhandler_changetomachinemode_\MODE\():
|
||||
// Force mstatus.MPP (bits 12:11) to 11 to enter machine mode after mret
|
||||
// Force status.MPP (bits 12:11) to 11 to enter machine mode after mret
|
||||
// note that it is impossible to return to M mode after a trap delegated to S mode
|
||||
li x1, 0b1100000000000
|
||||
csrs \MODE\()status, x1
|
||||
j trapreturn_\MODE\()
|
||||
j trapreturn_\MODE\()
|
||||
|
||||
ecallhandler_changetosupervisormode_\MODE\():
|
||||
// Force mstatus.MPP (bits 12:11) to 01 to enter supervisor mode after mret
|
||||
li x1, 0b1100000000000
|
||||
// Force status.MPP (bits 12:11) and status.SPP (bit 8) to 01 to enter supervisor mode after (m/s)ret
|
||||
li x1, 0b1000000000000
|
||||
csrc \MODE\()status, x1
|
||||
li x1, 0b0100000000000
|
||||
li x1, 0b0100100000000
|
||||
csrs \MODE\()status, x1
|
||||
j trapreturn_\MODE\()
|
||||
|
||||
ecallhandler_changetousermode_\MODE\():
|
||||
// Force mstatus.MPP (bits 12:11) to 00 to enter user mode after mret
|
||||
li x1, 0b1100000000000
|
||||
// Force status.MPP (bits 12:11) and status.SPP (bit 8) to 00 to enter user mode after (m/s)ret
|
||||
li x1, 0b1100100000000
|
||||
csrc \MODE\()status, x1
|
||||
j trapreturn_\MODE\()
|
||||
|
||||
@ -390,7 +471,6 @@ illegalinstr_\MODE\():
|
||||
j trapreturn_\MODE\() // return to the code after recording the mcause
|
||||
|
||||
accessfault_\MODE\():
|
||||
// *** What do I have to do here?
|
||||
j trapreturn_\MODE\()
|
||||
|
||||
addr_misaligned_\MODE\():
|
||||
@ -399,34 +479,107 @@ addr_misaligned_\MODE\():
|
||||
breakpt_\MODE\():
|
||||
j trapreturn_\MODE\()
|
||||
|
||||
soft_interrupt_\MODE\():
|
||||
li x5, 0x7EC // write 0x7EC (looks like VEC) to the output before the mcause and extras to indicate that this trap was handled with a vector table.
|
||||
sw x5, 0(x16)
|
||||
// Vectored interrupt handlers: record the fact that the handler went to the correct vector and then continue to handling
|
||||
// note: does not mess up any registers, saves and restores them to the stack instead.
|
||||
|
||||
s_soft_vector_\MODE\():
|
||||
csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
|
||||
sw x5, -4(sp) // put x5 on the scratch stack before messing with it
|
||||
li x5, 0x7EC01 // write 0x7ec01 (for "VEC"tored and 01 for the interrupt code)
|
||||
j vectored_int_end_\MODE\()
|
||||
|
||||
m_soft_vector_\MODE\():
|
||||
csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
|
||||
sw x5, -4(sp) // put x5 on the scratch stack before messing with it
|
||||
li x5, 0x7EC03 // write 0x7ec03 (for "VEC"tored and 03 for the interrupt code)
|
||||
j vectored_int_end_\MODE\()
|
||||
|
||||
s_time_vector_\MODE\():
|
||||
csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
|
||||
sw x5, -4(sp) // put x5 on the scratch stack before messing with it
|
||||
li x5, 0x7EC05 // write 0x7ec05 (for "VEC"tored and 05 for the interrupt code)
|
||||
j vectored_int_end_\MODE\()
|
||||
|
||||
m_time_vector_\MODE\():
|
||||
csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
|
||||
sw x5, -4(sp) // put x5 on the scratch stack before messing with it
|
||||
li x5, 0x7EC07 // write 0x7ec07 (for "VEC"tored and 07 for the interrupt code)
|
||||
j vectored_int_end_\MODE\()
|
||||
|
||||
s_ext_vector_\MODE\():
|
||||
csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
|
||||
sw x5, -4(sp) // put x5 on the scratch stack before messing with it
|
||||
li x5, 0x7EC09 // write 0x7ec09 (for "VEC"tored and 08 for the interrupt code)
|
||||
j vectored_int_end_\MODE\()
|
||||
|
||||
m_ext_vector_\MODE\():
|
||||
csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
|
||||
sw x5, -4(sp) // put x5 on the scratch stack before messing with it
|
||||
li x5, 0x7EC0B // write 0x7ec0B (for "VEC"tored and 0B for the interrupt code)
|
||||
j vectored_int_end_\MODE\()
|
||||
|
||||
vectored_int_end_\MODE\():
|
||||
sw x5, 0(x16) // store to signature to show vectored interrupts succeeded.
|
||||
addi x6, x6, 4
|
||||
addi x16, x16, 4
|
||||
la x28, 0x02000000 // Reset by clearing MSIP interrupt from CLINT
|
||||
sw x0, 0(x28)
|
||||
j trap_unvectored_\MODE\()
|
||||
lw x5, -4(sp) // restore x5 before continuing to handle trap in case its needed.
|
||||
j trap_stack_saved_\MODE\()
|
||||
|
||||
// specific interrupt handlers
|
||||
|
||||
soft_interrupt_\MODE\():
|
||||
la x5, 0x02000000 // Reset by clearing MSIP interrupt from CLINT
|
||||
sw x0, 0(x5)
|
||||
|
||||
csrci \MODE\()ip, 0x2 // clear supervisor software interrupt pending bit
|
||||
lw x1, -4(sp) // load return address from stack into ra (the address to return to after causing this interrupt)
|
||||
// Note: we do this because the mepc loads in the address of the instruction after the sw that causes the interrupt
|
||||
// This means that this trap handler will return to the next address after that one, which might be unpredictable behavior.
|
||||
j trapreturn_finished_\MODE\() // return to the code at ra value from before trap
|
||||
|
||||
time_interrupt_\MODE\():
|
||||
li x5, 0x7EC
|
||||
sw x5, 0(x16)
|
||||
addi x6, x6, 4
|
||||
addi x16, x16, 4
|
||||
la x29, 0x02004000 // MTIMECMP register in CLINT
|
||||
li x30, 0xFFFFFFFF
|
||||
sw x30, 0(x29) // reset interrupt by setting mtimecmp to 0xFFFFFFFF
|
||||
j trap_unvectored_\MODE\()
|
||||
la x5, 0x02004000 // MTIMECMP register in CLINT
|
||||
li x7, 0xFFFFFFFF
|
||||
sw x7, 0(x5) // reset interrupt by setting mtimecmp to 0xFFFFFFFF
|
||||
|
||||
li x5, 0x20
|
||||
csrc \MODE\()ip, x5
|
||||
lw x1, -4(sp) // load return address from stack into ra (the address to return to after the loop is complete)
|
||||
j trapreturn_finished_\MODE\() // return to the code at ra value from before trap
|
||||
|
||||
ext_interrupt_\MODE\():
|
||||
li x5, 0x7EC
|
||||
sw x5, 0(x16)
|
||||
addi x6, x6, 4
|
||||
addi x16, x16, 4
|
||||
li x28, 0x10060000 // reset interrupt by clearing all the GPIO bits
|
||||
sw x0, 8(x28) // disable the first pin as an output
|
||||
sw x0, 40(x28) // write a 0 to the first output pin (reset interrupt)
|
||||
j trap_unvectored_\MODE\()
|
||||
|
||||
# reset PLIC to turn off external interrupts
|
||||
# m priority threshold = 7
|
||||
li x28, 0xC200000
|
||||
li x5, 0x7
|
||||
sw x5, 0(x28)
|
||||
# s priority threshold = 7
|
||||
li x28, 0xC201000
|
||||
li x5, 0x7
|
||||
sw x5, 0(x28)
|
||||
# source 3 (GPIO) priority = 0
|
||||
li x28, 0xC000000
|
||||
li x5, 0
|
||||
sw x5, 0x0C(x28)
|
||||
# disable source 3 in M mode
|
||||
li x28, 0x0C002000
|
||||
li x5, 0b0000
|
||||
sw x5, 0(x28)
|
||||
# enable source 3 in S mode
|
||||
li x28, 0x0C002080
|
||||
li x29, 0b0000
|
||||
sw x29, 0(x28)
|
||||
|
||||
li x5, 0x200
|
||||
csrc \MODE\()ip, x5
|
||||
|
||||
lw x1, -4(sp) // load return address from stack into ra (the address to return to after the loop is complete)
|
||||
j trapreturn_finished_\MODE\() // return to the code at ra value from before trap
|
||||
|
||||
|
||||
// Table of trap behavior
|
||||
// lists what to do on each exception (not interrupts)
|
||||
@ -452,6 +605,22 @@ exception_vector_table_\MODE\():
|
||||
.4byte segfault_\MODE\() // 14: reserved
|
||||
.4byte trapreturn_\MODE\() // 15: store page fault
|
||||
|
||||
.align 2 // aligns this data table to an 4 byte boundary
|
||||
interrupt_vector_table_\MODE\():
|
||||
.4byte segfault_\MODE\() // 0: reserved
|
||||
.4byte soft_interrupt_\MODE\() // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table.
|
||||
.4byte segfault_\MODE\() // 2: reserved
|
||||
.4byte soft_interrupt_\MODE\() // 3: breakpoint
|
||||
.4byte segfault_\MODE\() // 4: reserved
|
||||
.4byte time_interrupt_\MODE\() // 5: load access fault
|
||||
.4byte segfault_\MODE\() // 6: reserved
|
||||
.4byte time_interrupt_\MODE\() // 7: store access fault
|
||||
.4byte segfault_\MODE\() // 8: reserved
|
||||
.4byte ext_interrupt_\MODE\() // 9: ecall from S-mode
|
||||
.4byte segfault_\MODE\() // 10: reserved
|
||||
.4byte ext_interrupt_\MODE\() // 11: ecall from M-mode
|
||||
|
||||
|
||||
.align 2
|
||||
trap_return_pagetype_table_\MODE\():
|
||||
.4byte 0xC // 0: kilopage has 12 offset bits
|
||||
@ -589,7 +758,8 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a
|
||||
// Turn translation off
|
||||
li x7, 0 // satp.MODE value for bare metal (0)
|
||||
slli x7, x7, 31
|
||||
sfence.vma x0, x0 // *** flushes global pte's as well
|
||||
csrw satp, x7
|
||||
//sfence.vma x0, x0 // *** flushes global pte's as well
|
||||
.endm
|
||||
|
||||
.macro GOTO_SV32 ASID BASE_PPN
|
||||
@ -602,7 +772,7 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a
|
||||
li x28, \BASE_PPN // Base Pagetable physical page number, satp.PPN field.
|
||||
add x7, x7, x28
|
||||
csrw satp, x7
|
||||
sfence.vma x0, x0 // *** flushes global pte's as well
|
||||
//sfence.vma x0, x0 // *** flushes global pte's as well
|
||||
.endm
|
||||
|
||||
.macro WRITE_READ_CSR CSR VAL
|
||||
@ -996,9 +1166,19 @@ rvtest_data:
|
||||
RVTEST_DATA_END
|
||||
|
||||
.align 2 // align stack to 4 byte boundary
|
||||
bottom_of_stack:
|
||||
stack_bottom:
|
||||
.fill 1024, 4, 0xdeadbeef
|
||||
top_of_stack:
|
||||
stack_top:
|
||||
|
||||
.align 2
|
||||
mscratch_bottom:
|
||||
.fill 512, 4, 0xdeadbeef
|
||||
mscratch_top:
|
||||
|
||||
.align 2
|
||||
sscratch_bottom:
|
||||
.fill 512, 4, 0xdeadbeef
|
||||
sscratch_top:
|
||||
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
|
||||
@ -21,24 +21,23 @@
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
#include "WALLY-TEST-LIB-64.h"
|
||||
#include "WALLY-TEST-LIB-32.h"
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
|
||||
|
||||
// test 5.3.1.5 Unvectored interrupt tests
|
||||
|
||||
TRAP_HANDLER m, VECTORED=0, DEBUG=1 // turn off vectored interrupts, while turning on recording of mstatus bits.
|
||||
|
||||
li x28, 0x8
|
||||
csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode
|
||||
WRITE_READ_CSR mie, 0xFFF // *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts
|
||||
csrs mstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode
|
||||
WRITE_READ_CSR mie, 0xFFF
|
||||
|
||||
// cause traps, ensuring that we DONT go through the vectored part of the trap handler
|
||||
// *** this assumes that interrupt code 0 remains reserved
|
||||
|
||||
CAUSE_TIME_INTERRUPT // *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
|
||||
CAUSE_SOFT_INTERRUPT // *** exiting out of the trap handler after these is current;y broken
|
||||
CAUSE_EXT_INTERRUPT
|
||||
jal cause_m_time_interrupt // *** only cause one interrupt because we just want to test the status stack
|
||||
|
||||
END_TESTS
|
||||
|
||||
|
||||
@ -26,7 +26,6 @@
|
||||
INIT_TESTS
|
||||
|
||||
TRAP_HANDLER m
|
||||
|
||||
// Test 5.3.2.3: Scratch registers test
|
||||
|
||||
WRITE_READ_CSR mscratch, 0x111 // check that mscratch is readable and writeable in machine mode
|
||||
|
||||
@ -21,34 +21,33 @@
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
#include "WALLY-TEST-LIB-64.h"
|
||||
#include "WALLY-TEST-LIB-32.h"
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
|
||||
|
||||
// test 5.3.1.5 Unvectored interrupt tests
|
||||
|
||||
TRAP_HANDLER m, VECTORED=0, DEBUG=1 // necessary to handle changing modes
|
||||
TRAP_HANDLER s, VECTORED=0, DEBUG=1 // turn off vectored interrupts, while turning on recording of mstatus bits.
|
||||
|
||||
// li x28, 0x8
|
||||
// csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode
|
||||
// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts
|
||||
|
||||
li x28, 0x2
|
||||
csrs sstatus, x28 // set sstatus.SIE bit to 1
|
||||
WRITE_READ_CSR mie, 0xFFFF
|
||||
WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
|
||||
|
||||
// cause traps, ensuring that we DONT go through the vectored part of the trap handler
|
||||
|
||||
GOTO_S_MODE
|
||||
|
||||
// cause traps, ensuring that we DONT go through the vectored part of the trap handler
|
||||
// *** this assumes that interrupt code 0 remains reserved
|
||||
jal cause_s_soft_interrupt // *** only cause one interrupt since we just want to test the tvec csr
|
||||
|
||||
// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
|
||||
// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
|
||||
// CAUSE_EXT_INTERRUPT
|
||||
GOTO_M_MODE
|
||||
|
||||
GOTO_U_MODE
|
||||
jal cause_s_soft_interrupt // set software interrupt pending without it firing so we can make it fire in U mode
|
||||
|
||||
// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
|
||||
// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
|
||||
// CAUSE_EXT_INTERRUPT
|
||||
GOTO_U_MODE // Should cause software interrupt to fire off.
|
||||
|
||||
END_TESTS
|
||||
|
||||
|
||||
@ -21,7 +21,7 @@
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
#include "WALLY-TEST-LIB-64.h"
|
||||
#include "WALLY-TEST-LIB-32.h"
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
@ -35,7 +35,7 @@ WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources // *** commented
|
||||
|
||||
// test 5.3.1.4 Basic trap tests
|
||||
|
||||
// jal cause_instr_addr_misaligned //skipped becuase this exception may be impossible when compressed instructions are enabled)
|
||||
jal cause_instr_addr_misaligned
|
||||
jal cause_instr_access
|
||||
jal cause_illegal_instr
|
||||
jal cause_breakpnt
|
||||
@ -47,16 +47,21 @@ GOTO_U_MODE // Causes M mode ecall
|
||||
GOTO_S_MODE // Causes U mode ecall
|
||||
GOTO_M_MODE // Causes S mode ecall
|
||||
|
||||
jal cause_time_interrupt // *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
|
||||
jal cause_soft_interrupt // *** exiting out of the trap handler after these is current;y broken
|
||||
jal cause_ext_interrupt
|
||||
|
||||
jal cause_s_soft_interrupt
|
||||
jal cause_m_soft_interrupt
|
||||
jal cause_s_time_interrupt
|
||||
jal cause_m_time_interrupt
|
||||
jal cause_s_ext_interrupt_GPIO
|
||||
jal cause_m_ext_interrupt
|
||||
|
||||
|
||||
// try the traps again with mideleg = medeleg = all 1's to ensure traps still go to M mode from M mode
|
||||
|
||||
WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF
|
||||
WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
|
||||
|
||||
// jal cause_instr_addr_misaligned //skipped becuase this exception may be impossible when compressed instructions are enabled)
|
||||
jal cause_instr_addr_misaligned
|
||||
jal cause_instr_access
|
||||
jal cause_illegal_instr
|
||||
jal cause_breakpnt
|
||||
@ -66,9 +71,16 @@ jal cause_store_addr_misaligned
|
||||
jal cause_store_acc
|
||||
jal cause_ecall // M mode ecall
|
||||
|
||||
jal cause_time_interrupt // *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
|
||||
jal cause_soft_interrupt // *** exiting out of the trap handler after these is current;y broken
|
||||
jal cause_ext_interrupt
|
||||
jal cause_s_soft_interrupt // The delegated S mode interrupts should not fire since we're running in M mode.
|
||||
jal cause_m_soft_interrupt
|
||||
jal cause_s_time_interrupt
|
||||
jal cause_m_time_interrupt
|
||||
li a3, 0x40 // these interrupts involve a time loop waiting for the interrupt to go off.
|
||||
// since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3
|
||||
jal cause_s_ext_interrupt_GPIO
|
||||
li a3, 0x40
|
||||
jal cause_m_ext_interrupt
|
||||
|
||||
|
||||
END_TESTS
|
||||
|
||||
|
||||
@ -21,38 +21,46 @@
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
#include "WALLY-TEST-LIB-64.h"
|
||||
#include "WALLY-TEST-LIB-32.h"
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
|
||||
|
||||
// test 5.3.1.4 Basic trap tests
|
||||
|
||||
TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps
|
||||
TRAP_HANDLER m, DEBUG=1 // necessary to handle switching privilege modes
|
||||
TRAP_HANDLER s, DEBUG=1 // have S mode trap handler as well
|
||||
|
||||
// Like WALLY-trap, cause all the same traps from S mode and make sure they go to machine mode with zeroed mideleg, medeleg
|
||||
|
||||
li x28, 0x2
|
||||
csrs sstatus, x28 // set sstatus.SIE bit to 1
|
||||
WRITE_READ_CSR mie, 0xFFFF // sie is a subset of mie, so writing this also enables sie.
|
||||
|
||||
GOTO_S_MODE
|
||||
|
||||
li x28, 0x8
|
||||
csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode
|
||||
// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts
|
||||
jal cause_instr_addr_misaligned
|
||||
jal cause_instr_access
|
||||
jal cause_illegal_instr
|
||||
jal cause_breakpnt
|
||||
jal cause_load_addr_misaligned
|
||||
jal cause_load_acc
|
||||
jal cause_store_addr_misaligned
|
||||
jal cause_store_acc
|
||||
GOTO_U_MODE // Causes S mode ecall
|
||||
GOTO_S_MODE // Causes U mode ecall
|
||||
|
||||
|
||||
// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled)
|
||||
CAUSE_INSTR_ACCESS
|
||||
CAUSE_ILLEGAL_INSTR
|
||||
CAUSE_BREAKPNT
|
||||
CAUSE_LOAD_ADDR_MISALIGNED
|
||||
CAUSE_LOAD_ACC
|
||||
CAUSE_STORE_ADDR_MISALIGNED
|
||||
CAUSE_STORE_ACC
|
||||
CAUSE_ECALL
|
||||
|
||||
// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
|
||||
// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
|
||||
// CAUSE_EXT_INTERRUPT
|
||||
|
||||
// some interrupts excluded becaus writing MIP is illegal from S mode
|
||||
jal cause_s_soft_interrupt
|
||||
jal cause_m_soft_interrupt
|
||||
jal cause_m_time_interrupt
|
||||
li a3, 0x40 // this interrupt involves a time loop waiting for the interrupt to go off.
|
||||
// since interrupts are not always enabled,
|
||||
jal cause_s_ext_interrupt_GPIO
|
||||
li a3, 0x40
|
||||
jal cause_m_ext_interrupt
|
||||
|
||||
// Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler
|
||||
// We can tell which one becuase the different trap handler modes write different bits of the status register
|
||||
@ -63,21 +71,24 @@ GOTO_M_MODE // so we can write the delegate registers
|
||||
WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF
|
||||
WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
|
||||
|
||||
GOTO_S_MODE
|
||||
GOTO_S_MODE // Since we're running in M mode, this ecall will NOT be delegated to S mode
|
||||
|
||||
// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled)
|
||||
CAUSE_INSTR_ACCESS
|
||||
CAUSE_ILLEGAL_INSTR
|
||||
CAUSE_BREAKPNT
|
||||
CAUSE_LOAD_ADDR_MISALIGNED
|
||||
CAUSE_LOAD_ACC
|
||||
CAUSE_STORE_ADDR_MISALIGNED
|
||||
CAUSE_STORE_ACC
|
||||
CAUSE_ECALL
|
||||
jal cause_instr_addr_misaligned
|
||||
jal cause_instr_access
|
||||
jal cause_illegal_instr
|
||||
jal cause_breakpnt
|
||||
jal cause_load_addr_misaligned
|
||||
jal cause_load_acc
|
||||
jal cause_store_addr_misaligned
|
||||
jal cause_store_acc
|
||||
GOTO_U_MODE // Causes S mode ecall
|
||||
GOTO_S_MODE // Causes U mode ecall
|
||||
|
||||
// M mode interrupts cannot be delegated in this implementation, so they are excluded from tests
|
||||
jal cause_s_soft_interrupt
|
||||
li a3, 0x40
|
||||
jal cause_s_ext_interrupt_GPIO
|
||||
|
||||
// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
|
||||
// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
|
||||
// CAUSE_EXT_INTERRUPT
|
||||
|
||||
END_TESTS
|
||||
|
||||
|
||||
@ -0,0 +1,42 @@
|
||||
///////////////////////////////////////////
|
||||
//
|
||||
// WALLY-trap-sret
|
||||
//
|
||||
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
|
||||
//
|
||||
// Created 2022-04-10
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
#include "WALLY-TEST-LIB-32.h"
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
TRAP_HANDLER m, DEBUG=1
|
||||
|
||||
// test 5.3.1.6 Interrupt enabling and priority tests
|
||||
|
||||
li x28, 0x400000
|
||||
csrs mstatus, x28 // Set mstatus.tsr to 1.
|
||||
|
||||
GOTO_S_MODE
|
||||
|
||||
sret // attempt to run sret instruction.
|
||||
// should cause illegal instruction exception despite being in s mode
|
||||
|
||||
END_TESTS
|
||||
|
||||
TEST_STACK_AND_DATA
|
||||
@ -21,10 +21,12 @@
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
#include "WALLY-TEST-LIB-64.h"
|
||||
#include "WALLY-TEST-LIB-32.h"
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
|
||||
|
||||
// test 5.3.1.4 Basic trap tests
|
||||
|
||||
TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps
|
||||
@ -32,27 +34,30 @@ TRAP_HANDLER s, DEBUG=1 // have S mode trap handler as well
|
||||
|
||||
// Like WALLY-trap, cause all the same traps from U mode and make sure they go to machine mode with zeroed mideleg, medeleg
|
||||
|
||||
li x28, 0x2
|
||||
csrs sstatus, x28 // set sstatus.SIE bit to 1. Not strictly necessary but this lets us differentiate which trap handler we went to
|
||||
WRITE_READ_CSR mie, 0xFFFF
|
||||
|
||||
GOTO_U_MODE
|
||||
|
||||
// li x28, 0x8
|
||||
// csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode
|
||||
// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts
|
||||
|
||||
|
||||
// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled)
|
||||
CAUSE_INSTR_ACCESS
|
||||
CAUSE_ILLEGAL_INSTR
|
||||
CAUSE_BREAKPNT
|
||||
CAUSE_LOAD_ADDR_MISALIGNED
|
||||
CAUSE_LOAD_ACC
|
||||
CAUSE_STORE_ADDR_MISALIGNED
|
||||
CAUSE_STORE_ACC
|
||||
CAUSE_ECALL
|
||||
|
||||
// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
|
||||
// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
|
||||
// CAUSE_EXT_INTERRUPT
|
||||
jal cause_instr_addr_misaligned
|
||||
jal cause_instr_access
|
||||
jal cause_illegal_instr
|
||||
jal cause_breakpnt
|
||||
jal cause_load_addr_misaligned
|
||||
jal cause_load_acc
|
||||
jal cause_store_addr_misaligned
|
||||
jal cause_store_acc
|
||||
jal cause_ecall
|
||||
|
||||
// some interrupts excluded becaus writing SIP/MIP is illegal from U mode
|
||||
jal cause_m_soft_interrupt
|
||||
jal cause_m_time_interrupt
|
||||
li a3, 0x40 // this interrupt involves a time loop waiting for the interrupt to go off.
|
||||
// since interrupts are not always enabled,
|
||||
jal cause_s_ext_interrupt_GPIO
|
||||
li a3, 0x40
|
||||
jal cause_m_ext_interrupt
|
||||
|
||||
// Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler
|
||||
// We can tell which one becuase the different trap handler modes write different bits of the status register
|
||||
@ -65,19 +70,19 @@ WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
|
||||
|
||||
GOTO_U_MODE
|
||||
|
||||
// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled)
|
||||
CAUSE_INSTR_ACCESS
|
||||
CAUSE_ILLEGAL_INSTR
|
||||
CAUSE_BREAKPNT
|
||||
CAUSE_LOAD_ADDR_MISALIGNED
|
||||
CAUSE_LOAD_ACC
|
||||
CAUSE_STORE_ADDR_MISALIGNED
|
||||
CAUSE_STORE_ACC
|
||||
CAUSE_ECALL
|
||||
|
||||
// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
|
||||
// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
|
||||
// CAUSE_EXT_INTERRUPT
|
||||
jal cause_instr_addr_misaligned
|
||||
jal cause_instr_access
|
||||
jal cause_illegal_instr
|
||||
jal cause_breakpnt
|
||||
jal cause_load_addr_misaligned
|
||||
jal cause_load_acc
|
||||
jal cause_store_addr_misaligned
|
||||
jal cause_store_acc
|
||||
jal cause_ecall
|
||||
|
||||
// M mode interrupts cannot be delegated in this implementation, so they are excluded from tests
|
||||
li a3, 0x40
|
||||
jal cause_s_ext_interrupt_GPIO
|
||||
|
||||
END_TESTS
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
include ../../Makefile.include
|
||||
|
||||
RVTEST_DEFINES += -march=rv$(XLEN)ia # KMG: removed compressed instructions from privileged tests
|
||||
RVTEST_DEFINES += -march=rv$(XLEN)iaf # KMG: removed compressed instructions from privileged tests
|
||||
|
||||
$(eval $(call compile_template,-march=rv64iac -mabi=lp64 -Drvtest_mtrap_routine=True -DXLEN=$(XLEN)))
|
||||
$(eval $(call compile_template,-march=rv64iaf -mabi=lp64 -Drvtest_mtrap_routine=True -DXLEN=$(XLEN)))
|
||||
|
||||
@ -35,10 +35,13 @@ rv64i_sc_tests = \
|
||||
WALLY-CSR-permission-s-01 \
|
||||
WALLY-CSR-permission-u-01 \
|
||||
WALLY-misa-01 \
|
||||
WALLY-scratch-01 \
|
||||
WALLY-sscratch-s-01 \
|
||||
WALLY-AMO \
|
||||
WALLY-LRSC \
|
||||
WALLY-trap-sret-01 \
|
||||
# WALLY-scratch-01 \
|
||||
# WALLY-sscratch-s-01 \
|
||||
|
||||
# WALLY-scratch-01 \
|
||||
|
||||
# Don't simulate these because they rely on SoC features that Wally does not offer.
|
||||
target_tests_nosim = \
|
||||
@ -57,7 +60,18 @@ target_tests_nosim = \
|
||||
WALLY-MVENDORID \
|
||||
WALLY-CSR-PERMISSIONS-M \
|
||||
WALLY-CSR-PERMISSIONS-S \
|
||||
WALLY-mtvec-01 \
|
||||
WALLY-stvec-01 \
|
||||
WALLY-MIE-01 \
|
||||
WALLY-PIE-stack-01 \
|
||||
WALLY-PIE-stack-s-01 \
|
||||
WALLY-trap-01 \
|
||||
WALLY-trap-s-01 \
|
||||
WALLY-trap-u-01 \
|
||||
WALLY-status-tw-01 \
|
||||
WALLY-WFI-01 \
|
||||
WALLY-status-fp-enabled-01 \
|
||||
WALLY-status-fp-disabled-01 \
|
||||
# Have all 0's in references!
|
||||
#WALLY-MEPC \
|
||||
#WALLY-SEPC \
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,3 +1,17 @@
|
||||
00000aaa # Test 5.3.1.5: readback value of SIE after enabling all interrupts.
|
||||
00000000
|
||||
00000007 # mcause from m time interrupt
|
||||
80000000
|
||||
00000000 # mtval for mtime interrupt (0x0)
|
||||
00000000
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000000
|
||||
0000000b # mcause from M mode ecall from test termination
|
||||
00000000
|
||||
00000000 # mtval of ecall (*** defined to be zero for now)
|
||||
00000000
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000000
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
@ -1007,18 +1021,4 @@ deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,43 +1,43 @@
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
00000aaa # Test 5.3.1.5: readback value of MIE after enabling all interrupts.
|
||||
00000000
|
||||
00000222 # readback value of mideleg after attempting to delegate all interrupts.
|
||||
00000000
|
||||
0000000b # mcause from ecall for going from M mode to S mode
|
||||
00000000
|
||||
00000000 # mtval of ecall (*** defined to be zero for now)
|
||||
00000000
|
||||
00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000000
|
||||
00000001 # mcause from s soft interrupt
|
||||
80000000
|
||||
00000000 # mtval for ssoft interrupt (0x0)
|
||||
00000000
|
||||
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000000
|
||||
00000009 # mcause from ecall for going from S mode to M mode
|
||||
00000000
|
||||
00000000 # mtval of ecall (*** defined to be zero for now)
|
||||
00000000
|
||||
00000800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000000
|
||||
0000000b # mcause from ecall for going from M mode to U mode
|
||||
00000000
|
||||
00000000 # mtval of ecall (*** defined to be zero for now)
|
||||
00000000
|
||||
00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000000
|
||||
00000001 # mcause from s soft interrupt from user mode this time
|
||||
80000000
|
||||
00000000 # mtval for mtime interrupt (0x0)
|
||||
00000000
|
||||
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000000
|
||||
00000008 # mcause from U mode ecall from test termination
|
||||
00000000
|
||||
00000000 # mtval of ecall (*** defined to be zero for now)
|
||||
00000000
|
||||
00000000 # masked out mstatus.MPP = 00, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000000
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
|
||||
@ -1,5 +1,11 @@
|
||||
00000aaa # Test 5.3.1.4: readback value from writing mie to enable interrupts
|
||||
00000000
|
||||
00000000 # mcause from instruction addr misaligned fault
|
||||
00000000
|
||||
800003d2 # mtval of faulting instruction adress (0x800003d3)
|
||||
00000000
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000000
|
||||
00000001 # mcause from an instruction access fault
|
||||
00000000
|
||||
00000000 # mtval of faulting instruction address (0x0)
|
||||
@ -14,13 +20,13 @@
|
||||
00000000
|
||||
00000003 # mcause from Breakpoint
|
||||
00000000
|
||||
800003ec # mtval of breakpoint instruction adress (0x800003ec)
|
||||
80000404 # mtval of breakpoint instruction adress (0x80000404)
|
||||
00000000
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000000
|
||||
00000004 # mcause from load address misaligned
|
||||
00000000
|
||||
800003f5 # mtval of misaligned address (0x800003f5)
|
||||
8000040d # mtval of misaligned address (0x8000040d)
|
||||
00000000
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000000
|
||||
@ -32,7 +38,7 @@
|
||||
00000000
|
||||
00000006 # mcause from store misaligned
|
||||
00000000
|
||||
80000411 # mtval of address with misaligned store instr (0x80000410)
|
||||
80000429 # mtval of address with misaligned store instr (0x80000429)
|
||||
00000000
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000000
|
||||
@ -60,7 +66,31 @@
|
||||
00000000
|
||||
00000880 # masked out mstatus.MPP = 01 (from S mode), mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000000
|
||||
000007ec # value to indicate a vectored interrupts
|
||||
0007ec01 # value to indicate successful vectoring on s soft interrupt
|
||||
00000000
|
||||
00000001 # mcause value from s soft interrupt
|
||||
80000000
|
||||
00000000 # mtval for ssoft interrupt (0x0)
|
||||
00000000
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000000
|
||||
0007ec03 # value to indicate successful vectoring on m soft interrupt
|
||||
00000000
|
||||
00000003 # mcause value from m soft interrupt
|
||||
80000000
|
||||
00000000 # mtval for msoft interrupt (0x0)
|
||||
00000000
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000000
|
||||
0007ec05 # value to indicate successful vectoring on s time interrupt
|
||||
00000000
|
||||
00000005 # mcause value from s time interrupt
|
||||
80000000
|
||||
00000000 # mtval for stime interrupt (0x0)
|
||||
00000000
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000000
|
||||
0007ec07 # value to indicate successful vectoring on m time interrupt
|
||||
00000000
|
||||
00000007 # mcause value from m time interrupt
|
||||
80000000
|
||||
@ -68,15 +98,15 @@
|
||||
00000000
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000000
|
||||
000007ec # value to indicate a vectored interrupts
|
||||
0007ec09 # value to indicate successful vectoring on s ext interrupt
|
||||
00000000
|
||||
00000001 # mcause value from m soft interrupt
|
||||
00000009 # mcause value from s ext interrupt
|
||||
80000000
|
||||
00000000 # mtval for msoft interrupt (0x0)
|
||||
00000000 # mtval for sext interrupt (0x0)
|
||||
00000000
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000000
|
||||
000007ec # value to indicate a vectored interrupts
|
||||
0007ec0b # value to indicate successful vectoring on m ext interrupt
|
||||
00000000
|
||||
0000000b # mcause value from m ext interrupt
|
||||
80000000
|
||||
@ -84,11 +114,17 @@
|
||||
00000000
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000000
|
||||
0000b309 # medeleg after attempted write of all 1's (only some bits are writeable)
|
||||
00000000
|
||||
fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable)
|
||||
ffffffff
|
||||
00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
|
||||
00000000
|
||||
00000001 # Test 5.3.1.4: mcause from an instruction access fault
|
||||
00000000 # mcause from instruction addr misaligned fault
|
||||
00000000
|
||||
800003d2 # mtval of faulting instruction adress (0x800003d3)
|
||||
00000000
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000000
|
||||
00000001 # mcause from an instruction access fault
|
||||
00000000
|
||||
00000000 # mtval of faulting instruction address (0x0)
|
||||
00000000
|
||||
@ -102,13 +138,13 @@
|
||||
00000000
|
||||
00000003 # mcause from Breakpoint
|
||||
00000000
|
||||
800003ec # mtval of breakpoint instruction adress (0x800003ec)
|
||||
80000404 # mtval of breakpoint instruction adress (0x80000404)
|
||||
00000000
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000000
|
||||
00000004 # mcause from load address misaligned
|
||||
00000000
|
||||
800003f5 # mtval of misaligned address (0x800003f5)
|
||||
8000040d # mtval of misaligned address (0x8000040d)
|
||||
00000000
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000000
|
||||
@ -120,7 +156,7 @@
|
||||
00000000
|
||||
00000006 # mcause from store misaligned
|
||||
00000000
|
||||
80000411 # mtval of address with misaligned store instr (0x80000410)
|
||||
80000429 # mtval of address with misaligned store instr (0x80000429)
|
||||
00000000
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000000
|
||||
@ -136,23 +172,23 @@
|
||||
00000000
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000000
|
||||
000007ec # value to indicate a vectored interrupts
|
||||
0007ec03 # value to indicate successful vectoring on m soft interrupt
|
||||
00000000
|
||||
00000007 # mcause value from time interrupt
|
||||
80000000
|
||||
00000000 # mtval for mtime interrupt (0x0)
|
||||
00000000
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000000
|
||||
000007ec # value to indicate a vectored interrupts
|
||||
00000000
|
||||
00000001 # mcause value from m soft interrupt
|
||||
00000003 # mcause value from m soft interrupt
|
||||
80000000
|
||||
00000000 # mtval for msoft interrupt (0x0)
|
||||
00000000
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000000
|
||||
000007ec # value to indicate a vectored interrupts
|
||||
0007ec07 # value to indicate successful vectoring on m time interrupt
|
||||
00000000
|
||||
00000007 # mcause value from m time interrupt
|
||||
80000000
|
||||
00000000 # mtval for mtime interrupt (0x0)
|
||||
00000000
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000000
|
||||
0007ec0b # value to indicate successful vectoring on m ext interrupt
|
||||
00000000
|
||||
0000000b # mcause value from m ext interrupt
|
||||
80000000
|
||||
@ -986,89 +1022,3 @@ deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user