diff --git a/.gitignore b/.gitignore index 4f0006c5f..0a25e7d3d 100644 --- a/.gitignore +++ b/.gitignore @@ -71,3 +71,35 @@ synthDC/runs/ synthDC/hdl /pipelined/regression/power.saif tests/fp/vectors/*.tv +# Temporary configs produced for synthesis +pipelined/config/rv32e_FPUoff +pipelined/config/rv32e_PMP0 +pipelined/config/rv32e_PMP16 +pipelined/config/rv32e_noMulDiv +pipelined/config/rv32e_noPriv +pipelined/config/rv32e_orig +pipelined/config/rv32gc_FPUoff +pipelined/config/rv32gc_PMP0 +pipelined/config/rv32gc_PMP16 +pipelined/config/rv32gc_noMulDiv +pipelined/config/rv32gc_noPriv +pipelined/config/rv32gc_orig +pipelined/config/rv32ic_FPUoff +pipelined/config/rv32ic_PMP0 +pipelined/config/rv32ic_PMP16 +pipelined/config/rv32ic_noMulDiv +pipelined/config/rv32ic_noPriv +pipelined/config/rv32ic_orig +pipelined/config/rv64gc_FPUoff +pipelined/config/rv64gc_PMP0 +pipelined/config/rv64gc_PMP16 +pipelined/config/rv64gc_noMulDiv +pipelined/config/rv64gc_noPriv +pipelined/config/rv64gc_orig +pipelined/config/rv64ic_FPUoff +pipelined/config/rv64ic_PMP0 +pipelined/config/rv64ic_PMP16 +pipelined/config/rv64ic_noMulDiv +pipelined/config/rv64ic_noPriv +pipelined/config/rv64ic_orig +synthDC/Summary.csv diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index be67c99bd..effd553a6 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit be67c99bd461742aa1c100bcc0732657faae2230 +Subproject commit effd553a6a91ed9b0ba251796a8a44505a45174f diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index c08f3710e..585d3b82a 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -475,7 +475,7 @@ connect_debug_port u_ila_0/probe103 [get_nets [list wallypipelinedsoc/core/ifu/I create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe104] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe104] -connect_debug_port u_ila_0/probe104 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[63]}]] +connect_debug_port u_ila_0/probe104 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[0]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[1]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[2]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[3]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[4]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[5]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[6]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[7]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[8]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[9]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[10]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[11]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[12]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[13]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[14]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[15]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[16]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[17]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[18]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[19]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[20]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[21]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[22]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[23]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[24]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[25]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[26]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[27]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[28]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[29]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[30]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[31]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[32]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[33]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[34]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[35]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[36]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[37]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[38]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[39]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[40]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[41]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[42]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[43]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[44]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[45]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[46]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[47]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[48]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[49]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[50]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[51]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[52]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[53]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[54]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[55]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[56]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[57]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[58]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[59]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[60]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[61]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[62]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[63]}]] create_debug_port u_ila_0 probe @@ -743,3 +743,75 @@ create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe154] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe154] connect_debug_port u_ila_0/probe154 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[63]} ]] + + +create_debug_port u_ila_0 probe +set_property port_width 11 [get_debug_ports u_ila_0/probe155] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe155] +connect_debug_port u_ila_0/probe155 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/RBR[0]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[1]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[2]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[3]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[4]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[5]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[6]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[7]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[8]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[9]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[10]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe156] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe156] +connect_debug_port u_ila_0/probe156 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/rxparityerr} ]] + +create_debug_port u_ila_0 probe +set_property port_width 2 [get_debug_ports u_ila_0/probe157] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe157] +connect_debug_port u_ila_0/probe157 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/rxstate[0]} {wallypipelinedsoc/uncore/uart.uart/u/rxstate[1]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 2 [get_debug_ports u_ila_0/probe158] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe158] +connect_debug_port u_ila_0/probe158 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/txstate[0]} {wallypipelinedsoc/uncore/uart.uart/u/txstate[1]} ]] + + +create_debug_port u_ila_0 probe +set_property port_width 8 [get_debug_ports u_ila_0/probe159] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe159] +connect_debug_port u_ila_0/probe159 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/LCR[0]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[1]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[2]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[3]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[4]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[5]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[6]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[7]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 8 [get_debug_ports u_ila_0/probe160] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe160] +connect_debug_port u_ila_0/probe160 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/LSR[0]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[1]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[2]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[3]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[4]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[5]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[6]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[7]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 8 [get_debug_ports u_ila_0/probe161] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe161] +connect_debug_port u_ila_0/probe161 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/SCR[0]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[1]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[2]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[3]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[4]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[5]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[6]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[7]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 8 [get_debug_ports u_ila_0/probe162] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe162] +connect_debug_port u_ila_0/probe162 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/DLL[0]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[1]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[2]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[3]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[4]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[5]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[6]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[7]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 8 [get_debug_ports u_ila_0/probe163] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe163] +connect_debug_port u_ila_0/probe163 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/DLM[0]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[1]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[2]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[3]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[4]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[5]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[6]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[7]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 4 [get_debug_ports u_ila_0/probe164] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe164] +connect_debug_port u_ila_0/probe164 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/IER[0]} {wallypipelinedsoc/uncore/uart.uart/u/IER[1]} {wallypipelinedsoc/uncore/uart.uart/u/IER[2]} {wallypipelinedsoc/uncore/uart.uart/u/IER[3]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 4 [get_debug_ports u_ila_0/probe165] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe165] +connect_debug_port u_ila_0/probe165 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/MSR[0]} {wallypipelinedsoc/uncore/uart.uart/u/MSR[1]} {wallypipelinedsoc/uncore/uart.uart/u/MSR[2]} {wallypipelinedsoc/uncore/uart.uart/u/MSR[3]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 5 [get_debug_ports u_ila_0/probe166] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe166] +connect_debug_port u_ila_0/probe166 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/MCR[0]} {wallypipelinedsoc/uncore/uart.uart/u/MCR[1]} {wallypipelinedsoc/uncore/uart.uart/u/MCR[2]} {wallypipelinedsoc/uncore/uart.uart/u/MCR[3]} {wallypipelinedsoc/uncore/uart.uart/u/MCR[4]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 8 [get_debug_ports u_ila_0/probe167] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe167] +connect_debug_port u_ila_0/probe167 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/FCR[0]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[1]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[2]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[3]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[4]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[5]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[6]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[7]} ]] + +create_debug_port u_ila_0 probe +set_property port_width 64 [get_debug_ports u_ila_0/probe168] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe168] +connect_debug_port u_ila_0/probe168 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63]} ]] diff --git a/fpga/generator/wave_config.wcfg b/fpga/generator/wave_config.wcfg index f98274f2e..9a6af16f2 100644 --- a/fpga/generator/wave_config.wcfg +++ b/fpga/generator/wave_config.wcfg @@ -10,14 +10,14 @@ - - + + - + - + @@ -53,7 +53,6 @@ CPU to LSU label - FullPathName wallypipelinedsoc/core/IEUAdrM[63:0] @@ -111,7 +110,6 @@ PLIC label - FullPathName wallypipelinedsoc/uncore/plic.plic/requests[12:1] @@ -140,7 +138,6 @@ interrupts label - wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[63:0] MEDELEG_REGW[63:0] @@ -178,7 +175,6 @@ LSU to Bus label - FullPathName wallypipelinedsoc/core/lsu/LSUBusRead @@ -312,7 +308,6 @@ sdc label - FullPathName wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_ERROR_Q @@ -352,144 +347,4 @@ STYLE_DIGITAL - - FullPathName - wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[11:0] - IP_REGW_writeable[11:0] - HEXRADIX - true - STYLE_DIGITAL - - - FullPathName - wallypipelinedsoc/core/priv.priv/csr/csri/MExtIntM - MExtIntM - true - STYLE_DIGITAL - - - FullPathName - wallypipelinedsoc/core/priv.priv/csr/csri/SExtIntM - SExtIntM - true - STYLE_DIGITAL - - - FullPathName - wallypipelinedsoc/core/priv.priv/csr/csri/SwIntM - SwIntM - true - STYLE_DIGITAL - - - FullPathName - wallypipelinedsoc/core/priv.priv/csr/csri/TimerIntM - TimerIntM - true - STYLE_DIGITAL - - - FullPathName - wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[63:0] - MEDELEG_REGW[63:0] - HEXRADIX - true - STYLE_DIGITAL - - - FullPathName - wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11:0] - MIDELEG_REGW[11:0] - HEXRADIX - true - STYLE_DIGITAL - - - FullPathName - wallypipelinedsoc/uncore/clint.clint/MTIMECMP[63:0] - MTIMECMP[63:0] - HEXRADIX - true - STYLE_DIGITAL - - - FullPathName - wallypipelinedsoc/uncore/clint.clint/MTIME[63:0] - MTIME[63:0] - HEXRADIX - true - STYLE_DIGITAL - - - FullPathName - wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[10:1] - intEn[1]__0[10:1] - HEXRADIX - true - STYLE_DIGITAL - - - FullPathName - wallypipelinedsoc/uncore/plic.plic/intPriority[10][2:0] - intPriority[10][2:0] - HEXRADIX - true - STYLE_DIGITAL - - - FullPathName - wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][10:1] - irqMatrix[1][1][10:1] - HEXRADIX - true - STYLE_DIGITAL - - - FullPathName - wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][10:1] - irqMatrix[1][2][10:1] - HEXRADIX - true - STYLE_DIGITAL - - - FullPathName - wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][10:1] - irqMatrix[1][3][10:1] - HEXRADIX - true - STYLE_DIGITAL - - - FullPathName - wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][10:1] - irqMatrix[1][4][10:1] - HEXRADIX - true - STYLE_DIGITAL - - - FullPathName - wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][10:1] - irqMatrix[1][5][10:1] - HEXRADIX - true - STYLE_DIGITAL - - - FullPathName - wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][10:1] - irqMatrix[1][6][10:1] - HEXRADIX - true - STYLE_DIGITAL - - - FullPathName - wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][10:1] - irqMatrix[1][7][10:1] - HEXRADIX - true - STYLE_DIGITAL - diff --git a/linux/buildroot-config-src/wally/rootfs_overlay/.profile b/linux/buildroot-config-src/wally/rootfs_overlay/.profile index 65dccfef0..eecc0d421 100644 --- a/linux/buildroot-config-src/wally/rootfs_overlay/.profile +++ b/linux/buildroot-config-src/wally/rootfs_overlay/.profile @@ -2,8 +2,8 @@ echo "Hello this ~/.profile is meant to demonstrate running some basic commands echo "I am $(whoami)" echo "And I am on $(hostname)" touch myFile.txt -echo "This is a line of text." > myFile.txt -echo "A second line of text." >> myFile.txt +echo "Hello World!" > myFile.txt +echo "And farewell!" >> myFile.txt mkdir myDir mv myFile.txt myDir echo "Created myFile.txt and moved it to myDir. It contains:" @@ -17,10 +17,7 @@ cd myDir ln -s ../myScript.sh symLinkToMyScript.sh echo "Created symLinkToMyScript.sh. Running it yields:" ./symLinkToMyScript.sh -ln ../myScript.sh hardLinkToMyScript.sh -echo "Created hardLinkToMyScript.sh. Running it yields:" -./hardLinkToMyScript.sh -echo "Now let\'s remove all these example files and scripts" +echo "Now let's remove all these example files and scripts" cd / rm -r myDir rm myScript.sh @@ -28,10 +25,5 @@ echo "Here is disk usage:" df -h echo "And here are the current processes:" ps -echo "We can create a user." -cd / -mkdir home -echo "password\npassword\n" | adduser myUser -su -c "cd ~; echo \"I am $(whoami) (a new user) and my home directory is $(pwd)\"" echo "And finally a login prompt." login diff --git a/linux/buildroot-scripts/Makefile b/linux/buildroot-scripts/Makefile index 34f5e3450..41ceacb41 100644 --- a/linux/buildroot-scripts/Makefile +++ b/linux/buildroot-scripts/Makefile @@ -1,4 +1,5 @@ -IMAGES := ${RISCV}/buildroot/output/images +BUILDROOT := ${RISCV}/buildroot +IMAGES := ${BUILDROOT}/output/images DIS := ${IMAGES}/disassembly all: @@ -7,7 +8,7 @@ all: generate: # generating device tree binary - dtc -I dts -O dtb ../devicetree/wally-virt.dts > ${RISCV}/buildroot/output/images/wally-virt.dtb + dtc -I dts -O dtb ../devicetree/wally-virt.dts > ${IMAGES}/wally-virt.dtb disassemble: mkdir -p ${DIS} @@ -21,6 +22,9 @@ disassemble: ${DIS}/fw_jump.objdump: ${IMAGES}/fw_jump.elf riscv64-unknown-elf-objdump -S ${IMAGES}/fw_jump.elf >> ${DIS}/fw_jump.objdump +${IMAGES}/vmlinux: ${BUILDROOT}/output/build/linux-5.10.7/vmlinux + cp ${BUILDROOT}/output/build/linux-5.10.7/vmlinux ${IMAGES}/vmlinux + ${DIS}/vmlinux.objdump: ${IMAGES}/vmlinux riscv64-unknown-elf-objdump -S ${IMAGES}/vmlinux >> ${DIS}/vmlinux.objdump diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh index 7587a9f2c..92abecde3 100644 --- a/pipelined/config/buildroot/wally-config.vh +++ b/pipelined/config/buildroot/wally-config.vh @@ -29,7 +29,6 @@ `define FPGA 1 `define QEMU 1 -`define LINUX_FIX_READ {'h10000005} // RV32 or RV64: XLEN = 32 or 64 `define XLEN 64 @@ -78,6 +77,9 @@ // Address space `define RESET_VECTOR 64'h0000000000001000 +// WFI Timeout Wait +`define WFI_TIMEOUT_BIT 20 + // Peripheral Addresses // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits @@ -126,6 +128,8 @@ `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 +`define BPRED_SIZE 10 + `define REPLAY 0 `define HPTW_WRITES_SUPPORTED 1 diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh index fc63937c1..b101a6796 100644 --- a/pipelined/config/fpga/wally-config.vh +++ b/pipelined/config/fpga/wally-config.vh @@ -79,6 +79,9 @@ // Address space `define RESET_VECTOR 64'h0000000000001000 +// WFI Timeout Wait +`define WFI_TIMEOUT_BIT 20 + // Peripheral Addresses // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits @@ -134,6 +137,8 @@ `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 1 +`define BPRED_SIZE 10 + `define REPLAY 0 `define HPTW_WRITES_SUPPORTED 1 diff --git a/pipelined/config/rv32e/wally-config.vh b/pipelined/config/rv32e/wally-config.vh index 42e20affe..5832033ab 100644 --- a/pipelined/config/rv32e/wally-config.vh +++ b/pipelined/config/rv32e/wally-config.vh @@ -80,6 +80,9 @@ // Address space `define RESET_VECTOR 32'h80000000 +// WFI Timeout Wait +`define WFI_TIMEOUT_BIT 20 + // Peripheral Addresses // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits @@ -131,6 +134,7 @@ `define BPRED_ENABLED 0 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 +`define BPRED_SIZE 10 `define REPLAY 0 `define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh index 022447ff6..41645e8ab 100644 --- a/pipelined/config/rv32gc/wally-config.vh +++ b/pipelined/config/rv32gc/wally-config.vh @@ -78,6 +78,9 @@ // Address space `define RESET_VECTOR 32'h80000000 +// WFI Timeout Wait +`define WFI_TIMEOUT_BIT 20 + // Peripheral Addresses // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits @@ -129,6 +132,7 @@ `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 +`define BPRED_SIZE 10 `define REPLAY 0 `define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv32ia/BTBPredictor.txt b/pipelined/config/rv32i/BTBPredictor.txt similarity index 100% rename from pipelined/config/rv32ia/BTBPredictor.txt rename to pipelined/config/rv32i/BTBPredictor.txt diff --git a/pipelined/config/rv32ia/twoBitPredictor.txt b/pipelined/config/rv32i/twoBitPredictor.txt similarity index 100% rename from pipelined/config/rv32ia/twoBitPredictor.txt rename to pipelined/config/rv32i/twoBitPredictor.txt diff --git a/pipelined/config/rv32ia/wally-config.vh b/pipelined/config/rv32i/wally-config.vh similarity index 93% rename from pipelined/config/rv32ia/wally-config.vh rename to pipelined/config/rv32i/wally-config.vh index 93042b8c0..a263beaa4 100644 --- a/pipelined/config/rv32ia/wally-config.vh +++ b/pipelined/config/rv32i/wally-config.vh @@ -37,8 +37,8 @@ // IEEE 754 compliance `define IEEE754 0 -// IA -`define MISA (32'h00000100 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 << 3 | 1 << 5) +// I +`define MISA (32'h00000100 | 1 << 20 | 1 << 18 ) `define ZICSR_SUPPORTED 1 `define ZIFENCEI_SUPPORTED 1 `define COUNTERS 32 @@ -80,6 +80,9 @@ // Address space `define RESET_VECTOR 32'h80000000 +// WFI Timeout Wait +`define WFI_TIMEOUT_BIT 5 + // Peripheral Addresses // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits @@ -92,10 +95,10 @@ `define EXT_MEM_SUPPORTED 1'b0 `define EXT_MEM_BASE 34'h80000000 `define EXT_MEM_RANGE 34'h07FFFFFF -`define CLINT_SUPPORTED 1'b0 +`define CLINT_SUPPORTED 1'b1 `define CLINT_BASE 34'h02000000 `define CLINT_RANGE 34'h0000FFFF -`define GPIO_SUPPORTED 1'b0 +`define GPIO_SUPPORTED 1'b1 `define GPIO_BASE 34'h10060000 `define GPIO_RANGE 34'h000000FF `define UART_SUPPORTED 1'b1 @@ -126,11 +129,13 @@ `define PLIC_GPIO_ID 3 `define PLIC_UART_ID 10 -`define TWO_BIT_PRELOAD "../config/rv32ia/twoBitPredictor.txt" -`define BTB_PRELOAD "../config/rv32ia/BTBPredictor.txt" +`define TWO_BIT_PRELOAD "../config/rv32i/twoBitPredictor.txt" +`define BTB_PRELOAD "../config/rv32i/BTBPredictor.txt" `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 +`define BPRED_SIZE 10 + `define REPLAY 0 `define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh index fcd3c8e5e..b615c739d 100644 --- a/pipelined/config/rv32ic/wally-config.vh +++ b/pipelined/config/rv32ic/wally-config.vh @@ -78,6 +78,9 @@ // Address space `define RESET_VECTOR 32'h80000000 +// WFI Timeout Wait +`define WFI_TIMEOUT_BIT 20 + // Peripheral Addresses // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits @@ -129,6 +132,8 @@ `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 +`define BPRED_SIZE 10 + `define REPLAY 0 `define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv64BP/wally-config.vh b/pipelined/config/rv64BP/wally-config.vh index 005a1de3f..417051f1c 100644 --- a/pipelined/config/rv64BP/wally-config.vh +++ b/pipelined/config/rv64BP/wally-config.vh @@ -59,7 +59,7 @@ // TLB configuration. Entries should be a power of 2 `define ITLB_ENTRIES 32 -`define DTLB_ENTRIES 32 +`define DTLB_ENTRIES 32 // Cache configuration. Sizes should be a power of two // typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines @@ -82,6 +82,9 @@ // Bus Interface width `define AHBW 64 +// WFI Timeout Wait +`define WFI_TIMEOUT_BIT 20 + // Peripheral Addresses // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits @@ -132,6 +135,8 @@ //`define BPTYPE "BPGSHARE" // BPGLOBAL or BPTWOBIT or BPGSHARE `define BPTYPE "BPGSHARE" // BPTWOBIT or "BPGLOBAL" or BPLOCALPAg or BPGSHARE `define TESTSBP 1 +`define BPRED_SIZE 10 + `define REPLAY 0 `define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv64fp/wally-config.vh b/pipelined/config/rv64fp/wally-config.vh index d25827b73..da74f981d 100644 --- a/pipelined/config/rv64fp/wally-config.vh +++ b/pipelined/config/rv64fp/wally-config.vh @@ -84,6 +84,9 @@ // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits +// WFI Timeout Wait +`define WFI_TIMEOUT_BIT 20 + // *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file? `define BOOTROM_SUPPORTED 1'b1 `define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder @@ -130,6 +133,8 @@ `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 +`define BPRED_SIZE 10 + `define REPLAY 0 `define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh index 6af3c7bd9..b069a532c 100644 --- a/pipelined/config/rv64gc/wally-config.vh +++ b/pipelined/config/rv64gc/wally-config.vh @@ -82,6 +82,9 @@ // Bus Interface width `define AHBW 64 +// WFI Timeout Wait +`define WFI_TIMEOUT_BIT 20 + // Peripheral Physiccal Addresses // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits @@ -132,6 +135,7 @@ `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 +`define BPRED_SIZE 10 `define REPLAY 0 `define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv64ia/BTBPredictor.txt b/pipelined/config/rv64i/BTBPredictor.txt similarity index 100% rename from pipelined/config/rv64ia/BTBPredictor.txt rename to pipelined/config/rv64i/BTBPredictor.txt diff --git a/pipelined/config/rv64ia/twoBitPredictor.txt b/pipelined/config/rv64i/twoBitPredictor.txt similarity index 100% rename from pipelined/config/rv64ia/twoBitPredictor.txt rename to pipelined/config/rv64i/twoBitPredictor.txt diff --git a/pipelined/config/rv64ia/wally-config.vh b/pipelined/config/rv64i/wally-config.vh similarity index 94% rename from pipelined/config/rv64ia/wally-config.vh rename to pipelined/config/rv64i/wally-config.vh index 43bd1ecd4..e936364c5 100644 --- a/pipelined/config/rv64ia/wally-config.vh +++ b/pipelined/config/rv64i/wally-config.vh @@ -37,8 +37,8 @@ // IEEE 754 compliance `define IEEE754 0 -// MISA RISC-V configuration per specification IA -`define MISA (32'h00000100 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 << 3 | 1 << 5) +// MISA RISC-V configuration per specification I +`define MISA (32'h00000100 | 1 << 20 | 1 << 18 ) `define ZICSR_SUPPORTED 1 `define ZIFENCEI_SUPPORTED 1 `define COUNTERS 32 @@ -82,6 +82,9 @@ // Bus Interface width `define AHBW 64 +// WFI Timeout Wait +`define WFI_TIMEOUT_BIT 5 + // Peripheral Physiccal Addresses // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits @@ -127,11 +130,12 @@ `define PLIC_GPIO_ID 3 `define PLIC_UART_ID 10 -`define TWO_BIT_PRELOAD "../config/rv64ia/twoBitPredictor.txt" -`define BTB_PRELOAD "../config/rv64ia/BTBPredictor.txt" +`define TWO_BIT_PRELOAD "../config/rv64i/twoBitPredictor.txt" +`define BTB_PRELOAD "../config/rv64i/BTBPredictor.txt" `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 +`define BPRED_SIZE 10 `define REPLAY 0 `define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv64ic/wally-config.vh b/pipelined/config/rv64ic/wally-config.vh index c46dbfe70..592304764 100644 --- a/pipelined/config/rv64ic/wally-config.vh +++ b/pipelined/config/rv64ic/wally-config.vh @@ -82,6 +82,9 @@ // Bus Interface width `define AHBW 64 +// WFI Timeout Wait +`define WFI_TIMEOUT_BIT 20 + // Peripheral Physiccal Addresses // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits @@ -132,6 +135,7 @@ `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 +`define BPRED_SIZE 10 `define REPLAY 0 `define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/regression/regression-wally b/pipelined/regression/regression-wally index cbd2caf75..a05e21924 100755 --- a/pipelined/regression/regression-wally +++ b/pipelined/regression/regression-wally @@ -45,7 +45,7 @@ configs = [ ) ] def getBuildrootTC(short): - INSTR_LIMIT = 100000 # multiple of 100000 + INSTR_LIMIT = 4000000 # multiple of 100000; 4M is interesting because it gets into the kernel and enabling VM MAX_EXPECTED = 246000000 if short: BRcmd="vsim > {} -c < {} -c < {} -c < {} -c < {} -c <work/torture.tv") || die("Can't write torture.tv"); +my $datestring = localtime(); +print(TORTURE "// Torture tests generated $datestring by $0\n"); +foreach my $tv (@names) { + open(TV, "work/$tv") || die("Can't read $tv"); + my $type = &getType($tv); # is it mul, add, mulAdd + my $rm = &getRm($tv); # rounding mode +# if ($rm != 0) { next; } # only do rz + print (TORTURE "\n////////// Testcases from $tv of type $type rounding mode $rm\n"); + print ("\n////////// Testcases from $tv of type $type rounding mode $rm\n"); + my $linecount = 0; + my $babyTorture = 0; + while () { + my $line = $_; + $linecount++; + my $density = 10; + if ($type eq "mulAdd") {$density = 500;} + if ($babyTorture) { + $density = 100; + if ($type eq "mulAdd") {$density = 50000;} + } + if ((($linecount + $rm) % $density) != 0) { next }; # too many tests to use + chomp($line); # strip off newline + my @parts = split(/_/, $line); + my ($x, $y, $z, $op, $w, $flags); + $x = $parts[0]; + if ($type eq "add") { $y = "0000"; } else {$y = $parts[1]}; + if ($type eq "mul") { $z = "3CFF"; } elsif ($type eq "add") {$z = $parts[1]} else { $z = $parts[2]}; + $op = $rm << 4; + if ($type eq "mul" || $type eq "mulAdd") { $op = $op + 8; } + if ($type eq "add" || $type eq "mulAdd") { $op = $op + 4; } + my $opname = sprintf("%02x", $op); + if ($type eq "mulAdd") {$w = $parts[3];} else {$w = $parts[2]}; + if ($type eq "mulAdd") {$flags = $parts[4];} else {$flags = $parts[3]}; + $flags = substr($flags, -1); # take last character + if (&fpval($w) eq "NaN") { $w = "7e00"; } + my $vec = "${x}_${y}_${z}_${opname}_${w}_${flags}"; + my $skip = ""; + if (&isdenorm($x) || &isdenorm($y) || &isdenorm($z) || &isdenorm($w)) { + $skip = "Skipped denorm"; + } + my $summary = &summary($x, $y, $z, $w, $type); + if ($skip ne "") { + print TORTURE "// $skip $tv line $linecount $line $summary\n" + } + else { print TORTURE "$vec // $tv line $linecount $line $summary\n";} + } + close(TV); +} +close(TORTURE); + +sub fpval { + my $val = shift; + $val = hex($val); # convert hex string to number + my $frac = $val & 0x3FF; + my $exp = ($val >> 10) & 0x1F; + my $sign = $val >> 15; + + my $res; + if ($exp == 31 && $frac != 0) { return "NaN"; } + elsif ($exp == 31) { $res = "INF"; } + elsif ($val == 0) { $res = 0; } + elsif ($exp == 0) { $res = "Denorm"; } + else { $res = sprintf("1.%011b x 2^%d", $frac, $exp-15); } + + if ($sign == 1) { $res = "-$res"; } + return $res; +} + +sub summary { + my $x = shift; my $y = shift; my $z = shift; my $w = shift; my $type = shift; + + my $xv = &fpval($x); + my $yv = &fpval($y); + my $zv = &fpval($z); + my $wv = &fpval($w); + + if ($type eq "add") { return "$xv + $zv = $wv"; } + elsif ($type eq "mul") { return "$xv * $yv = $wv"; } + else {return "$xv * $yv + $zv = $wv"; } +} + +sub getType { + my $tv = shift; + + if ($tv =~ /mulAdd/) { return("mulAdd"); } + elsif ($tv =~ /mul/) { return "mul"; } + else { return "add"; } +} + +sub getRm { + my $tv = shift; + + if ($tv =~ /rz/) { return 0; } + elsif ($tv =~ /rne/) { return 1; } + elsif ($tv =~ /rd/) {return 2; } + elsif ($tv =~ /ru/) { return 3; } + else { return "bad"; } +} + +sub isdenorm { + my $fp = shift; + my $val = hex($fp); + my $expv = $val >> 10; + $expv = $expv & 0x1F; + my $denorm = 0; + if ($expv == 0 && $val != 0) { $denorm = 1;} + # my $e0 = ($expv == 0); + # my $vn0 = ($val != 0); + # my $denorm = 0; #($exp == 0 && $val != 0); # denorm exponent but not all zero + # print("Num $fp Exp $expv Denorm $denorm Done\n"); + return $denorm; +} \ No newline at end of file diff --git a/pipelined/src/fpu/fcvtfp.sv b/pipelined/src/fpu/fcvtfp.sv index e93822ee5..fb8e1ad9a 100644 --- a/pipelined/src/fpu/fcvtfp.sv +++ b/pipelined/src/fpu/fcvtfp.sv @@ -30,11 +30,17 @@ module cvtfp ( logic [31:0] DSRes; // double to single precision result + // add support for all formats + // consider reordering code blocks so upconverting is in one region of the file + // and downconverting is in the other region. /////////////////////////////////////////////////////////////////////////////// - // LZC + // LZC: Leading Zero Counter /////////////////////////////////////////////////////////////////////////////// + // *** consider sharing this with fcvtint + // *** emphasize parallel structure between the two + // *** add a priorityencoder module to generic (similar to priorityonehot) and use it // LZC - find the first 1 in the input's mantissa logic [8:0] i,NormCnt; diff --git a/pipelined/src/fpu/fcvtint.sv b/pipelined/src/fpu/fcvtint.sv index d394d7c3e..6a6686993 100644 --- a/pipelined/src/fpu/fcvtint.sv +++ b/pipelined/src/fpu/fcvtint.sv @@ -61,6 +61,10 @@ module fcvt ( // fcvt.d.l = 100 // fcvt.d.lu = 110 // {long, unsigned, to int} + + // *** revisit this module, explain in more depth + // should the int to fp and fp to int paths be separated? + // add support for all formats // calculate signals based off the input and output's size assign Res64 = (FOpCtrlE[0]&FOpCtrlE[2]) | (FmtE&~FOpCtrlE[0]); diff --git a/pipelined/src/hazard/hazard.sv b/pipelined/src/hazard/hazard.sv index 0fa6706de..368d4e52d 100644 --- a/pipelined/src/hazard/hazard.sv +++ b/pipelined/src/hazard/hazard.sv @@ -79,8 +79,8 @@ module hazard( // Each stage flushes if the previous stage is the last one stalled (for cause) or the system has reason to flush assign FlushF = BPPredWrongE | InvalidateICacheM; - assign FlushD = FirstUnstalledD | TrapM | RetM | BPPredWrongE | InvalidateICacheM; - assign FlushE = FirstUnstalledE | TrapM | RetM | BPPredWrongE | InvalidateICacheM; + assign FlushD = FirstUnstalledD | TrapM | RetM | BPPredWrongE | InvalidateICacheM; // *** does RetM only need to flush if the privilege changes? + assign FlushE = FirstUnstalledE | TrapM | RetM | BPPredWrongE | InvalidateICacheM; // *** why is BPPredWrongE here, but not needed in simple processor assign FlushM = FirstUnstalledM | TrapM | RetM | InvalidateICacheM; // on Trap the memory stage should be flushed going into the W stage, // except if the instruction causing the Trap is an ecall or ebreak. diff --git a/pipelined/src/ieu/alu.sv b/pipelined/src/ieu/alu.sv index 50100c3c7..c5184c578 100644 --- a/pipelined/src/ieu/alu.sv +++ b/pipelined/src/ieu/alu.sv @@ -40,9 +40,9 @@ module alu #(parameter WIDTH=32) ( logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult; logic Carry, Neg; logic LT, LTU; - logic Overflow; logic W64, SubArith, ALUOp; logic [2:0] ALUFunct; + logic Asign, Bsign; // Extract control signals // W64 indicates RV64 W-suffix instructions acting on lower 32-bit word @@ -57,12 +57,13 @@ module alu #(parameter WIDTH=32) ( // Shifts shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift)); - // condition code flags based on subtract output + // condition code flags based on subtract output Sum = A-B // Overflow occurs when the numbers being subtracted have the opposite sign // and the result has the opposite sign of A - assign Overflow = (A[WIDTH-1] ^ B[WIDTH-1]) & (A[WIDTH-1] ^ Sum[WIDTH-1]); assign Neg = Sum[WIDTH-1]; - assign LT = Neg ^ Overflow; + assign Asign = A[WIDTH-1]; + assign Bsign = B[WIDTH-1]; + assign LT = Asign & ~Bsign | Asign & Neg | ~Bsign & Neg; // simplified from Overflow = Asign & Bsign & Asign & Neg; LT = Neg ^ Overflow assign LTU = ~Carry; // SLT diff --git a/pipelined/src/ieu/comparator.sv b/pipelined/src/ieu/comparator.sv index f1a668616..26ea6d868 100644 --- a/pipelined/src/ieu/comparator.sv +++ b/pipelined/src/ieu/comparator.sv @@ -36,9 +36,8 @@ module comparator #(parameter WIDTH=32) ( logic [WIDTH-1:0] bbar, diff; logic carry, eq, neg, overflow, lt, ltu; - - // NOTE: This can be replaced by some faster logic optimized - // to just compute flags and not the difference. +/* + // Subtractor implementation // subtraction assign bbar = ~b; @@ -53,5 +52,35 @@ module comparator #(parameter WIDTH=32) ( assign lt = neg ^ overflow; assign ltu = ~carry; assign flags = {eq, lt, ltu}; +*/ + + /* verilator lint_off UNOPTFLAT */ + // prefix implementation + localparam levels=$clog2(WIDTH); + genvar i; + genvar level; + logic [WIDTH-1:0] e[levels:0]; + logic [WIDTH-1:0] l[levels:0]; + logic eq2, lt2, ltu2; + + // Bitwise logic + assign e[0] = a ~^ b; // bitwise equality + assign l[0] = ~a & b; // bitwise less than unsigned: A=0 and B=1 + + // Recursion + for (level = 1; level<=levels; level++) begin + for (i=0; i= 5) begin $display("%tns, %d instrs: Reg Write Address %02d ? expected value: %02d", $time, AttemptedInstructionCount, dut.core.ieu.dp.regf.a3, ExpectedRegAdrW); diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 2b8e6df8b..bf4903e51 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -361,8 +361,8 @@ module riscvassertions; // assert (`MEM_DCACHE == 0 | `MEM_DTIM == 0) else $error("Can't simultaneously have a data cache and TIM"); assert (`DMEM == `MEM_CACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache"); assert (`IMEM == `MEM_CACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache"); - assert (`DMEM == `MEM_CACHE | `DBUS ==0) else $error("Dcache rquires DBUS."); - assert (`IMEM == `MEM_CACHE | `IBUS ==0) else $error("Icache rquires IBUS."); + //assert (`DMEM == `MEM_CACHE | `DBUS ==0) else $error("Dcache rquires DBUS."); + //assert (`IMEM == `MEM_CACHE | `IBUS ==0) else $error("Icache rquires IBUS."); end endmodule diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index 90d41f556..e7841bab8 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -47,7 +47,8 @@ string tvpaths[] = '{ string wally64a[] = '{ `WALLYTEST, "rv64i_m/privilege/WALLY-AMO", "2210", - "rv64i_m/privilege/WALLY-LRSC", "2410" + "rv64i_m/privilege/WALLY-LRSC", "2410", + "rv64i_m/privilege/WALLY-status-fp-enabled-01", "50a0" }; string wally32a[] = '{ @@ -1467,11 +1468,22 @@ string imperas32f[] = '{ "rv64i_m/privilege/WALLY-MTVEC", "002090", "rv64i_m/privilege/WALLY-MVENDORID", "004090", */ "rv64i_m/privilege/WALLY-PMA", "0050a0", - "rv64i_m/privilege/WALLY-PMP", "0050a0" + "rv64i_m/privilege/WALLY-PMP", "0050a0", // "rv64i_m/privilege/WALLY-SCAUSE", "002090", // "rv64i_m/privilege/WALLY-scratch-01", "0040a0", // "rv64i_m/privilege/WALLY-sscratch-s-01", "0040a0", -// "rv64i_m/privilege/WALLY-trap-01", "0050a0" + "rv64i_m/privilege/WALLY-trap-01", "0050a0", + "rv64i_m/privilege/WALLY-trap-s-01", "0050a0", + "rv64i_m/privilege/WALLY-trap-u-01", "0050a0", + "rv64i_m/privilege/WALLY-MIE-01", "0050a0", + "rv64i_m/privilege/WALLY-mtvec-01", "0050a0", + "rv64i_m/privilege/WALLY-stvec-01", "0050a0", + "rv64i_m/privilege/WALLY-PIE-stack-01", "0050a0", + "rv64i_m/privilege/WALLY-PIE-stack-s-01", "0050a0", + "rv64i_m/privilege/WALLY-trap-sret-01", "0050a0", + // "rv64i_m/privilege/WALLY-status-tw-01", "0050a0", + "rv64i_m/privilege/WALLY-WFI-01", "0050a0", + "rv64i_m/privilege/WALLY-status-fp-disabled-01", "50a0" // "rv64i_m/privilege/WALLY-STVEC", "002090", // "rv64i_m/privilege/WALLY-UCAUSE", "002090", @@ -1534,15 +1546,23 @@ string wally32i[] = '{ string wally32priv[] = '{ `WALLYTEST, - "rv32i_m/privilege/WALLY-CSR-permission-s-01", "004060", - "rv32i_m/privilege/WALLY-CSR-permission-u-01", "004060", - "rv32i_m/privilege/WALLY-minfo-01", "004060", - "rv32i_m/privilege/WALLY-misa-01", "004060", - "rv32i_m/privilege/WALLY-MMU-SV32", "004060", - "rv32i_m/privilege/WALLY-PMA", "004060", - "rv32i_m/privilege/WALLY-PMP", "004060", - "rv32i_m/privilege/WALLY-scratch-01", "004060", - "rv32i_m/privilege/WALLY-sscratch-s-01", "004060" + "rv32i_m/privilege/WALLY-CSR-permission-s-01", "006080", + "rv32i_m/privilege/WALLY-CSR-permission-u-01", "006080", + "rv32i_m/privilege/WALLY-minfo-01", "005080", + "rv32i_m/privilege/WALLY-misa-01", "005080", + "rv32i_m/privilege/WALLY-MMU-SV32", "005080", + "rv32i_m/privilege/WALLY-PMA", "005080", + "rv32i_m/privilege/WALLY-PMP", "005080", + "rv32i_m/privilege/WALLY-trap-01", "005080", + "rv32i_m/privilege/WALLY-trap-s-01", "005080", + "rv32i_m/privilege/WALLY-trap-u-01", "005080", + "rv32i_m/privilege/WALLY-MIE-01", "005080", + "rv32i_m/privilege/WALLY-mtvec-01", "005080", + "rv32i_m/privilege/WALLY-stvec-01", "005080", + "rv32i_m/privilege/WALLY-PIE-stack-01", "005080", + "rv32i_m/privilege/WALLY-PIE-stack-s-01", "005080", + "rv32i_m/privilege/WALLY-trap-sret-01", "005080" + }; string wally32periph[] = '{ diff --git a/synthDC/Makefile b/synthDC/Makefile index b1452f0e2..b8a79fbdf 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -24,9 +24,19 @@ export SAIFPOWER ?= 0 CONFIGDIR ?= ${WALLY}/pipelined/config CONFIGFILES ?= $(shell find $(CONFIGDIR) -name rv*_*) CONFIGFILESTRIM = $(notdir $(CONFIGFILES)) +# FREQS = 25 50 100 150 200 250 300 350 400 +k = 3 6 + +ifeq ($(TECH), sky130) + FREQS = 25 50 100 150 200 250 300 350 400 +else + FREQS = 500 550 600 650 700 750 800 850 900 950 1000 +endif + print: - echo $(CONFIGFILESTRIM) - echo $(DIRS) + @echo $(FREQS) + @echo $(CONFIGFILESTRIM) + default: @echo "Basic synthesis procedure for Wally:" @@ -39,24 +49,25 @@ rv%.log: rv% echo $< -DIRS = rv32e #rv32gc rv64ic rv64gc rv32ic +DIRS = rv64gc rv32e rv32gc rv64ic rv32ic # DELDIRS = rv32e rv32gc rv64ic rv64gc rv32ic # CONFIGSUBDIRS = _FPUoff _noMulDiv _noVirtMem _PMP0 _PMP16 _orig - +# bpred: +# @$(foreach kval, $(k), rm -rf $(CONFIGDIR)/rv64gc_bpred_$(kval);) +# @$(foreach kval, $(k), cp -r $(CONFIGDIR)/rv64gc $(CONFIGDIR)/rv64gc_bpred_$(kval);) +# @$(foreach kval, $(k), sed -i 's/BPRED_SIZE.*/BPRED_SIZE $(kval)/g' $(CONFIGDIR)/rv64gc_bpred_$(kval)/wally-config.vh;) +# @$(foreach kval, $(k), make synth DESIGN=wallypipelinedcore CONFIG=rv64gc_bpred_$(kval) TECH=sky90 FREQ=500 MAXCORES=4 --jobs;) copy: @$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_orig;) @$(foreach dir, $(DIRS), cp -r $(CONFIGDIR)/$(dir) $(CONFIGDIR)/$(dir)_orig;) @$(foreach dir, $(DIRS), sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;) @$(foreach dir, $(DIRS), sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;) @$(foreach dir, $(DIRS), sed -i "s/RAM_RANGE.*/RAM_RANGE 34\'h01FF/g" $(CONFIGDIR)/$(dir)_orig/wally-config.vh ;) + @$(foreach dir, $(DIRS), sed -i 's/BPRED_SIZE.*/BPRED_SIZE 5/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;) + del: - @$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_orig;) - @$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_FPUoff;) - @$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_PMP16;) - @$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_PMP0;) - @$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_noVirtMem;) - @$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_noMulDiv;) + rm -rf $(CONFIGDIR)/*_* configs: $(DIRS) $(DIRS): @@ -76,23 +87,25 @@ $(DIRS): cp -r $(CONFIGDIR)/$@_FPUoff $(CONFIGDIR)/$@_PMP0 sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/$@_PMP0/wally-config.vh - # No Virtual Memory - rm -rf $(CONFIGDIR)/$@_noVirtMem - cp -r $(CONFIGDIR)/$@_PMP0 $(CONFIGDIR)/$@_noVirtMem - sed -i 's/VIRTMEM_SUPPORTED 1/VIRTMEM_SUPPORTED 0/' $(CONFIGDIR)/$@_noVirtMem/wally-config.vh - #no muldiv rm -rf $(CONFIGDIR)/$@_noMulDiv - cp -r $(CONFIGDIR)/$@_noVirtMem $(CONFIGDIR)/$@_noMulDiv + cp -r $(CONFIGDIR)/$@_PMP0 $(CONFIGDIR)/$@_noMulDiv sed -i 's/1 *<< *12/0 << 12/' $(CONFIGDIR)/$@_noMulDiv/wally-config.vh + #no priv + rm -rf $(CONFIGDIR)/$@_noPriv + cp -r $(CONFIGDIR)/$@_noMulDiv $(CONFIGDIR)/$@_noPriv + sed -i 's/ZICSR_SUPPORTED *1/ZICSR_SUPPORTED 0/' $(CONFIGDIR)/$@_noPriv/wally-config.vh + +freqs: + @$(foreach freq, $(FREQS), make synth DESIGN=wallypipelinedcore CONFIG=rv32e FREQ=$(freq) MAXCORES=1;) allsynth: $(CONFIGFILESTRIM) $(CONFIGFILESTRIM): - make synth DESIGN=wallypipelinedcore CONFIG=$@ TECH=sky90 FREQ=500 MAXCORES=1 + make synth DESIGN=wallypipelinedcore CONFIG=$@ TECH=sky90 FREQ=1000 MAXCORES=1 + - synth: @echo "DC Synthesis" @mkdir -p hdl/ diff --git a/synthDC/hdl/wally-shared.vh b/synthDC/hdl/wally-shared.vh deleted file mode 100644 index 198a4ab2e..000000000 --- a/synthDC/hdl/wally-shared.vh +++ /dev/null @@ -1,99 +0,0 @@ -////////////////////////////////////////// -// wally-shared.vh -// -// Written: david_harris@hmc.edu 7 June 2021 -// -// Purpose: Shared and default configuration values common to all designs -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software -// is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -/////////////////////////////////////////// - -// include shared constants -`include "wally-constants.vh" - -// macros to define supported modes -// NOTE: No hardware support fo Q yet - -`define A_SUPPORTED ((`MISA >> 0) % 2 == 1) -`define C_SUPPORTED ((`MISA >> 2) % 2 == 1) -`define D_SUPPORTED ((`MISA >> 3) % 2 == 1) -`define E_SUPPORTED ((`MISA >> 4) % 2 == 1) -`define F_SUPPORTED ((`MISA >> 5) % 2 == 1) -`define I_SUPPORTED ((`MISA >> 8) % 2 == 1) -`define M_SUPPORTED ((`MISA >> 12) % 2 == 1) -`define Q_SUPPORTED ((`MISA >> 16) % 2 == 1) -`define S_SUPPORTED ((`MISA >> 18) % 2 == 1) -`define U_SUPPORTED ((`MISA >> 20) % 2 == 1) - -// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21 -//`define N_SUPPORTED ((MISA >> 13) % 2 == 1) -`define N_SUPPORTED 0 - - -// logarithm of XLEN, used for number of index bits to select -`define LOG_XLEN (`XLEN == 32 ? 5 : 6) - -// Number of 64 bit PMP Configuration Register entries (or pairs of 32 bit entries) -`define PMPCFG_ENTRIES (`PMP_ENTRIES/8) - - -// Floating-point half-precision -`define ZFH_SUPPORTED 0 - -// Floating point constants for Quad, Double, Single, and Half precisions -`define Q_LEN 128 -`define Q_NE 15 -`define Q_NF 112 -`define Q_BIAS 16383 -`define D_LEN 64 -`define D_NE 11 -`define D_NF 52 -`define D_BIAS 1023 -`define S_LEN 32 -`define S_NE 8 -`define S_NF 23 -`define S_BIAS 127 -`define H_LEN 16 -`define H_NE 5 -`define H_NF 10 -`define H_BIAS 15 - -// Floating point length FLEN and number of exponent (NE) and fraction (NF) bits -`define FLEN (`Q_SUPPORTED ? `Q_LEN : `D_SUPPORTED ? `D_LEN : `F_SUPPORTED ? `S_LEN : `H_LEN) -`define NE (`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `F_SUPPORTED ? `S_NE : `H_NE) -`define NF (`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `F_SUPPORTED ? `S_NF : `H_NF) -`define FMT (`Q_SUPPORTED ? 3 : `D_SUPPORTED ? 1 : `F_SUPPORTED ? 0 : 2) -`define BIAS (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `F_SUPPORTED ? `S_BIAS : `H_BIAS) - -// Floating point constants needed for FPU paramerterization -`define FPSIZES (`Q_SUPPORTED+`D_SUPPORTED+`F_SUPPORTED+`ZFH_SUPPORTED) -`define LEN1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_LEN : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_LEN : `H_LEN) -`define NE1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NE : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NE : `H_NE) -`define NF1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NF : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NF : `H_NF) -`define FMT1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? 1 : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? 0 : 2) -`define BIAS1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_BIAS : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_BIAS : `H_BIAS) -`define LEN2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_LEN : `H_LEN) -`define NE2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NE : `H_NE) -`define NF2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NF : `H_NF) -`define FMT2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? 0 : 2) -`define BIAS2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_BIAS : `H_BIAS) - -// Disable spurious Verilator warnings - -/* verilator lint_off STMTDLY */ -/* verilator lint_off ASSIGNDLY */ -/* verilator lint_off PINCONNECTEMPTY */ diff --git a/synthDC/runConfigsSynth.sh b/synthDC/runConfigsSynth.sh new file mode 100755 index 000000000..40c4b6a8f --- /dev/null +++ b/synthDC/runConfigsSynth.sh @@ -0,0 +1,9 @@ +#!/usr/bin/bash +rm -r runs/* +make clean +make del +make copy +make configs +make allsynth +scripts/extractSummary.py +make del \ No newline at end of file diff --git a/synthDC/runFrequencySynth.sh b/synthDC/runFrequencySynth.sh new file mode 100755 index 000000000..cf603cfd3 --- /dev/null +++ b/synthDC/runFrequencySynth.sh @@ -0,0 +1,7 @@ +#!/usr/bin/bash +rm -r runs/* +make clean +make del +make freqs TECH=$1 +scripts/extractSummary.py +make del diff --git a/synthDC/scripts/extractSummary.py b/synthDC/scripts/extractSummary.py new file mode 100755 index 000000000..c9ec53494 --- /dev/null +++ b/synthDC/scripts/extractSummary.py @@ -0,0 +1,50 @@ +#!/usr/bin/python3 +# Shreya Sanghai (ssanghai@hmc.edu) 2/28/2022 +import glob +import re +import csv +import linecache +import os + + +def main(): + data = [] + curr_dir = os.path.dirname(os.path.abspath(__file__)) + output_file = os.path.join(curr_dir,"..","Summary.csv") + runs_dir = os.path.join(curr_dir,"..","runs/*/reports/wallypipelinedcore_qor.rep") + # cruns_dir = "/home/ssanghai/Desktop/cleanRun/*/reports/wallypipelinedcore_qor.rep" + search_strings = [ + "Critical Path Length:", "Cell Area:", "Overall Compile Time:", + "Critical Path Clk Period:", "Critical Path Slack:" + ] + for name in glob.glob(runs_dir): + f = open(name, 'r') + trimName = re.search("wallypipelinedcore_(.*?)_sky",name).group(1) + + output = {'Name':trimName} + num_lines = len(f.readlines()) + curr_line_index = 0 + + while curr_line_index < num_lines: + line = linecache.getline(name, curr_line_index) + for search_string in search_strings: + if search_string in line: + val = getVal(name,search_string,line,curr_line_index) + output[search_string] = val + curr_line_index +=1 + data += [output] + + with open(output_file, 'w') as csvfile: + writer = csv.DictWriter(csvfile, fieldnames=['Name'] + search_strings) + writer.writeheader() + writer.writerows(data) + +def getVal(filename, search_string, line, line_index): + data = re.search(f"{search_string} *(.*?)\\n", line).group(1) + if data == '': #sometimes data is stored in two line + data = linecache.getline(filename, line_index+1).strip() + return data + +if __name__=="__main__": + main() + \ No newline at end of file diff --git a/tests/fp/run_all.sh b/tests/fp/run_all.sh index 9c45ff2d4..f1ba3625c 100755 --- a/tests/fp/run_all.sh +++ b/tests/fp/run_all.sh @@ -1,5 +1,5 @@ #!/bin/sh +mkdir -p vectors ./create_vectors.sh ./remove_spaces.sh -./append_ctrlSig.sh diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefile b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefile index 095f81ff0..0c60cf417 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefile +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefile @@ -1,5 +1,5 @@ include ../../Makefile.include -RVTEST_DEFINES += -march=rv$(XLEN)ia # KMG: removed compressed instructions from privileged tests +RVTEST_DEFINES += -march=rv$(XLEN)iaf # KMG: removed compressed instructions from privileged tests -$(eval $(call compile_template,-march=rv32iac -mabi=ilp32 -Drvtest_mtrap_routine=True -DXLEN=$(XLEN))) +$(eval $(call compile_template,-march=rv32iaf -mabi=ilp32 -Drvtest_mtrap_routine=True -DXLEN=$(XLEN))) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag index a4da7afc7..3bc4b4e1a 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag @@ -34,12 +34,22 @@ rv32i_sc_tests = \ WALLY-CSR-permission-u-01 \ WALLY-minfo-01 \ WALLY-misa-01 \ - WALLY-scratch-01 \ - WALLY-sscratch-s-01 \ WALLY-AMO \ - WALLY-LRSC + WALLY-LRSC \ + # WALLY-scratch-01 \ + # WALLY-sscratch-s-01 \ -target_tests_nosim = WALLY-PMA \ +target_tests_nosim = \ + WALLY-PMA \ + WALLY-mtvec-01 \ + WALLY-stvec-01 \ + WALLY-MIE-01 \ + WALLY-PIE-stack-01 \ + WALLY-PIE-stack-s-01 \ + WALLY-trap-sret-01 \ + WALLY-trap-01 \ + WALLY-trap-s-01 \ + WALLY-trap-u-01 \ rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests)) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-MIE-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-MIE-01.reference_output new file mode 100644 index 000000000..2a2edbd91 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-MIE-01.reference_output @@ -0,0 +1,1024 @@ +00000000 # test 5.3.1.6: Readback value from zeroing out MIE. # note that none of the attempted interrupts should fire since MIE is zeroed. +0000000b # mcause for ecall from terminating tests in M mode +00000000 # mtval of ecall (*** defined to be zero for now) +00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef 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b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-PIE-stack-01.reference_output new file mode 100644 index 000000000..cf0b9854f --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-PIE-stack-01.reference_output @@ -0,0 +1,1024 @@ +00000aaa # test 5.3.1.6: enabling all of MIE +0007ec03 # value to indicate successful vectoring on m soft interrupt +80000003 # mcause value from m time interrupt +00000000 # mtval for mtime interrupt (0x0) +00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 # Note here that we atempt to cause an interrupt after zeroing status.mie, but it shouldn't fire. +0000000b # mcause for ecall from terminating tests in M mode +00000000 # mtval of ecall (*** defined to be zero for now) +00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0 +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef 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+deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-PIE-stack-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-PIE-stack-s-01.reference_output new file mode 100644 index 000000000..ba197a523 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-PIE-stack-s-01.reference_output @@ -0,0 +1,1012 @@ +00000aaa # test 5.3.1.6: enabling all of MIE +00000222 # writeaback for delegating all interrupts to S mode +0000000b # mcause for ecall from going to S mode from M mode +00000000 # mtval of ecall (*** defined to be zero for now) +00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0 +0007ec01 # value to indicate successful vectoring on s soft interrupt +80000001 # scause value from s soft interrupt +00000000 # stval for ssoft interrupt (0x0) +00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 # Note here that we atempt to cause an interrupt after zeroing status.mie, but it shouldn't fire. +00000009 # mcause for ecall from terminating tests in S mode +00000000 # mtval of ecall (*** defined to be zero for now) +00000800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0 +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef 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+deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-PMA.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-PMA.reference_output index 38042cfc7..a9cdc3633 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-PMA.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-PMA.reference_output @@ -1,10 +1,6 @@ -beef00b5 -00000007 # write access fault with 16 bit write to CLINT -00000005 # read access fault with 16 bit write to CLINT -00000bad -00000007 # write access fault with 8 bit write to CLINT -00000005 # read access fault with 8 bit write to CLINT -00000bad +beef00b5 +000000b6 +ffffffb7 00000001 00000bad 00000002 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-mtvec-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-mtvec-01.reference_output index 4e523b017..8c4f8f6bf 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-mtvec-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-mtvec-01.reference_output @@ -1,11 +1,10 @@ -000000 -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef +00000aaa # Test 5.3.1.5: readback value of SIE after enabling all interrupts. +80000007 # mcause from m time interrupt +00000000 # mtval for mtime interrupt (0x0) +00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 +0000000b # mcause from M mode ecall from test termination +00000000 # mtval of ecall (*** defined to be zero for now) +00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 deadbeef deadbeef deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-scratch-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-scratch-01.reference_output index 1e15db105..fd5eefd64 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-scratch-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-scratch-01.reference_output @@ -1,7 +1,7 @@ 00000111 # Test 5.3.2.3: successful read the 0x111 written to mscratch +00000000 0000000b # ecall from ending tests in machine mode -deadbeef -deadbeef +00000000 deadbeef deadbeef deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-sscratch-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-sscratch-s-01.reference_output index 9a6e9ed32..e44b95848 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-sscratch-s-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-sscratch-s-01.reference_output @@ -1,11 +1,11 @@ 00000111 # Test 5.3.2.3: successful read of the 0x111 written to sscratch +00000000 0000000b # ecall from going to s mode from m mode +00000000 00000aaa # successful read of 0xAAA written to sscratch +00000000 00000009 # ecall from ending tests in supervisor mode -deadbeef -deadbeef -deadbeef -deadbeef +00000000 deadbeef deadbeef deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-stvec-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-stvec-01.reference_output index bc760ed62..fd53d0392 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-stvec-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-stvec-01.reference_output @@ -1,23 +1,23 @@ -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef +00000aaa # Test 5.3.1.5: readback value of MIE after enabling all interrupts. +00000222 # readback value of mideleg after attempting to delegate all interrupts. +0000000b # mcause from ecall for going from M mode to S mode +00000000 # mtval of ecall (*** defined to be zero for now) +00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0 +80000001 # mcause from s soft interrupt +00000000 # mtval for ssoft interrupt (0x0) +00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000009 # mcause from ecall for going from S mode to M mode +00000000 # mtval of ecall (*** defined to be zero for now) +00000800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0 +0000000b # mcause from ecall for going from M mode to U mode +00000000 # mtval of ecall (*** defined to be zero for now) +00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0 +80000001 # mcause from s soft interrupt from user mode this time +00000000 # mtval for mtime interrupt (0x0) +00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000008 # mcause from U mode ecall from test termination +00000000 # mtval of ecall (*** defined to be zero for now) +00000000 # masked out mstatus.MPP = 00, mstatus.MPIE = 0, and mstatus.MIE = 0 deadbeef deadbeef deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output index faac488f3..33a069d6d 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output @@ -1,4 +1,7 @@ -00000aaa # Test 5.3.1.4: readback value from writing mie to enable interrupts +00000aaa # Test 5.3.1.4: readback value from writing mie to enable interrupts +00000000 # mcause from instruction addr misaligned fault +8000013a # mtval of faulting instruction adress +00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000001 # mcause from an instruction access fault 00000000 # mtval of faulting instruction address (0x0) 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 @@ -6,21 +9,21 @@ 00000000 # mtval of faulting instruction (0x0) 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000003 # mcause from Breakpoint -800003ec # mtval of breakpoint instruction adress (0x800003ec) +8000016c # mtval of breakpoint instruction adress 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000004 # mcause from load address misaligned -800003f5 # mtval of misaligned address (0x800003f5) +80000175 # mtval of misaligned address 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000005 # mcause from load access 00000000 # mtval of accessed adress (0x0) 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000006 # mcause from store misaligned -80000411 # mtval of address with misaligned store instr (0x80000410) +80000191 # mtval of address with misaligned store instr 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000007 # mcause from store access 00000000 # mtval of accessed address (0x0) 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 -0000000b # mcause from M mode ecall +0000000b # mcause from M mode ecall 00000000 # mtval of ecall (*** defined to be zero for now) 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000008 # mcause from U mode ecall @@ -29,54 +32,69 @@ 00000009 # mcause from S mode ecall 00000000 # mtval of ecall (*** defined to be zero for now) 00000880 # masked out mstatus.MPP = 01 (from S mode), mstatus.MPIE = 1, and mstatus.MIE = 0 -000007ec # value to indicate a vectored interrupts +0007ec01 # value to indicate successful vectoring on s soft interrupt +80000001 # mcause value from s soft interrupt +00000000 # mtval for ssoft interrupt (0x0) +00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 +0007ec03 # value to indicate successful vectoring on m soft interrupt +80000003 # mcause value from m soft interrupt +00000000 # mtval for msoft interrupt (0x0) +00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 +0007ec05 # value to indicate successful vectoring on s time interrupt +80000005 # mcause value from s time interrupt +00000000 # mtval for stime interrupt (0x0) +00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 +0007ec07 # value to indicate successful vectoring on m time interrupt 80000007 # mcause value from m time interrupt 00000000 # mtval for mtime interrupt (0x0) 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 -000007ec # value to indicate a vectored interrupts -80000001 # mcause value from m soft interrupt -00000000 # mtval for msoft interrupt (0x0) +0007ec09 # value to indicate successful vectoring on s ext interrupt +80000009 # mcause value from s ext interrupt +00000000 # mtval for sext interrupt (0x0) 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 -000007ec # value to indicate a vectored interrupts +0007ec0b # value to indicate successful vectoring on m ext interrupt 8000000b # mcause value from m ext interrupt 00000000 # mtval for mext interrupt (0x0) 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 -0000b309 # medeleg after attempted write of all 1's (only some bits are writeable) +fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable) 00000222 # mideleg after attempted write of all 1's (only some bits are writeable) -00000001 # Test 5.3.1.4: mcause from an instruction access fault +00000000 # mcause from instruction addr misaligned fault +8000013a # mtval of faulting instruction adress +00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 +00000001 # mcause from an instruction access fault 00000000 # mtval of faulting instruction address (0x0) 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000002 # mcause from an Illegal instruction 00000000 # mtval of faulting instruction (0x0) 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000003 # mcause from Breakpoint -800003ec # mtval of breakpoint instruction adress (0x800003ec) +8000016c # mtval of breakpoint instruction adress 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000004 # mcause from load address misaligned -800003f5 # mtval of misaligned address (0x800003f5) +80000175 # mtval of misaligned address 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000005 # mcause from load access 00000000 # mtval of accessed adress (0x0) 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000006 # mcause from store misaligned -80000411 # mtval of address with misaligned store instr (0x80000410) +80000191 # mtval of address with misaligned store instr 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000007 # mcause from store access 00000000 # mtval of accessed address (0x0) 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 -0000000b # mcause from M mode ecall +0000000b # mcause from M mode ecall 00000000 # mtval of ecall (*** defined to be zero for now) 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 -000007ec # value to indicate a vectored interrupts -80000007 # mcause value from time interrupt -00000000 # mtval for mtime interrupt (0x0) -00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 -000007ec # value to indicate a vectored interrupts -80000001 # mcause value from m soft interrupt +0007ec03 # value to indicate successful vectoring on m soft interrupt +80000003 # mcause value from m soft interrupt 00000000 # mtval for msoft interrupt (0x0) 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 -000007ec # value to indicate a vectored interrupts -0000000b # mcause value from m ext interrupt +0007ec07 # value to indicate successful vectoring on m time interrupt +80000007 # mcause value from m time interrupt +00000000 # mtval for mtime interrupt (0x0) +00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 +0007ec0b # value to indicate successful vectoring on m ext interrupt +8000000b # mcause value from m ext interrupt 00000000 # mtval for mext interrupt (0x0) 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 0000000b # mcause from M mode ecall from test termination @@ -988,3 +1006,19 @@ deadbeef deadbeef deadbeef deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output index bc760ed62..724d4e5e8 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output @@ -1,106 +1,106 @@ -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef +00000aaa # readback value from writing mie to enable interrupts +0000000b # Test 5.3.1.4: mcause from ecall going from M mode to S mode +00000000 # mtval of ecall (*** defined to be zero for now) +00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 # scause from instruction addr misaligned fault +8000013a # stval of faulting instruction adress +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000001 # scause from an instruction access fault +00000000 # stval of faulting instruction address (0x0) +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000002 # scause from an Illegal instruction +00000000 # stval of faulting instruction (0x0) +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000003 # scause from Breakpoint +8000016c # stval of breakpoint instruction adress +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000004 # scause from load address misaligned +80000175 # stval of misaligned address +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000005 # scause from load access +00000000 # stval of accessed adress (0x0) +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000006 # scause from store misaligned +80000191 # stval of address with misaligned store instr +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000007 # scause from store access +00000000 # stval of accessed address (0x0) +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000009 # scause from S mode ecall +00000000 # stval of ecall (*** defined to be zero for now) +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000008 # scause from U mode ecall +00000000 # stval of ecall (*** defined to be zero for now) +00000000 # masked out mstatus.mpp = 0 (from U mode), mstatus.MPIE = 0, and mstatus.MIE = 0 +0007ec01 # value to indicate successful vectoring on s soft interrupt +80000001 # scause value from s soft interrupt +00000000 # stval for ssoft interrupt (0x0) +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +0007ec03 # value to indicate successful vectoring on m soft interrupt +80000003 # scause value from m soft interrupt +00000000 # stval for msoft interrupt (0x0) +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +0007ec07 # value to indicate successful vectoring on m time interrupt +80000007 # scause value from m time interrupt +00000000 # stval for mtime interrupt (0x0) +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +0007ec09 # value to indicate successful vectoring on s ext interrupt +80000009 # scause value from s ext interrupt +00000000 # stval for sext interrupt (0x0) +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +0007ec0b # value to indicate successful vectoring on m ext interrupt +8000000b # scause value from m ext interrupt +00000000 # stval for mext interrupt (0x0) +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000009 # scause from S mode ecall +00000000 # stval of ecall (*** defined to be zero for now) +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable) +00000222 # mideleg after attempted write of all 1's (only some bits are writeable) +0000000b # scause from M mode ecall +00000000 # stval of ecall (*** defined to be zero for now) +00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 # scause from instruction addr misaligned fault +8000013a # stval of faulting instruction adress +00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000001 # scause from an instruction access fault +00000000 # stval of faulting instruction address (0x0) +00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000002 # scause from an Illegal instruction +00000000 # stval of faulting instruction (0x0) +00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000003 # scause from Breakpoint +8000016c # stval of breakpoint instruction adress +00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000004 # scause from load address misaligned +80000175 # stval of misaligned address +00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000005 # scause from load access +00000000 # stval of accessed adress (0x0) +00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000006 # scause from store misaligned +80000191 # stval of address with misaligned store instr +00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000007 # scause from store access +00000000 # stval of accessed address (0x0) +00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000009 # scause from S mode ecall +00000000 # stval of ecall (*** defined to be zero for now) +00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000008 # scause from U mode ecall +00000000 # stval of ecall (*** defined to be zero for now) +00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 +0007ec01 # value to indicate successful vectoring on s soft interrupt +80000001 # scause value from s soft interrupt +00000000 # stval for ssoft interrupt (0x0) +00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 +0007ec09 # value to indicate successful vectoring on s ext interrupt +80000009 # scause value from s ext interrupt +00000000 # stval for sext interrupt (0x0) +00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000009 # scause from S mode ecall from test termination +00000000 # stval of ecall (*** defined to be zero for now) +00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 deadbeef deadbeef deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-sret-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-sret-01.reference_output new file mode 100644 index 000000000..7d62f0bb9 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-sret-01.reference_output @@ -0,0 +1,1024 @@ +0000000b # test 5.3.1.6: mcause for ecall from going to S mode from M mode +00000000 # mtval of ecall (*** defined to be zero for now) +00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000002 # mcause for illegal sret instruction due to status.tsr bit being set. +10200073 # mtval of illegal instruction (illegal instruction's machine code) +00000800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0 +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef 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+deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output index bc760ed62..7670852ea 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output @@ -1,92 +1,92 @@ -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef +00000aaa # readback value from writing mie to enable interrupts +0000000b # Test 5.3.1.4: mcause from ecall going from M mode to U mode +00000000 # mtval of ecall (*** defined to be zero for now) +00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 # scause from instruction addr misaligned fault +8000013a # stval of faulting instruction adress +00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000001 # scause from an instruction access fault +00000000 # stval of faulting instruction address (0x0) +00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000002 # scause from an Illegal instruction +00000000 # stval of faulting instruction (0x0) +00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000003 # scause from Breakpoint +8000016c # stval of breakpoint instruction adress +00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000004 # scause from load address misaligned +80000175 # stval of misaligned address +00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000005 # scause from load access +00000000 # stval of accessed adress (0x0) +00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000006 # scause from store misaligned +80000191 # stval of address with misaligned store instr +00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000007 # scause from store access +00000000 # stval of accessed address (0x0) +00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000008 # scause from U mode ecall +00000000 # stval of ecall (*** defined to be zero for now) +00000000 # masked out mstatus.mpp = 0 (from U mode), mstatus.MPIE = 0, and mstatus.MIE = 0 +0007ec03 # value to indicate successful vectoring on m soft interrupt +80000003 # scause value from m soft interrupt +00000000 # stval for msoft interrupt (0x0) +00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 +0007ec07 # value to indicate successful vectoring on m time interrupt +80000007 # scause value from m time interrupt +00000000 # stval for mtime interrupt (0x0) +00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 +0007ec09 # value to indicate successful vectoring on s ext interrupt +80000009 # scause value from s ext interrupt +00000000 # stval for sext interrupt (0x0) +00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 +0007ec0b # value to indicate successful vectoring on m ext interrupt +8000000b # scause value from m ext interrupt +00000000 # stval for mext interrupt (0x0) +00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000008 # scause from U mode ecall +00000000 # stval of ecall (*** defined to be zero for now) +00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 +fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable) +00000222 # mideleg after attempted write of all 1's (only some bits are writeable) +0000000b # scause from M mode ecall +00000000 # stval of ecall (*** defined to be zero for now) +00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 # scause from instruction addr misaligned fault +8000013a # stval of faulting instruction adress +00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000001 # scause from an instruction access fault +00000000 # stval of faulting instruction address (0x0) +00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000002 # scause from an Illegal instruction +00000000 # stval of faulting instruction (0x0) +00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000003 # scause from Breakpoint +8000016c # stval of breakpoint instruction adress +00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000004 # scause from load address misaligned +80000175 # stval of misaligned address +00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000005 # scause from load access +00000000 # stval of accessed adress (0x0) +00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000006 # scause from store misaligned +80000191 # stval of address with misaligned store instr +00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000007 # scause from store access +00000000 # stval of accessed address (0x0) +00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000008 # scause from U mode ecall +00000000 # stval of ecall (*** defined to be zero for now) +00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 +0007ec09 # value to indicate successful vectoring on s ext interrupt +80000009 # scause value from s ext interrupt +00000000 # stval for sext interrupt (0x0) +00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000008 # scause from U mode ecall from test termination +00000000 # stval of ecall (*** defined to be zero for now) +00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 deadbeef deadbeef deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-MIE-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-MIE-01.S new file mode 100644 index 000000000..88555e3de --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-MIE-01.S @@ -0,0 +1,53 @@ +/////////////////////////////////////////// +// +// WALLY-MIE +// +// Author: Kip Macsai-Goren +// +// Created 2022-04-10 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-LIB-32.h" + +INIT_TESTS + +CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses + +TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps + +li x28, 0x8 +csrs mstatus, x28 // set mstatus.MIE bit to 1. +WRITE_READ_CSR mie, 0x0 // force zeroing out mie CSR. + +// test 5.3.1.6 Interrupt enabling and priority tests +// testing with MIE bits set already tested in WALLY-trap +// note that none of these interrupts should be caught or handled. + +jal cause_s_soft_interrupt +jal cause_m_soft_interrupt +jal cause_s_time_interrupt +jal cause_m_time_interrupt +li a3, 0x40 // these interrupts involve a time loop waiting for the interrupt to go off. +// since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3 +jal cause_s_ext_interrupt_GPIO +li a3, 0x40 +jal cause_m_ext_interrupt + +END_TESTS + +TEST_STACK_AND_DATA + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PIE-stack-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PIE-stack-01.S new file mode 100644 index 000000000..d5a46e753 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PIE-stack-01.S @@ -0,0 +1,49 @@ +/////////////////////////////////////////// +// +// WALLY-privilege-interrupt-enable-stack +// +// Author: Kip Macsai-Goren +// +// Created 2022-04-10 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-LIB-32.h" + +INIT_TESTS + +CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses + +TRAP_HANDLER m, DEBUG=1 + +li x28, 0x8 +csrs mstatus, x28 // set mstatus.MIE bit to 1 +WRITE_READ_CSR mie, 0xFFF + +// test 5.3.1.6 Interrupt enabling and priority tests + +// Cause interrupt, ensuring that status.mie = 0 , status.mpie = 1, and status.mpp = 11 during trap handling +jal cause_m_soft_interrupt // *** only cause one interrupt because we just want to test the status stack + +li x28, 0x8 +csrc mstatus, x28 // set mstatus.MIE bit to 0. interrupts from M mode should not happen + +// attempt to cause interrupt, it should not go through +jal cause_m_soft_interrupt + +END_TESTS + +TEST_STACK_AND_DATA diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PIE-stack-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PIE-stack-s-01.S new file mode 100644 index 000000000..0f23e8291 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PIE-stack-s-01.S @@ -0,0 +1,53 @@ +/////////////////////////////////////////// +// +// WALLY-privilege-interrupt-enable-stack +// +// Author: Kip Macsai-Goren +// +// Created 2022-04-10 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-LIB-32.h" + +INIT_TESTS + +CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses + +TRAP_HANDLER m, DEBUG=1 // necessary so we can go to S mode +TRAP_HANDLER s, DEBUG=1 // neccessary to handle s mode interrupts. + +li x28, 0x2 +csrs sstatus, x28 // set sstatus.SIE bit to 1 +WRITE_READ_CSR mie, 0xFFF // enable all interrupts, including supervisor ones +WRITE_READ_CSR mideleg 0xFFFF // delegate all interrupts to S mode. + +// test 5.3.1.6 Interrupt enabling and priority tests + +GOTO_S_MODE + +// Cause interrupt, ensuring that status.sie = 0 , status.spie = 1, and status.spp = 1 during trap handling +jal cause_s_soft_interrupt // *** only cause one interrupt because we just want to test the status stack + +li x28, 0x2 +csrc sstatus, x28 // set sstatus.SIE bit to 0. interrupts from S mode should not happen + +// attempt to cause interrupt, it should not go through +jal cause_s_soft_interrupt + +END_TESTS + +TEST_STACK_AND_DATA diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMA.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMA.S index 98d5e0134..1462ff800 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMA.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMA.S @@ -81,14 +81,14 @@ test_cases: # ----------------- CLINT --------------------- # Use timecmp register as readable and writable section of the CLINT -.4byte CLINT_BASE + 0x4000, 0xBEEF00B5, write32_test # 32-bit write: success -.4byte CLINT_BASE + 0x4000, 0xBEEF00B5, read32_test # 32-bit read: success -.4byte CLINT_BASE + 0x4000, 0xBEEF00B6, write16_test# 16-bit write: failure *** Due to non-native access length in CLINT -.4byte CLINT_BASE + 0x4000, 0xBEEF00B6, read16_test# 16-bit read: failure -.4byte CLINT_BASE + 0x4000, 0xBEEF00B7, write08_test# 08-bit write: failure -.4byte CLINT_BASE + 0x4000, 0xBEEF00B7, read08_test# 08-bit read: failure +.4byte CLINT_BASE + 0x4000, 0xBEEF00B5, write32_test # 32-bit write: success +.4byte CLINT_BASE + 0x4000, 0xBEEF00B5, read32_test # 32-bit read: success +.4byte CLINT_BASE + 0x4000, 0xBEEF00B6, write16_test # 16-bit write: success +.4byte CLINT_BASE + 0x4000, 0xBEEF00B6, read16_test # 16-bit read: success +.4byte CLINT_BASE + 0x4000, 0xBEEF00B7, write08_test # 08-bit write: success +.4byte CLINT_BASE + 0x4000, 0xBEEF00B7, read08_test # 08-bit read: success -.4byte CLINT_BASE, 0xbad, executable_test# execute: instruction access fault +.4byte CLINT_BASE, 0xbad, executable_test # execute: instruction access fault # ----------------- PLIC --------------------- diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h index 2400173b9..e5fe13043 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h @@ -39,8 +39,7 @@ RVTEST_CODE_BEGIN // // Initialize x6 as a virtual pointer to the test results // Initialize x16 as a physical pointer to the test results - // Set up stack pointer (sp = x2) - // Set up the exception Handler, keeping the original handler in x4. + // Set up stack pointer, mscratch, sscratch // // --------------------------------------------------------------------------------------------- @@ -49,8 +48,12 @@ RVTEST_CODE_BEGIN la x16, test_1_res // x16 reserved for the physical address equivalent of x6 to be used in trap handlers // any time either is used, both must be updated. - // address for stack - la sp, top_of_stack + // address for normal user stack, mscratch stack, and sscratch stack + la sp, mscratch_top + csrw mscratch, sp + la sp, sscratch_top + csrw sscratch, sp + la sp, stack_top .endm @@ -61,11 +64,13 @@ j end_trap_triggers // The following tests involve causing many of the interrupts and exceptions that are easily done in a few lines // This effectively includes everything that isn't to do with page faults (virtual memory) - +// +// INPUTS: a3 (x13): the number of times one of the infinitely looping interrupt causes should loop before giving up and continuing without the interrupt firing. +// cause_instr_addr_misaligned: // cause a misaligned address trap auipc x28, 0 // get current PC, which is aligned - addi x28, x28, 0x3 // add 1 to pc to create misaligned address + addi x28, x28, 0x2 // add 2 to pc to create misaligned address (Assumes compressed instructions are disabled) jr x28 // cause instruction address midaligned trap ret @@ -79,10 +84,10 @@ cause_instr_access: ret cause_illegal_instr: - .word 0x00000000 // a 32 bit zros is an illegal instruction + .word 0x00000000 // 32 bit zero is an illegal instruction ret -cause_breakpnt: // **** +cause_breakpnt: ebreak ret @@ -113,10 +118,11 @@ cause_ecall: ecall ret -cause_time_interrupt: +cause_m_time_interrupt: // The following code works for both RV32 and RV64. // RV64 alone would be easier using double-word adds and stores li x28, 0x30 // Desired offset from the present time + mv a3, x28 // copy value in to know to stop waiting for interrupt after this many cycles la x29, 0x02004000 // MTIMECMP register in CLINT la x30, 0x0200BFF8 // MTIME register in CLINT lw x7, 0(x30) // low word of MTIME @@ -127,21 +133,101 @@ cause_time_interrupt: sw x31,4(x29) // store into most significant word of MTIMECMP nowrap: sw x28, 0(x29) // store into least significant word of MTIMECMP - loop: j loop // wait until interrupt occurs +time_loop: + //wfi // *** this may now spin us forever in the loop??? + addi a3, a3, -1 + bnez a3, time_loop // go through this loop for [a3 value] iterations before returning without performing interrupt ret -cause_soft_interrupt: +cause_s_time_interrupt: + li x28, 0x20 + csrs mip, x28 // set supervisor time interrupt pending. SIP is a subset of MIP, so writing this should also change MIP. + nop // added extra nops in so the csrs can get through the pipeline before returning. + ret + +cause_m_soft_interrupt: la x28, 0x02000000 // MSIP register in CLINT li x29, 1 // 1 in the lsb sw x29, 0(x28) // Write MSIP bit ret -cause_ext_interrupt: +cause_s_soft_interrupt: + li x28, 0x2 + csrs sip, x28 // set supervisor software interrupt pending. SIP is a subset of MIP, so writing this should also change MIP. + ret + +cause_m_ext_interrupt: + # ========== Configure PLIC ========== + # m priority threshold = 0 + li x28, 0xC200000 + li x29, 0 + sw x29, 0(x28) + # s priority threshold = 7 + li x28, 0xC201000 + li x29, 7 + sw x29, 0(x28) + # source 3 (GPIO) priority = 1 + li x28, 0xC000000 + li x29, 1 + sw x29, 0x0C(x28) + # enable source 3 in M Mode + li x28, 0x0C002000 + li x29, 0b1000 + sw x29, 0(x28) + li x28, 0x10060000 // load base GPIO memory location li x29, 0x1 - sw x29, 8(x28) // enable the first pin as an output - sw x29, 28(x28) // set first pin to high interrupt enable - sw x29, 40(x28) // write a 1 to the first output pin (cause interrupt) + sw x29, 0x08(x28) // enable the first pin as an output + sw x29, 0x04(x28) // enable the first pin as an input as well to cause the interrupt to fire + + sw x0, 0x1C(x28) // clear rise_ip + sw x0, 0x24(x28) // clear fall_ip + sw x0, 0x2C(x28) // clear high_ip + sw x0, 0x34(x28) // clear low_ip + + sw x29, 0x28(x28) // set first pin to interrupt on a rising value + sw x29, 0x0C(x28) // write a 1 to the first output pin (cause interrupt) +m_ext_loop: + //wfi + addi a3, a3, -1 + bnez a3, m_ext_loop // go through this loop for [a3 value] iterations before returning without performing interrupt + ret + +cause_s_ext_interrupt_GPIO: + # ========== Configure PLIC ========== + # s priority threshold = 0 + li x28, 0xC201000 + li x29, 0 + sw x29, 0(x28) + # m priority threshold = 7 + li x28, 0xC200000 + li x29, 7 + sw x29, 0(x28) + # source 3 (GPIO) priority = 1 + li x28, 0xC000000 + li x29, 1 + sw x29, 0x0C(x28) + # enable source 3 in S mode + li x28, 0x0C002080 + li x29, 0b1000 + sw x29, 0(x28) + + li x28, 0x10060000 // load base GPIO memory location + li x29, 0x1 + sw x29, 0x08(x28) // enable the first pin as an output + sw x29, 0x04(x28) // enable the first pin as an input as well to cause the interrupt to fire + + sw x0, 0x1C(x28) // clear rise_ip + sw x0, 0x24(x28) // clear fall_ip + sw x0, 0x2C(x28) // clear high_ip + sw x0, 0x34(x28) // clear low_ip + + sw x29, 0x28(x28) // set first pin to interrupt on a rising value + sw x29, 0x0C(x28) // write a 1 to the first output pin (cause interrupt) +s_ext_loop: + //wfi + addi a3, a3, -1 + bnez a3, s_ext_loop // go through this loop for [a3 value] iterations before returning without performing interrupt ret end_trap_triggers: @@ -149,7 +235,7 @@ end_trap_triggers: .macro TRAP_HANDLER MODE, VECTORED=1, DEBUG=0 // MODE decides which mode this trap handler will be taken in (M or S mode) - // Vectored decides whether interrumpts are handled with the vector table at trap_handler_MODE (1) + // Vectored decides whether interrupts are handled with the vector table at trap_handler_MODE (1) // vs Using the non-vector approach the rest of the trap handler takes (0) // DEBUG decides whether we will print mtval a string with status.mpie, status.mie, and status.mpp to the signature (1) // vs not saving that info to the signature (0) @@ -214,24 +300,28 @@ trap_handler_\MODE\(): // *** ASSUMES that a cause value of 0 for an interrupt is unimplemented // otherwise, a vectored interrupt handler should jump to trap_handler_\MODE\() + 4 * Interrupt cause code // No matter the value of VECTORED, exceptions (not interrupts) are handled in an unvecotred way - j soft_interrupt_\MODE\() // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table. + j s_soft_vector_\MODE\() // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table. j segfault_\MODE\() // 2: reserved - j soft_interrupt_\MODE\() // 3: breakpoint + j m_soft_vector_\MODE\() // 3: breakpoint j segfault_\MODE\() // 4: reserved - j time_interrupt_\MODE\() // 5: load access fault + j s_time_vector_\MODE\() // 5: load access fault j segfault_\MODE\() // 6: reserved - j time_interrupt_\MODE\() // 7: store access fault + j m_time_vector_\MODE\() // 7: store access fault j segfault_\MODE\() // 8: reserved - j ext_interrupt_\MODE\() // 9: ecall from S-mode + j s_ext_vector_\MODE\() // 9: ecall from S-mode j segfault_\MODE\() // 10: reserved - j ext_interrupt_\MODE\() // 11: ecall from M-mode + j m_ext_vector_\MODE\() // 11: ecall from M-mode // 12 through >=16 are reserved or designated for platform use trap_unvectored_\MODE\(): - // The processor is always in machine mode when a trap takes us here + csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself. + // *** NOTE: this means that nested traps will be screwed up but they shouldn't happen in any of these tests + +trap_stack_saved_\MODE\(): // jump here after handling vectored interupt since we already switch sp and scratch there // save registers on stack before using sw x1, -4(sp) - sw x5, -8(sp) + sw x5, -8(sp) + sw x7, -12(sp) // Record trap csrr x1, \MODE\()cause // record the mcause @@ -261,49 +351,36 @@ trap_unvectored_\MODE\(): // Respond to trap based on cause // All interrupts should return after being logged csrr x1, \MODE\()cause - li x5, 0x8000000000000000 // if msb is set, it is an interrupt + li x5, 0x80000000 // if msb is set, it is an interrupt and x5, x5, x1 - bnez x5, trapreturn_\MODE\() // return from interrupt + bnez x5, interrupt_handler_\MODE\() // Other trap handling is specified in the vector Table - slli x1, x1, 2 // multiply cause by 4 to get offset in vector Table la x5, exception_vector_table_\MODE\() + slli x1, x1, 2 // multiply cause by 4 to get offset in vector Table add x5, x5, x1 // compute address of vector in Table lw x5, 0(x5) // fectch address of handler from vector Table jr x5 // and jump to the handler - + +interrupt_handler_\MODE\(): + la x5, interrupt_vector_table_\MODE\() // NOTE THIS IS NOT THE SAME AS VECTORED INTERRUPTS!!! + slli x1, x1, 2 // multiply cause by 4 to get offset in vector Table + add x5, x5, x1 // compute address of vector in Table + lw x5, 0(x5) // fectch address of handler from vector Table + jr x5 // and jump to the handler + segfault_\MODE\(): - lw x5, -8(sp) // restore registers from stack before faulting + lw x7, -12(sp) // restore registers from stack before faulting + lw x5, -8(sp) lw x1, -4(sp) j terminate_test // halt program. trapreturn_\MODE\(): - // look at the instruction to figure out whether to add 2 or 4 bytes to PC, or go to address specified in a1 csrr x1, \MODE\()epc // get the mepc - addi x1, x1, 4 // *** should be 2 for compressed instructions, see note. - - -// ****** KMG: the following is no longer as easy to determine. mepc gets the virtual address of the trapped instruction, -// ******** but in the handler, we work in M mode with physical addresses -// This means the address in mepc is suddenly pointing somewhere else. -// to get this to work, We could either retranslate the vaddr back into a paddr (probably on the scale of difficult to intractible) -// or we could come up with some other ingenious way to stay in M mode and see if the instruction was compressed. - -// lw x5, 0(x1) // read the faulting instruction -// li x1, 3 // check bottom 2 bits of instruction to see if compressed -// and x5, x5, x1 // mask the other bits -// beq x5, x1, trapreturn_uncompressed // if 11, the instruction is return_uncompressed - -// trapreturn_compressed: -// csrr x1, mepc // get the mepc again -// addi x1, x1, 2 // add 2 to find the next instruction -// j trapreturn_specified // and return - -// trapreturn_uncompressed: -// csrr x1, mepc // get the mepc again -// addi x1, x1, 4 // add 4 to find the next instruction + addi x1, x1, 4 trapreturn_specified_\MODE\(): // reset the necessary pointers and registers (x1, x5, x6, and the return address going to mepc) + // note that we don't need to change x7 since it was a temporary register with no important address in it. // so that when we return to a new virtual address, they're all in the right spot as well. beqz a1, trapreturn_finished_\MODE\() // either update values, of go to default return address. @@ -333,7 +410,7 @@ trapreturn_specified_\MODE\(): and x7, x5, x6 // x7 = offset for x6 add x6, x7, a1 // x6 = new address for the result pointer - // set return address, stored temporarily in x1, to the next instruction, but in the new virtual page. + // reset x1, which temporarily holds the return address that will be written to mepc. and x1, x5, x1 // x1 = offset for the return address add x1, x1, a1 // x1 = new return address. @@ -342,13 +419,16 @@ trapreturn_specified_\MODE\(): trapreturn_finished_\MODE\(): csrw \MODE\()epc, x1 // update the mepc with address of next instruction - lw x5, -8(sp) // restore registers from stack before returning + lw x7, -12(sp) // restore registers from stack before returning + lw x5, -8(sp) lw x1, -4(sp) + csrrw sp, \MODE\()scratch, sp // switch sp and scratch stack back to restore the non-trap stack pointer \MODE\()ret // return from trap +// specific exception handlers + ecallhandler_\MODE\(): // Check input parameter a0. encoding above. - // *** ASSUMES: that this trap is being handled in machine mode. in other words, that nothing odd has been written to the medeleg or mideleg csrs. li x5, 2 // case 2: change to machine mode beq a0, x5, ecallhandler_changetomachinemode_\MODE\() li x5, 3 // case 3: change to supervisor mode @@ -359,22 +439,23 @@ ecallhandler_\MODE\(): j segfault_\MODE\() ecallhandler_changetomachinemode_\MODE\(): - // Force mstatus.MPP (bits 12:11) to 11 to enter machine mode after mret + // Force status.MPP (bits 12:11) to 11 to enter machine mode after mret + // note that it is impossible to return to M mode after a trap delegated to S mode li x1, 0b1100000000000 csrs \MODE\()status, x1 - j trapreturn_\MODE\() + j trapreturn_\MODE\() ecallhandler_changetosupervisormode_\MODE\(): - // Force mstatus.MPP (bits 12:11) to 01 to enter supervisor mode after mret - li x1, 0b1100000000000 + // Force status.MPP (bits 12:11) and status.SPP (bit 8) to 01 to enter supervisor mode after (m/s)ret + li x1, 0b1000000000000 csrc \MODE\()status, x1 - li x1, 0b0100000000000 + li x1, 0b0100100000000 csrs \MODE\()status, x1 j trapreturn_\MODE\() ecallhandler_changetousermode_\MODE\(): - // Force mstatus.MPP (bits 12:11) to 00 to enter user mode after mret - li x1, 0b1100000000000 + // Force status.MPP (bits 12:11) and status.SPP (bit 8) to 00 to enter user mode after (m/s)ret + li x1, 0b1100100000000 csrc \MODE\()status, x1 j trapreturn_\MODE\() @@ -390,7 +471,6 @@ illegalinstr_\MODE\(): j trapreturn_\MODE\() // return to the code after recording the mcause accessfault_\MODE\(): - // *** What do I have to do here? j trapreturn_\MODE\() addr_misaligned_\MODE\(): @@ -399,34 +479,107 @@ addr_misaligned_\MODE\(): breakpt_\MODE\(): j trapreturn_\MODE\() -soft_interrupt_\MODE\(): - li x5, 0x7EC // write 0x7EC (looks like VEC) to the output before the mcause and extras to indicate that this trap was handled with a vector table. - sw x5, 0(x16) +// Vectored interrupt handlers: record the fact that the handler went to the correct vector and then continue to handling +// note: does not mess up any registers, saves and restores them to the stack instead. + +s_soft_vector_\MODE\(): + csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself. + sw x5, -4(sp) // put x5 on the scratch stack before messing with it + li x5, 0x7EC01 // write 0x7ec01 (for "VEC"tored and 01 for the interrupt code) + j vectored_int_end_\MODE\() + +m_soft_vector_\MODE\(): + csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself. + sw x5, -4(sp) // put x5 on the scratch stack before messing with it + li x5, 0x7EC03 // write 0x7ec03 (for "VEC"tored and 03 for the interrupt code) + j vectored_int_end_\MODE\() + +s_time_vector_\MODE\(): + csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself. + sw x5, -4(sp) // put x5 on the scratch stack before messing with it + li x5, 0x7EC05 // write 0x7ec05 (for "VEC"tored and 05 for the interrupt code) + j vectored_int_end_\MODE\() + +m_time_vector_\MODE\(): + csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself. + sw x5, -4(sp) // put x5 on the scratch stack before messing with it + li x5, 0x7EC07 // write 0x7ec07 (for "VEC"tored and 07 for the interrupt code) + j vectored_int_end_\MODE\() + +s_ext_vector_\MODE\(): + csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself. + sw x5, -4(sp) // put x5 on the scratch stack before messing with it + li x5, 0x7EC09 // write 0x7ec09 (for "VEC"tored and 08 for the interrupt code) + j vectored_int_end_\MODE\() + +m_ext_vector_\MODE\(): + csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself. + sw x5, -4(sp) // put x5 on the scratch stack before messing with it + li x5, 0x7EC0B // write 0x7ec0B (for "VEC"tored and 0B for the interrupt code) + j vectored_int_end_\MODE\() + +vectored_int_end_\MODE\(): + sw x5, 0(x16) // store to signature to show vectored interrupts succeeded. addi x6, x6, 4 addi x16, x16, 4 - la x28, 0x02000000 // Reset by clearing MSIP interrupt from CLINT - sw x0, 0(x28) - j trap_unvectored_\MODE\() + lw x5, -4(sp) // restore x5 before continuing to handle trap in case its needed. + j trap_stack_saved_\MODE\() + +// specific interrupt handlers + +soft_interrupt_\MODE\(): + la x5, 0x02000000 // Reset by clearing MSIP interrupt from CLINT + sw x0, 0(x5) + + csrci \MODE\()ip, 0x2 // clear supervisor software interrupt pending bit + lw x1, -4(sp) // load return address from stack into ra (the address to return to after causing this interrupt) + // Note: we do this because the mepc loads in the address of the instruction after the sw that causes the interrupt + // This means that this trap handler will return to the next address after that one, which might be unpredictable behavior. + j trapreturn_finished_\MODE\() // return to the code at ra value from before trap time_interrupt_\MODE\(): - li x5, 0x7EC - sw x5, 0(x16) - addi x6, x6, 4 - addi x16, x16, 4 - la x29, 0x02004000 // MTIMECMP register in CLINT - li x30, 0xFFFFFFFF - sw x30, 0(x29) // reset interrupt by setting mtimecmp to 0xFFFFFFFF - j trap_unvectored_\MODE\() + la x5, 0x02004000 // MTIMECMP register in CLINT + li x7, 0xFFFFFFFF + sw x7, 0(x5) // reset interrupt by setting mtimecmp to 0xFFFFFFFF + + li x5, 0x20 + csrc \MODE\()ip, x5 + lw x1, -4(sp) // load return address from stack into ra (the address to return to after the loop is complete) + j trapreturn_finished_\MODE\() // return to the code at ra value from before trap ext_interrupt_\MODE\(): - li x5, 0x7EC - sw x5, 0(x16) - addi x6, x6, 4 - addi x16, x16, 4 li x28, 0x10060000 // reset interrupt by clearing all the GPIO bits sw x0, 8(x28) // disable the first pin as an output sw x0, 40(x28) // write a 0 to the first output pin (reset interrupt) - j trap_unvectored_\MODE\() + + # reset PLIC to turn off external interrupts + # m priority threshold = 7 + li x28, 0xC200000 + li x5, 0x7 + sw x5, 0(x28) + # s priority threshold = 7 + li x28, 0xC201000 + li x5, 0x7 + sw x5, 0(x28) + # source 3 (GPIO) priority = 0 + li x28, 0xC000000 + li x5, 0 + sw x5, 0x0C(x28) + # disable source 3 in M mode + li x28, 0x0C002000 + li x5, 0b0000 + sw x5, 0(x28) + # enable source 3 in S mode + li x28, 0x0C002080 + li x29, 0b0000 + sw x29, 0(x28) + + li x5, 0x200 + csrc \MODE\()ip, x5 + + lw x1, -4(sp) // load return address from stack into ra (the address to return to after the loop is complete) + j trapreturn_finished_\MODE\() // return to the code at ra value from before trap + // Table of trap behavior // lists what to do on each exception (not interrupts) @@ -452,6 +605,22 @@ exception_vector_table_\MODE\(): .4byte segfault_\MODE\() // 14: reserved .4byte trapreturn_\MODE\() // 15: store page fault + .align 2 // aligns this data table to an 4 byte boundary +interrupt_vector_table_\MODE\(): + .4byte segfault_\MODE\() // 0: reserved + .4byte soft_interrupt_\MODE\() // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table. + .4byte segfault_\MODE\() // 2: reserved + .4byte soft_interrupt_\MODE\() // 3: breakpoint + .4byte segfault_\MODE\() // 4: reserved + .4byte time_interrupt_\MODE\() // 5: load access fault + .4byte segfault_\MODE\() // 6: reserved + .4byte time_interrupt_\MODE\() // 7: store access fault + .4byte segfault_\MODE\() // 8: reserved + .4byte ext_interrupt_\MODE\() // 9: ecall from S-mode + .4byte segfault_\MODE\() // 10: reserved + .4byte ext_interrupt_\MODE\() // 11: ecall from M-mode + + .align 2 trap_return_pagetype_table_\MODE\(): .4byte 0xC // 0: kilopage has 12 offset bits @@ -589,7 +758,8 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a // Turn translation off li x7, 0 // satp.MODE value for bare metal (0) slli x7, x7, 31 - sfence.vma x0, x0 // *** flushes global pte's as well + csrw satp, x7 + //sfence.vma x0, x0 // *** flushes global pte's as well .endm .macro GOTO_SV32 ASID BASE_PPN @@ -602,7 +772,7 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a li x28, \BASE_PPN // Base Pagetable physical page number, satp.PPN field. add x7, x7, x28 csrw satp, x7 - sfence.vma x0, x0 // *** flushes global pte's as well + //sfence.vma x0, x0 // *** flushes global pte's as well .endm .macro WRITE_READ_CSR CSR VAL @@ -996,9 +1166,19 @@ rvtest_data: RVTEST_DATA_END .align 2 // align stack to 4 byte boundary -bottom_of_stack: +stack_bottom: .fill 1024, 4, 0xdeadbeef -top_of_stack: +stack_top: + +.align 2 +mscratch_bottom: + .fill 512, 4, 0xdeadbeef +mscratch_top: + +.align 2 +sscratch_bottom: + .fill 512, 4, 0xdeadbeef +sscratch_top: RVMODEL_DATA_BEGIN diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mtvec-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mtvec-01.S index 3930d227e..cbc87d196 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mtvec-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mtvec-01.S @@ -21,24 +21,23 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -#include "WALLY-TEST-LIB-64.h" +#include "WALLY-TEST-LIB-32.h" INIT_TESTS +CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses + // test 5.3.1.5 Unvectored interrupt tests TRAP_HANDLER m, VECTORED=0, DEBUG=1 // turn off vectored interrupts, while turning on recording of mstatus bits. li x28, 0x8 -csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode -WRITE_READ_CSR mie, 0xFFF // *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts +csrs mstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode +WRITE_READ_CSR mie, 0xFFF // cause traps, ensuring that we DONT go through the vectored part of the trap handler -// *** this assumes that interrupt code 0 remains reserved -CAUSE_TIME_INTERRUPT // *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. -CAUSE_SOFT_INTERRUPT // *** exiting out of the trap handler after these is current;y broken -CAUSE_EXT_INTERRUPT +jal cause_m_time_interrupt // *** only cause one interrupt because we just want to test the status stack END_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-scratch-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-scratch-01.S index 3f8d5cc94..686bbacc3 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-scratch-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-scratch-01.S @@ -26,7 +26,6 @@ INIT_TESTS TRAP_HANDLER m - // Test 5.3.2.3: Scratch registers test WRITE_READ_CSR mscratch, 0x111 // check that mscratch is readable and writeable in machine mode diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-stvec-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-stvec-01.S index 688c78910..febd69d23 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-stvec-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-stvec-01.S @@ -21,34 +21,33 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -#include "WALLY-TEST-LIB-64.h" +#include "WALLY-TEST-LIB-32.h" INIT_TESTS +CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses + // test 5.3.1.5 Unvectored interrupt tests +TRAP_HANDLER m, VECTORED=0, DEBUG=1 // necessary to handle changing modes TRAP_HANDLER s, VECTORED=0, DEBUG=1 // turn off vectored interrupts, while turning on recording of mstatus bits. -// li x28, 0x8 -// csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode -// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts - +li x28, 0x2 +csrs sstatus, x28 // set sstatus.SIE bit to 1 +WRITE_READ_CSR mie, 0xFFFF WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF +// cause traps, ensuring that we DONT go through the vectored part of the trap handler + GOTO_S_MODE -// cause traps, ensuring that we DONT go through the vectored part of the trap handler -// *** this assumes that interrupt code 0 remains reserved +jal cause_s_soft_interrupt // *** only cause one interrupt since we just want to test the tvec csr -// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. -// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken -// CAUSE_EXT_INTERRUPT +GOTO_M_MODE -GOTO_U_MODE +jal cause_s_soft_interrupt // set software interrupt pending without it firing so we can make it fire in U mode -// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. -// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken -// CAUSE_EXT_INTERRUPT +GOTO_U_MODE // Should cause software interrupt to fire off. END_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-01.S index 45d34c344..35fea2b98 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-01.S @@ -21,7 +21,7 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -#include "WALLY-TEST-LIB-64.h" +#include "WALLY-TEST-LIB-32.h" INIT_TESTS @@ -35,7 +35,7 @@ WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources // *** commented // test 5.3.1.4 Basic trap tests -// jal cause_instr_addr_misaligned //skipped becuase this exception may be impossible when compressed instructions are enabled) +jal cause_instr_addr_misaligned jal cause_instr_access jal cause_illegal_instr jal cause_breakpnt @@ -47,16 +47,21 @@ GOTO_U_MODE // Causes M mode ecall GOTO_S_MODE // Causes U mode ecall GOTO_M_MODE // Causes S mode ecall -jal cause_time_interrupt // *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. -jal cause_soft_interrupt // *** exiting out of the trap handler after these is current;y broken -jal cause_ext_interrupt + +jal cause_s_soft_interrupt +jal cause_m_soft_interrupt +jal cause_s_time_interrupt +jal cause_m_time_interrupt +jal cause_s_ext_interrupt_GPIO +jal cause_m_ext_interrupt + // try the traps again with mideleg = medeleg = all 1's to ensure traps still go to M mode from M mode WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF -// jal cause_instr_addr_misaligned //skipped becuase this exception may be impossible when compressed instructions are enabled) +jal cause_instr_addr_misaligned jal cause_instr_access jal cause_illegal_instr jal cause_breakpnt @@ -66,9 +71,16 @@ jal cause_store_addr_misaligned jal cause_store_acc jal cause_ecall // M mode ecall -jal cause_time_interrupt // *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. -jal cause_soft_interrupt // *** exiting out of the trap handler after these is current;y broken -jal cause_ext_interrupt +jal cause_s_soft_interrupt // The delegated S mode interrupts should not fire since we're running in M mode. +jal cause_m_soft_interrupt +jal cause_s_time_interrupt +jal cause_m_time_interrupt +li a3, 0x40 // these interrupts involve a time loop waiting for the interrupt to go off. +// since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3 +jal cause_s_ext_interrupt_GPIO +li a3, 0x40 +jal cause_m_ext_interrupt + END_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S index 9a813d9a2..0c4477619 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S @@ -21,38 +21,46 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -#include "WALLY-TEST-LIB-64.h" +#include "WALLY-TEST-LIB-32.h" INIT_TESTS +CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses + // test 5.3.1.4 Basic trap tests -TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps +TRAP_HANDLER m, DEBUG=1 // necessary to handle switching privilege modes TRAP_HANDLER s, DEBUG=1 // have S mode trap handler as well // Like WALLY-trap, cause all the same traps from S mode and make sure they go to machine mode with zeroed mideleg, medeleg +li x28, 0x2 +csrs sstatus, x28 // set sstatus.SIE bit to 1 +WRITE_READ_CSR mie, 0xFFFF // sie is a subset of mie, so writing this also enables sie. + GOTO_S_MODE -li x28, 0x8 -csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode -// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts +jal cause_instr_addr_misaligned +jal cause_instr_access +jal cause_illegal_instr +jal cause_breakpnt +jal cause_load_addr_misaligned +jal cause_load_acc +jal cause_store_addr_misaligned +jal cause_store_acc +GOTO_U_MODE // Causes S mode ecall +GOTO_S_MODE // Causes U mode ecall -// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled) -CAUSE_INSTR_ACCESS -CAUSE_ILLEGAL_INSTR -CAUSE_BREAKPNT -CAUSE_LOAD_ADDR_MISALIGNED -CAUSE_LOAD_ACC -CAUSE_STORE_ADDR_MISALIGNED -CAUSE_STORE_ACC -CAUSE_ECALL - -// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. -// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken -// CAUSE_EXT_INTERRUPT - +// some interrupts excluded becaus writing MIP is illegal from S mode +jal cause_s_soft_interrupt +jal cause_m_soft_interrupt +jal cause_m_time_interrupt +li a3, 0x40 // this interrupt involves a time loop waiting for the interrupt to go off. +// since interrupts are not always enabled, +jal cause_s_ext_interrupt_GPIO +li a3, 0x40 +jal cause_m_ext_interrupt // Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler // We can tell which one becuase the different trap handler modes write different bits of the status register @@ -63,21 +71,24 @@ GOTO_M_MODE // so we can write the delegate registers WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF -GOTO_S_MODE +GOTO_S_MODE // Since we're running in M mode, this ecall will NOT be delegated to S mode -// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled) -CAUSE_INSTR_ACCESS -CAUSE_ILLEGAL_INSTR -CAUSE_BREAKPNT -CAUSE_LOAD_ADDR_MISALIGNED -CAUSE_LOAD_ACC -CAUSE_STORE_ADDR_MISALIGNED -CAUSE_STORE_ACC -CAUSE_ECALL +jal cause_instr_addr_misaligned +jal cause_instr_access +jal cause_illegal_instr +jal cause_breakpnt +jal cause_load_addr_misaligned +jal cause_load_acc +jal cause_store_addr_misaligned +jal cause_store_acc +GOTO_U_MODE // Causes S mode ecall +GOTO_S_MODE // Causes U mode ecall + +// M mode interrupts cannot be delegated in this implementation, so they are excluded from tests +jal cause_s_soft_interrupt +li a3, 0x40 +jal cause_s_ext_interrupt_GPIO -// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. -// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken -// CAUSE_EXT_INTERRUPT END_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-sret-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-sret-01.S new file mode 100644 index 000000000..1baf02dfe --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-sret-01.S @@ -0,0 +1,42 @@ +/////////////////////////////////////////// +// +// WALLY-trap-sret +// +// Author: Kip Macsai-Goren +// +// Created 2022-04-10 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-LIB-32.h" + +INIT_TESTS + +TRAP_HANDLER m, DEBUG=1 + +// test 5.3.1.6 Interrupt enabling and priority tests + +li x28, 0x400000 +csrs mstatus, x28 // Set mstatus.tsr to 1. + +GOTO_S_MODE + +sret // attempt to run sret instruction. +// should cause illegal instruction exception despite being in s mode + +END_TESTS + +TEST_STACK_AND_DATA diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S index 498c2ee3b..326f53625 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S @@ -21,10 +21,12 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -#include "WALLY-TEST-LIB-64.h" +#include "WALLY-TEST-LIB-32.h" INIT_TESTS +CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses + // test 5.3.1.4 Basic trap tests TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps @@ -32,27 +34,30 @@ TRAP_HANDLER s, DEBUG=1 // have S mode trap handler as well // Like WALLY-trap, cause all the same traps from U mode and make sure they go to machine mode with zeroed mideleg, medeleg +li x28, 0x2 +csrs sstatus, x28 // set sstatus.SIE bit to 1. Not strictly necessary but this lets us differentiate which trap handler we went to +WRITE_READ_CSR mie, 0xFFFF + GOTO_U_MODE -// li x28, 0x8 -// csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode -// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts - - -// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled) -CAUSE_INSTR_ACCESS -CAUSE_ILLEGAL_INSTR -CAUSE_BREAKPNT -CAUSE_LOAD_ADDR_MISALIGNED -CAUSE_LOAD_ACC -CAUSE_STORE_ADDR_MISALIGNED -CAUSE_STORE_ACC -CAUSE_ECALL - -// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. -// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken -// CAUSE_EXT_INTERRUPT +jal cause_instr_addr_misaligned +jal cause_instr_access +jal cause_illegal_instr +jal cause_breakpnt +jal cause_load_addr_misaligned +jal cause_load_acc +jal cause_store_addr_misaligned +jal cause_store_acc +jal cause_ecall +// some interrupts excluded becaus writing SIP/MIP is illegal from U mode +jal cause_m_soft_interrupt +jal cause_m_time_interrupt +li a3, 0x40 // this interrupt involves a time loop waiting for the interrupt to go off. +// since interrupts are not always enabled, +jal cause_s_ext_interrupt_GPIO +li a3, 0x40 +jal cause_m_ext_interrupt // Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler // We can tell which one becuase the different trap handler modes write different bits of the status register @@ -65,19 +70,19 @@ WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF GOTO_U_MODE -// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled) -CAUSE_INSTR_ACCESS -CAUSE_ILLEGAL_INSTR -CAUSE_BREAKPNT -CAUSE_LOAD_ADDR_MISALIGNED -CAUSE_LOAD_ACC -CAUSE_STORE_ADDR_MISALIGNED -CAUSE_STORE_ACC -CAUSE_ECALL - -// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. -// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken -// CAUSE_EXT_INTERRUPT +jal cause_instr_addr_misaligned +jal cause_instr_access +jal cause_illegal_instr +jal cause_breakpnt +jal cause_load_addr_misaligned +jal cause_load_acc +jal cause_store_addr_misaligned +jal cause_store_acc +jal cause_ecall + +// M mode interrupts cannot be delegated in this implementation, so they are excluded from tests +li a3, 0x40 +jal cause_s_ext_interrupt_GPIO END_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefile b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefile index 27e6ec971..7404f07c1 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefile +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefile @@ -1,5 +1,5 @@ include ../../Makefile.include -RVTEST_DEFINES += -march=rv$(XLEN)ia # KMG: removed compressed instructions from privileged tests +RVTEST_DEFINES += -march=rv$(XLEN)iaf # KMG: removed compressed instructions from privileged tests -$(eval $(call compile_template,-march=rv64iac -mabi=lp64 -Drvtest_mtrap_routine=True -DXLEN=$(XLEN))) +$(eval $(call compile_template,-march=rv64iaf -mabi=lp64 -Drvtest_mtrap_routine=True -DXLEN=$(XLEN))) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag index 73ef3c203..f21592b10 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag @@ -35,10 +35,13 @@ rv64i_sc_tests = \ WALLY-CSR-permission-s-01 \ WALLY-CSR-permission-u-01 \ WALLY-misa-01 \ - WALLY-scratch-01 \ - WALLY-sscratch-s-01 \ WALLY-AMO \ WALLY-LRSC \ + WALLY-trap-sret-01 \ +# WALLY-scratch-01 \ +# WALLY-sscratch-s-01 \ + +# WALLY-scratch-01 \ # Don't simulate these because they rely on SoC features that Wally does not offer. target_tests_nosim = \ @@ -57,7 +60,18 @@ target_tests_nosim = \ WALLY-MVENDORID \ WALLY-CSR-PERMISSIONS-M \ WALLY-CSR-PERMISSIONS-S \ + WALLY-mtvec-01 \ + WALLY-stvec-01 \ + WALLY-MIE-01 \ + WALLY-PIE-stack-01 \ + WALLY-PIE-stack-s-01 \ WALLY-trap-01 \ + WALLY-trap-s-01 \ + WALLY-trap-u-01 \ + WALLY-status-tw-01 \ + WALLY-WFI-01 \ + WALLY-status-fp-enabled-01 \ + WALLY-status-fp-disabled-01 \ # Have all 0's in references! #WALLY-MEPC \ #WALLY-SEPC \ diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MIE-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MIE-01.reference_output new file mode 100644 index 000000000..a50302e59 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MIE-01.reference_output @@ -0,0 +1,1024 @@ +00000000 # test 5.3.1.6: Readback value from zeroing out MIE. +00000000 # note that none of the attempted interrupts should fire since MIE is zeroed. +0000000b # mcause for ecall from terminating tests in M mode +00000000 +00000000 # mtval of ecall (*** defined to be zero for now) +00000000 +00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 +00000000 +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef 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a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PIE-stack-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PIE-stack-s-01.reference_output new file mode 100644 index 000000000..748d8b72d --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PIE-stack-s-01.reference_output @@ -0,0 +1,1024 @@ +00000aaa # test 5.3.1.6: enabling all of MIE +00000000 +00000222 # writeaback for delegating all interrupts to S mode +00000000 +0000000b # mcause for ecall from going to S mode from M mode +00000000 +00000000 # mtval of ecall (*** defined to be zero for now) +00000000 +00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +0007ec01 # value to indicate successful vectoring on s soft interrupt +00000000 +00000001 # scause value from s soft interrupt +80000000 +00000000 # stval for ssoft interrupt (0x0) +00000000 +00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 # Note here that we atempt to cause an interrupt after zeroing status.mie, but it shouldn't fire. +00000009 # mcause for ecall from terminating tests in S mode +00000000 +00000000 # mtval of ecall (*** defined to be zero for now) +00000000 +00000800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef 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b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mtvec-01.reference_output @@ -1,3 +1,17 @@ +00000aaa # Test 5.3.1.5: readback value of SIE after enabling all interrupts. +00000000 +00000007 # mcause from m time interrupt +80000000 +00000000 # mtval for mtime interrupt (0x0) +00000000 +00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 +00000000 +0000000b # mcause from M mode ecall from test termination +00000000 +00000000 # mtval of ecall (*** defined to be zero for now) +00000000 +00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 +00000000 deadbeef deadbeef deadbeef @@ -1007,18 +1021,4 @@ deadbeef deadbeef deadbeef deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef +deadbeef \ No newline at end of file diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-fp-disabled-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-fp-disabled-01.reference_output new file mode 100644 index 000000000..67ee6be74 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-fp-disabled-01.reference_output @@ -0,0 +1,1016 @@ +00000000 # read SD = 0, FS = 00 after diabling floating point +00000000 +00000000 # read SD = 0, FS = 00 after attempting to write to diabled bits +00000000 +0000000b # mcause from M mode ecall from test termination +00000000 +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef 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b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-fp-enabled-01.reference_output new file mode 100644 index 000000000..936435099 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-fp-enabled-01.reference_output @@ -0,0 +1,1020 @@ +00002000 # read SD = 0, FS = 01 +00000000 +00006000 # read SD = 1, FS = 11 +80000000 +00004000 # read written SD = 1, FS = 10 +00000000 +00006000 # read SD = 1, FS = 11 +80000000 +0000000b # mcause from M mode ecall from test termination +00000000 +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef 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b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-tw-01.reference_output @@ -0,0 +1,1024 @@ +0000000b # mcause from ecall going from M mode to S mode +00000000 +00000000 # mtval of ecall (*** defined to be zero for now) +00000000 +00001800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000002 # mcause from an Illegal instruction +00000000 +00000000 # mtval of faulting instruction (0x0) +00000000 +00000800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000009 # mcause from S mode ecall from test termination +00000000 +00000000 # mtval of ecall (*** defined to be zero for now) +00000000 +00000800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef 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b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-stvec-01.reference_output index bc760ed62..769df3823 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-stvec-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-stvec-01.reference_output @@ -1,43 +1,43 @@ -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef +00000aaa # Test 5.3.1.5: readback value of MIE after enabling all interrupts. +00000000 +00000222 # readback value of mideleg after attempting to delegate all interrupts. +00000000 +0000000b # mcause from ecall for going from M mode to S mode +00000000 +00000000 # mtval of ecall (*** defined to be zero for now) +00000000 +00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000001 # mcause from s soft interrupt +80000000 +00000000 # mtval for ssoft interrupt (0x0) +00000000 +00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +00000009 # mcause from ecall for going from S mode to M mode +00000000 +00000000 # mtval of ecall (*** defined to be zero for now) +00000000 +00000800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +0000000b # mcause from ecall for going from M mode to U mode +00000000 +00000000 # mtval of ecall (*** defined to be zero for now) +00000000 +00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000001 # mcause from s soft interrupt from user mode this time +80000000 +00000000 # mtval for mtime interrupt (0x0) +00000000 +00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +00000008 # mcause from U mode ecall from test termination +00000000 +00000000 # mtval of ecall (*** defined to be zero for now) +00000000 +00000000 # masked out mstatus.MPP = 00, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 deadbeef deadbeef deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output index eef583deb..d8f7f8b40 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output @@ -1,5 +1,11 @@ 00000aaa # Test 5.3.1.4: readback value from writing mie to enable interrupts 00000000 +00000000 # mcause from instruction addr misaligned fault +00000000 +800003d2 # mtval of faulting instruction adress (0x800003d3) +00000000 +00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 +00000000 00000001 # mcause from an instruction access fault 00000000 00000000 # mtval of faulting instruction address (0x0) @@ -14,13 +20,13 @@ 00000000 00000003 # mcause from Breakpoint 00000000 -800003ec # mtval of breakpoint instruction adress (0x800003ec) +80000404 # mtval of breakpoint instruction adress (0x80000404) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 00000004 # mcause from load address misaligned 00000000 -800003f5 # mtval of misaligned address (0x800003f5) +8000040d # mtval of misaligned address (0x8000040d) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 @@ -32,7 +38,7 @@ 00000000 00000006 # mcause from store misaligned 00000000 -80000411 # mtval of address with misaligned store instr (0x80000410) +80000429 # mtval of address with misaligned store instr (0x80000429) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 @@ -60,7 +66,31 @@ 00000000 00000880 # masked out mstatus.MPP = 01 (from S mode), mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 -000007ec # value to indicate a vectored interrupts +0007ec01 # value to indicate successful vectoring on s soft interrupt +00000000 +00000001 # mcause value from s soft interrupt +80000000 +00000000 # mtval for ssoft interrupt (0x0) +00000000 +00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 +00000000 +0007ec03 # value to indicate successful vectoring on m soft interrupt +00000000 +00000003 # mcause value from m soft interrupt +80000000 +00000000 # mtval for msoft interrupt (0x0) +00000000 +00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 +00000000 +0007ec05 # value to indicate successful vectoring on s time interrupt +00000000 +00000005 # mcause value from s time interrupt +80000000 +00000000 # mtval for stime interrupt (0x0) +00000000 +00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 +00000000 +0007ec07 # value to indicate successful vectoring on m time interrupt 00000000 00000007 # mcause value from m time interrupt 80000000 @@ -68,15 +98,15 @@ 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 -000007ec # value to indicate a vectored interrupts +0007ec09 # value to indicate successful vectoring on s ext interrupt 00000000 -00000001 # mcause value from m soft interrupt +00000009 # mcause value from s ext interrupt 80000000 -00000000 # mtval for msoft interrupt (0x0) +00000000 # mtval for sext interrupt (0x0) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 -000007ec # value to indicate a vectored interrupts +0007ec0b # value to indicate successful vectoring on m ext interrupt 00000000 0000000b # mcause value from m ext interrupt 80000000 @@ -84,11 +114,17 @@ 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 -0000b309 # medeleg after attempted write of all 1's (only some bits are writeable) -00000000 +fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable) +ffffffff 00000222 # mideleg after attempted write of all 1's (only some bits are writeable) 00000000 -00000001 # Test 5.3.1.4: mcause from an instruction access fault +00000000 # mcause from instruction addr misaligned fault +00000000 +800003d2 # mtval of faulting instruction adress (0x800003d3) +00000000 +00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 +00000000 +00000001 # mcause from an instruction access fault 00000000 00000000 # mtval of faulting instruction address (0x0) 00000000 @@ -102,13 +138,13 @@ 00000000 00000003 # mcause from Breakpoint 00000000 -800003ec # mtval of breakpoint instruction adress (0x800003ec) +80000404 # mtval of breakpoint instruction adress (0x80000404) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 00000004 # mcause from load address misaligned 00000000 -800003f5 # mtval of misaligned address (0x800003f5) +8000040d # mtval of misaligned address (0x8000040d) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 @@ -120,7 +156,7 @@ 00000000 00000006 # mcause from store misaligned 00000000 -80000411 # mtval of address with misaligned store instr (0x80000410) +80000429 # mtval of address with misaligned store instr (0x80000429) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 @@ -136,23 +172,23 @@ 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 -000007ec # value to indicate a vectored interrupts +0007ec03 # value to indicate successful vectoring on m soft interrupt 00000000 -00000007 # mcause value from time interrupt -80000000 -00000000 # mtval for mtime interrupt (0x0) -00000000 -00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 -00000000 -000007ec # value to indicate a vectored interrupts -00000000 -00000001 # mcause value from m soft interrupt +00000003 # mcause value from m soft interrupt 80000000 00000000 # mtval for msoft interrupt (0x0) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 -000007ec # value to indicate a vectored interrupts +0007ec07 # value to indicate successful vectoring on m time interrupt +00000000 +00000007 # mcause value from m time interrupt +80000000 +00000000 # mtval for mtime interrupt (0x0) +00000000 +00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 +00000000 +0007ec0b # value to indicate successful vectoring on m ext interrupt 00000000 0000000b # mcause value from m ext interrupt 80000000 @@ -986,89 +1022,3 @@ deadbeef deadbeef deadbeef deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output index bc760ed62..84519e037 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output @@ -1,219 +1,209 @@ -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef +00000aaa # readback value from writing mie to enable interrupts +00000000 +0000000b # Test 5.3.1.4: mcause from ecall going from M mode to S mode +00000000 +00000000 # mtval of ecall (*** defined to be zero for now) +00000000 +00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000000 # scause from instruction addr misaligned fault +00000000 +800003d2 # stval of faulting instruction adress (0x800003d3) +00000000 +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000001 # scause from an instruction access fault +00000000 +00000000 # stval of faulting instruction address (0x0) +00000000 +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000002 # scause from an Illegal instruction +00000000 +00000000 # stval of faulting instruction (0x0) +00000000 +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000003 # scause from Breakpoint +00000000 +80000404 # stval of breakpoint instruction adress (0x80000404) +00000000 +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000004 # scause from load address misaligned +00000000 +8000040d # stval of misaligned address (0x8000040d) +00000000 +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000005 # scause from load access +00000000 +00000000 # stval of accessed adress (0x0) +00000000 +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000006 # scause from store misaligned +00000000 +80000429 # stval of address with misaligned store instr (0x80000429) +00000000 +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000007 # scause from store access +00000000 +00000000 # stval of accessed address (0x0) +00000000 +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000009 # scause from S mode ecall +00000000 +00000000 # stval of ecall (*** defined to be zero for now) +00000000 +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000008 # scause from U mode ecall +00000000 +00000000 # stval of ecall (*** defined to be zero for now) +00000000 +00000000 # masked out mstatus.mpp = 0 (from U mode), mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +0007ec01 # value to indicate successful vectoring on s soft interrupt +00000000 +00000001 # scause value from s soft interrupt +80000000 +00000000 # stval for ssoft interrupt (0x0) +00000000 +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +0007ec03 # value to indicate successful vectoring on m soft interrupt +00000000 +00000003 # scause value from m soft interrupt +80000000 +00000000 # stval for msoft interrupt (0x0) +00000000 +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +0007ec07 # value to indicate successful vectoring on m time interrupt +00000000 +00000007 # scause value from m time interrupt +80000000 +00000000 # stval for mtime interrupt (0x0) +00000000 +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +0007ec09 # value to indicate successful vectoring on s ext interrupt +00000000 +00000009 # scause value from s ext interrupt +80000000 +00000000 # stval for sext interrupt (0x0) +00000000 +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +0007ec0b # value to indicate successful vectoring on m ext interrupt +00000000 +0000000b # scause value from m ext interrupt +80000000 +00000000 # stval for mext interrupt (0x0) +00000000 +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000009 # scause from S mode ecall +00000000 +00000000 # stval of ecall (*** defined to be zero for now) +00000000 +00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable) +ffffffff +00000222 # mideleg after attempted write of all 1's (only some bits are writeable) +00000000 +0000000b # scause from M mode ecall +00000000 +00000000 # stval of ecall (*** defined to be zero for now) +00000000 +00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000000 # scause from instruction addr misaligned fault +00000000 +800003d2 # stval of faulting instruction adress (0x800003d3) +00000000 +00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +00000001 # scause from an instruction access fault +00000000 +00000000 # stval of faulting instruction address (0x0) +00000000 +00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +00000002 # scause from an Illegal instruction +00000000 +00000000 # stval of faulting instruction (0x0) +00000000 +00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +00000003 # scause from Breakpoint +00000000 +80000404 # stval of breakpoint instruction adress (0x80000404) +00000000 +00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +00000004 # scause from load address misaligned +00000000 +8000040d # stval of misaligned address (0x8000040d) +00000000 +00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +00000005 # scause from load access +00000000 +00000000 # stval of accessed adress (0x0) +00000000 +00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +00000006 # scause from store misaligned +00000000 +80000429 # stval of address with misaligned store instr (0x80000429) +00000000 +00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +00000007 # scause from store access +00000000 +00000000 # stval of accessed address (0x0) +00000000 +00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +00000009 # scause from S mode ecall +00000000 +00000000 # stval of ecall (*** defined to be zero for now) +00000000 +00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +00000008 # scause from U mode ecall +00000000 +00000000 # stval of ecall (*** defined to be zero for now) +00000000 +00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +0007ec01 # value to indicate successful vectoring on s soft interrupt +00000000 +00000001 # scause value from s soft interrupt +80000000 +00000000 # stval for ssoft interrupt (0x0) +00000000 +00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +0007ec09 # value to indicate successful vectoring on s ext interrupt +00000000 +00000009 # scause value from s ext interrupt +80000000 +00000000 # stval for sext interrupt (0x0) +00000000 +00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +00000009 # scause from S mode ecall from test termination +00000000 +00000000 # stval of ecall (*** defined to be zero for now) +00000000 +00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 deadbeef deadbeef deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-sret-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-sret-01.reference_output new file mode 100644 index 000000000..240da5850 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-sret-01.reference_output @@ -0,0 +1,1024 @@ +0000000b # test 5.3.1.6: mcause for ecall from going to S mode from M mode +00000000 +00000000 # mtval of ecall (*** defined to be zero for now) +00000000 +00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000002 # mcause for illegal sret instruction due to status.tsr bit being set. +00000000 +10200073 # mtval of illegal instruction (illegal instruction's machine code) +00000000 +00000800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000009 # mcause from S mode ecall from test termination +00000000 +00000000 # mtval of ecall (*** defined to be zero for now) +00000000 +00000800 # masked out mstatus.MPP = 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+deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output index bc760ed62..7a1b3dcd8 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output @@ -1,181 +1,181 @@ -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef +00000aaa # readback value from writing mie to enable interrupts +00000000 +0000000b # Test 5.3.1.4: mcause from ecall going from M mode to U mode +00000000 +00000000 # mtval of ecall (*** defined to be zero for now) +00000000 +00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000000 # scause from instruction addr misaligned fault +00000000 +800003d2 # stval of faulting instruction adress (0x800003d3) +00000000 +00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000001 # scause from an instruction access fault +00000000 +00000000 # stval of faulting instruction address (0x0) +00000000 +00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000002 # scause from an Illegal instruction +00000000 +00000000 # stval of faulting instruction (0x0) +00000000 +00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000003 # scause from Breakpoint +00000000 +80000404 # stval of breakpoint instruction adress (0x80000404) +00000000 +00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000004 # scause from load address misaligned +00000000 +8000040d # stval of misaligned address (0x8000040d) +00000000 +00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000005 # scause from load access +00000000 +00000000 # stval of accessed adress (0x0) +00000000 +00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000006 # scause from store misaligned +00000000 +80000429 # stval of address with misaligned store instr (0x80000429) +00000000 +00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000007 # scause from store access +00000000 +00000000 # stval of accessed address (0x0) +00000000 +00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000008 # scause from U mode ecall +00000000 +00000000 # stval of ecall (*** defined to be zero for now) +00000000 +00000000 # masked out mstatus.mpp = 0 (from U mode), mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +0007ec03 # value to indicate successful vectoring on m soft interrupt +00000000 +00000003 # scause value from m soft interrupt +80000000 +00000000 # stval for msoft interrupt (0x0) +00000000 +00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +0007ec07 # value to indicate successful vectoring on m time interrupt +00000000 +00000007 # scause value from m time interrupt +80000000 +00000000 # stval for mtime interrupt (0x0) +00000000 +00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +0007ec09 # value to indicate successful vectoring on s ext interrupt +00000000 +00000009 # scause value from s ext interrupt +80000000 +00000000 # stval for sext interrupt (0x0) +00000000 +00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +0007ec0b # value to indicate successful vectoring on m ext interrupt +00000000 +0000000b # scause value from m ext interrupt +80000000 +00000000 # stval for mext interrupt (0x0) +00000000 +00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000008 # scause from U mode ecall +00000000 +00000000 # stval of ecall (*** defined to be zero for now) +00000000 +00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable) +ffffffff +00000222 # mideleg after attempted write of all 1's (only some bits are writeable) +00000000 +0000000b # scause from M mode ecall +00000000 +00000000 # stval of ecall (*** defined to be zero for now) +00000000 +00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0 +00000000 +00000000 # scause from instruction addr misaligned fault +00000000 +800003d2 # stval of faulting instruction adress (0x800003d3) +00000000 +00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +00000001 # scause from an instruction access fault +00000000 +00000000 # stval of faulting instruction address (0x0) +00000000 +00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +00000002 # scause from an Illegal instruction +00000000 +00000000 # stval of faulting instruction (0x0) +00000000 +00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +00000003 # scause from Breakpoint +00000000 +80000404 # stval of breakpoint instruction adress (0x80000404) +00000000 +00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +00000004 # scause from load address misaligned +00000000 +8000040d # stval of misaligned address (0x8000040d) +00000000 +00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +00000005 # scause from load access +00000000 +00000000 # stval of accessed adress (0x0) +00000000 +00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +00000006 # scause from store misaligned +00000000 +80000429 # stval of address with misaligned store instr (0x80000429) +00000000 +00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +00000007 # scause from store access +00000000 +00000000 # stval of accessed address (0x0) +00000000 +00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +00000008 # scause from U mode ecall +00000000 +00000000 # stval of ecall (*** defined to be zero for now) +00000000 +00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +0007ec09 # value to indicate successful vectoring on s ext interrupt +00000000 +00000009 # scause value from s ext interrupt +80000000 +00000000 # stval for sext interrupt (0x0) +00000000 +00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 +00000008 # scause from U mode ecall from test termination +00000000 +00000000 # stval of ecall (*** defined to be zero for now) +00000000 +00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 +00000000 deadbeef deadbeef deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MIE-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MIE-01.S new file mode 100644 index 000000000..ce265a35c --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MIE-01.S @@ -0,0 +1,53 @@ +/////////////////////////////////////////// +// +// WALLY-MIE +// +// Author: Kip Macsai-Goren +// +// Created 2022-04-10 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-LIB-64.h" + +INIT_TESTS + +CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses + +TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps + +li x28, 0x8 +csrs mstatus, x28 // set mstatus.MIE bit to 1. +WRITE_READ_CSR mie, 0x0 // force zeroing out mie CSR. + +// test 5.3.1.6 Interrupt enabling and priority tests +// testing with MIE bits set already tested in WALLY-trap +// note that none of these interrupts should be caught or handled. + +jal cause_s_soft_interrupt +jal cause_m_soft_interrupt +jal cause_s_time_interrupt +jal cause_m_time_interrupt +li a3, 0x40 // these interrupts involve a time loop waiting for the interrupt to go off. +// since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3 +jal cause_s_ext_interrupt_GPIO +li a3, 0x40 +jal cause_m_ext_interrupt + +END_TESTS + +TEST_STACK_AND_DATA + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PIE-stack-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PIE-stack-01.S new file mode 100644 index 000000000..ff16a18b2 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PIE-stack-01.S @@ -0,0 +1,49 @@ +/////////////////////////////////////////// +// +// WALLY-privilege-interrupt-enable-stack +// +// Author: Kip Macsai-Goren +// +// Created 2022-04-10 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-LIB-64.h" + +INIT_TESTS + +CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses + +TRAP_HANDLER m, DEBUG=1 + +li x28, 0x8 +csrs mstatus, x28 // set mstatus.MIE bit to 1 +WRITE_READ_CSR mie, 0xFFF + +// test 5.3.1.6 Interrupt enabling and priority tests + +// Cause interrupt, ensuring that status.mie = 0 , status.mpie = 1, and status.mpp = 11 during trap handling +jal cause_m_soft_interrupt /// only cause one interrupt because we just want to test the status stack + +li x28, 0x8 +csrc mstatus, x28 // set mstatus.MIE bit to 0. interrupts from M mode should not happen + +// attempt to cause interrupt, it should not go through +jal cause_m_soft_interrupt + +END_TESTS + +TEST_STACK_AND_DATA diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PIE-stack-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PIE-stack-s-01.S new file mode 100644 index 000000000..e5b9bf00c --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PIE-stack-s-01.S @@ -0,0 +1,53 @@ +/////////////////////////////////////////// +// +// WALLY-privilege-interrupt-enable-stack +// +// Author: Kip Macsai-Goren +// +// Created 2022-04-10 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-LIB-64.h" + +INIT_TESTS + +CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses + +TRAP_HANDLER m, DEBUG=1 // necessary so we can go to S mode +TRAP_HANDLER s, DEBUG=1 // neccessary to handle s mode interrupts. + +li x28, 0x2 +csrs sstatus, x28 // set sstatus.SIE bit to 1 +WRITE_READ_CSR mie, 0xFFF // enable all interrupts, including supervisor ones +WRITE_READ_CSR mideleg 0xFFFF // delegate all interrupts to S mode. + +// test 5.3.1.6 Interrupt enabling and priority tests + +GOTO_S_MODE + +// Cause interrupt, ensuring that status.sie = 0 , status.spie = 1, and status.spp = 1 during trap handling +jal cause_s_soft_interrupt // only cause one interrupt because we just want to test the status stack + +li x28, 0x2 +csrc sstatus, x28 // set sstatus.SIE bit to 0. interrupts from S mode should not happen + +// attempt to cause interrupt, it should not go through +jal cause_s_soft_interrupt + +END_TESTS + +TEST_STACK_AND_DATA diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMP.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMP.S index ca4617c55..e1feb6866 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMP.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMP.S @@ -57,7 +57,7 @@ test_cases: # Test 12.3.2.2.1 Config: Write known values and set PMP config according to table 12.4 in the *** riscv book, copied below # write pmpaddr regs. Each of these should output the value of the pmpaddr after being written. - # *** change the pmpcfg and addr commands to the right number # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments | +# | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments | .8byte 0x0, 0x0FFFFFFF, write_pmpaddr_0 # | 0 | 0x0FFFFFFF | 1F | 0 | NAPOT | 0 | 1 | 1 | I/O 00000000-7FFFFFFF RW | .8byte 0x1, 0x20040000, write_pmpaddr_1 # | 1 | 0x20040000 | 00 | 0 | OFF | 0 | 0 | 0 | | .8byte 0x2, 0x2004003F, write_pmpaddr_2 # | 2 | 0x2004003F | 09 | 0 | TOR | 0 | 0 | 1 | 80100000-801000FF R | diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h index 4f96071ea..f34f5035f 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h @@ -66,11 +66,13 @@ j end_trap_triggers // The following tests involve causing many of the interrupts and exceptions that are easily done in a few lines // This effectively includes everything that isn't to do with page faults (virtual memory) - +// +// INPUTS: a3 (x13): the number of times one of the infinitely looping interrupt causes should loop before giving up and continuing without the interrupt firing. +// cause_instr_addr_misaligned: // cause a misaligned address trap auipc x28, 0 // get current PC, which is aligned - addi x28, x28, 0x3 // add 1 to pc to create misaligned address + addi x28, x28, 0x2 // add 2 to pc to create misaligned address (Assumes compressed instructions are disabled) jr x28 // cause instruction address midaligned trap ret @@ -84,7 +86,7 @@ cause_instr_access: ret cause_illegal_instr: - .word 0x00000000 // a 32 bit zros is an illegal instruction + .word 0x00000000 // 32 bit zero is an illegal instruction ret cause_breakpnt: @@ -114,14 +116,15 @@ cause_store_acc: ret cause_ecall: - // *** ASSUMES you have already gone to the mode you need to call this from. + // ASSUMES you have already gone to the mode you need to call this from. ecall ret -cause_time_interrupt: +cause_m_time_interrupt: // The following code works for both RV32 and RV64. // RV64 alone would be easier using double-word adds and stores li x28, 0x30 // Desired offset from the present time + mv a3, x28 // copy value in to know to stop waiting for interrupt after this many cycles la x29, 0x02004000 // MTIMECMP register in CLINT la x30, 0x0200BFF8 // MTIME register in CLINT lw x7, 0(x30) // low word of MTIME @@ -132,23 +135,101 @@ cause_time_interrupt: sw x31,4(x29) // store into most significant word of MTIMECMP nowrap: sw x28, 0(x29) // store into least significant word of MTIMECMP -loop: - wfi - j loop // wait until interrupt occurs +time_loop: + //wfi // *** this may now spin us forever in the loop??? + addi a3, a3, -1 + bnez a3, time_loop // go through this loop for [a3 value] iterations before returning without performing interrupt ret -cause_soft_interrupt: +cause_s_time_interrupt: + li x28, 0x20 + csrs mip, x28 // set supervisor time interrupt pending. SIP is a subset of MIP, so writing this should also change MIP. + nop // added extra nops in so the csrs can get through the pipeline before returning. + ret + +cause_m_soft_interrupt: la x28, 0x02000000 // MSIP register in CLINT li x29, 1 // 1 in the lsb sw x29, 0(x28) // Write MSIP bit ret -cause_ext_interrupt: +cause_s_soft_interrupt: + li x28, 0x2 + csrs sip, x28 // set supervisor software interrupt pending. SIP is a subset of MIP, so writing this should also change MIP. + ret + +cause_m_ext_interrupt: + # ========== Configure PLIC ========== + # m priority threshold = 0 + li x28, 0xC200000 + li x29, 0 + sw x29, 0(x28) + # s priority threshold = 7 + li x28, 0xC201000 + li x29, 7 + sw x29, 0(x28) + # source 3 (GPIO) priority = 1 + li x28, 0xC000000 + li x29, 1 + sw x29, 0x0C(x28) + # enable source 3 in M Mode + li x28, 0x0C002000 + li x29, 0b1000 + sw x29, 0(x28) + li x28, 0x10060000 // load base GPIO memory location li x29, 0x1 - sw x29, 8(x28) // enable the first pin as an output - sw x29, 28(x28) // set first pin to high interrupt enable - sw x29, 40(x28) // write a 1 to the first output pin (cause interrupt) + sw x29, 0x08(x28) // enable the first pin as an output + sw x29, 0x04(x28) // enable the first pin as an input as well to cause the interrupt to fire + + sw x0, 0x1C(x28) // clear rise_ip + sw x0, 0x24(x28) // clear fall_ip + sw x0, 0x2C(x28) // clear high_ip + sw x0, 0x34(x28) // clear low_ip + + sw x29, 0x28(x28) // set first pin to interrupt on a rising value + sw x29, 0x0C(x28) // write a 1 to the first output pin (cause interrupt) +m_ext_loop: + //wfi + addi a3, a3, -1 + bnez a3, m_ext_loop // go through this loop for [a3 value] iterations before returning without performing interrupt + ret + +cause_s_ext_interrupt_GPIO: + # ========== Configure PLIC ========== + # s priority threshold = 0 + li x28, 0xC201000 + li x29, 0 + sw x29, 0(x28) + # m priority threshold = 7 + li x28, 0xC200000 + li x29, 7 + sw x29, 0(x28) + # source 3 (GPIO) priority = 1 + li x28, 0xC000000 + li x29, 1 + sw x29, 0x0C(x28) + # enable source 3 in S mode + li x28, 0x0C002080 + li x29, 0b1000 + sw x29, 0(x28) + + li x28, 0x10060000 // load base GPIO memory location + li x29, 0x1 + sw x29, 0x08(x28) // enable the first pin as an output + sw x29, 0x04(x28) // enable the first pin as an input as well to cause the interrupt to fire + + sw x0, 0x1C(x28) // clear rise_ip + sw x0, 0x24(x28) // clear fall_ip + sw x0, 0x2C(x28) // clear high_ip + sw x0, 0x34(x28) // clear low_ip + + sw x29, 0x28(x28) // set first pin to interrupt on a rising value + sw x29, 0x0C(x28) // write a 1 to the first output pin (cause interrupt) +s_ext_loop: + //wfi + addi a3, a3, -1 + bnez a3, s_ext_loop // go through this loop for [a3 value] iterations before returning without performing interrupt ret end_trap_triggers: @@ -216,7 +297,7 @@ end_trap_triggers: // // -------------------------------------------------------------------------------------------- -.align 2 +.align 3 trap_handler_\MODE\(): j trap_unvectored_\MODE\() // for the unvectored implimentation: jump past this table of addresses into the actual handler // *** ASSUMES that a cause value of 0 for an interrupt is unimplemented @@ -273,24 +354,25 @@ trap_stack_saved_\MODE\(): // jump here after handling vectored interupt since w // Respond to trap based on cause // All interrupts should return after being logged csrr x1, \MODE\()cause - slli x1, x1, 3 // multiply cause by 8 to get offset in vector Table li x5, 0x8000000000000000 // if msb is set, it is an interrupt and x5, x5, x1 - bnez x5, interrupt_handler_\MODE\() // return from interrupt + bnez x5, interrupt_handler_\MODE\() // Other trap handling is specified in the vector Table la x5, exception_vector_table_\MODE\() + slli x1, x1, 3 // multiply cause by 8 to get offset in vector Table add x5, x5, x1 // compute address of vector in Table ld x5, 0(x5) // fectch address of handler from vector Table jr x5 // and jump to the handler interrupt_handler_\MODE\(): la x5, interrupt_vector_table_\MODE\() // NOTE THIS IS NOT THE SAME AS VECTORED INTERRUPTS!!! + slli x1, x1, 3 // multiply cause by 8 to get offset in vector Table add x5, x5, x1 // compute address of vector in Table ld x5, 0(x5) // fectch address of handler from vector Table jr x5 // and jump to the handler segfault_\MODE\(): - sd x7, -24(sp) // restore registers from stack before faulting + ld x7, -24(sp) // restore registers from stack before faulting ld x5, -16(sp) ld x1, -8(sp) j terminate_test // halt program. @@ -343,8 +425,11 @@ trapreturn_finished_\MODE\(): ld x7, -24(sp) // restore registers from stack before returning ld x5, -16(sp) ld x1, -8(sp) + csrrw sp, \MODE\()scratch, sp // switch sp and scratch stack back to restore the non-trap stack pointer \MODE\()ret // return from trap +// specific exception handlers + ecallhandler_\MODE\(): // Check input parameter a0. encoding above. li x5, 2 // case 2: change to machine mode @@ -358,21 +443,22 @@ ecallhandler_\MODE\(): ecallhandler_changetomachinemode_\MODE\(): // Force status.MPP (bits 12:11) to 11 to enter machine mode after mret + // note that it is impossible to return to M mode after a trap delegated to S mode li x1, 0b1100000000000 csrs \MODE\()status, x1 - j trapreturn_\MODE\() + j trapreturn_\MODE\() ecallhandler_changetosupervisormode_\MODE\(): - // Force status.MPP (bits 12:11) to 01 to enter supervisor mode after mret - li x1, 0b1100000000000 + // Force status.MPP (bits 12:11) and status.SPP (bit 8) to 01 to enter supervisor mode after (m/s)ret + li x1, 0b1000000000000 csrc \MODE\()status, x1 - li x1, 0b0100000000000 + li x1, 0b0100100000000 csrs \MODE\()status, x1 j trapreturn_\MODE\() ecallhandler_changetousermode_\MODE\(): - // Force mstatus.MPP (bits 12:11) to 00 to enter user mode after mret - li x1, 0b1100000000000 + // Force status.MPP (bits 12:11) and status.SPP (bit 8) to 00 to enter user mode after (m/s)ret + li x1, 0b1100100000000 csrc \MODE\()status, x1 j trapreturn_\MODE\() @@ -396,6 +482,9 @@ addr_misaligned_\MODE\(): breakpt_\MODE\(): j trapreturn_\MODE\() +// Vectored interrupt handlers: record the fact that the handler went to the correct vector and then continue to handling +// note: does not mess up any registers, saves and restores them to the stack instead. + s_soft_vector_\MODE\(): csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself. sd x5, -8(sp) // put x5 on the scratch stack before messing with it @@ -439,24 +528,61 @@ vectored_int_end_\MODE\(): ld x5, -8(sp) // restore x5 before continuing to handle trap in case its needed. j trap_stack_saved_\MODE\() +// specific interrupt handlers + soft_interrupt_\MODE\(): - la x28, 0x02000000 // Reset by clearing MSIP interrupt from CLINT - sw x0, 0(x28) - j trapreturn_\MODE\() + la x5, 0x02000000 // Reset by clearing MSIP interrupt from CLINT + sw x0, 0(x5) + + csrci \MODE\()ip, 0x2 // clear supervisor software interrupt pending bit + ld x1, -8(sp) // load return address from stack into ra (the address to return to after causing this interrupt) + // Note: we do this because the mepc loads in the address of the instruction after the sw that causes the interrupt + // This means that this trap handler will return to the next address after that one, which might be unpredictable behavior. + j trapreturn_finished_\MODE\() // return to the code at ra value from before trap time_interrupt_\MODE\(): - la x29, 0x02004000 // MTIMECMP register in CLINT - li x30, 0xFFFFFFFF - sd x30, 0(x29) // reset interrupt by setting mtimecmp to 0xFFFFFFFF + la x5, 0x02004000 // MTIMECMP register in CLINT + li x7, 0xFFFFFFFF + sd x7, 0(x5) // reset interrupt by setting mtimecmp to 0xFFFFFFFF - ld x1, -8(sp) // load return address from stack into ra (the address AFTER the jal to the faulting address) + li x5, 0x20 + csrc \MODE\()ip, x5 + ld x1, -8(sp) // load return address from stack into ra (the address to return to after the loop is complete) j trapreturn_finished_\MODE\() // return to the code at ra value from before trap ext_interrupt_\MODE\(): li x28, 0x10060000 // reset interrupt by clearing all the GPIO bits sw x0, 8(x28) // disable the first pin as an output sw x0, 40(x28) // write a 0 to the first output pin (reset interrupt) - j trapreturn_\MODE\() + + # reset PLIC to turn off external interrupts + # m priority threshold = 7 + li x28, 0xC200000 + li x5, 0x7 + sw x5, 0(x28) + # s priority threshold = 7 + li x28, 0xC201000 + li x5, 0x7 + sw x5, 0(x28) + # source 3 (GPIO) priority = 0 + li x28, 0xC000000 + li x5, 0 + sw x5, 0x0C(x28) + # disable source 3 in M mode + li x28, 0x0C002000 + li x5, 0b0000 + sw x5, 0(x28) + # enable source 3 in S mode + li x28, 0x0C002080 + li x29, 0b0000 + sw x29, 0(x28) + + li x5, 0x200 + csrc \MODE\()ip, x5 + + ld x1, -8(sp) // load return address from stack into ra (the address to return to after the loop is complete) + j trapreturn_finished_\MODE\() // return to the code at ra value from before trap + // Table of trap behavior // lists what to do on each exception (not interrupts) @@ -485,17 +611,17 @@ exception_vector_table_\MODE\(): .align 3 // aligns this data table to an 8 byte boundary interrupt_vector_table_\MODE\(): .8byte segfault_\MODE\() // 0: reserved - .8byte s_soft_vector_\MODE\() // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table. + .8byte soft_interrupt_\MODE\() // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table. .8byte segfault_\MODE\() // 2: reserved - .8byte m_soft_vector_\MODE\() // 3: breakpoint + .8byte soft_interrupt_\MODE\() // 3: breakpoint .8byte segfault_\MODE\() // 4: reserved - .8byte s_time_vector_\MODE\() // 5: load access fault + .8byte time_interrupt_\MODE\() // 5: load access fault .8byte segfault_\MODE\() // 6: reserved - .8byte m_time_vector_\MODE\() // 7: store access fault + .8byte time_interrupt_\MODE\() // 7: store access fault .8byte segfault_\MODE\() // 8: reserved - .8byte s_ext_vector_\MODE\() // 9: ecall from S-mode + .8byte ext_interrupt_\MODE\() // 9: ecall from S-mode .8byte segfault_\MODE\() // 10: reserved - .8byte m_ext_vector_\MODE\() // 11: ecall from M-mode + .8byte ext_interrupt_\MODE\() // 11: ecall from M-mode .align 3 trap_return_pagetype_table_\MODE\(): @@ -530,8 +656,6 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a // write_read_csr : write to specified CSR : old CSR value, 0x2, depending on perms : value written to CSR // csr_r_access : test read-only permissions on CSR : 0xbad : 0x2, then 0x11 -// *** TESTS TO ADD: execute inline, read unknown value out, read CSR unknown value, just read CSR value - .macro WRITE64 ADDR VAL // attempt to write VAL to ADDR // Success outputs: @@ -622,7 +746,6 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a // 0x9: test called from S mode // 0xB: test called from M mode // they generally do not fault or cause issues as long as these modes are enabled -// *** add functionality to check if modes are enabled before jumping? maybe cause a fault if not? .macro GOTO_M_MODE RETURN_VPN=0x0 RETURN_PAGETYPE=0x0 li a0, 2 // determine trap handler behavior (go to machine mode) @@ -649,7 +772,7 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a .endm // These tests change virtual memory settings, turning it on/off and changing between types. -// They don't have outputs as any error with turning on virtual memory should reveal itself in the tests *** Consider changing this policy? +// They don't have outputs as any error with turning on virtual memory should reveal itself in the tests .macro GOTO_BAREMETAL // Turn translation off @@ -688,7 +811,7 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a // value read back out from CSR after writing // Fault outputs: // The previous CSR value before write attempt - // *** Most likely 0x2, the mcause for illegal instruction if we don't have write or read access + // Most likely 0x2, the mcause for illegal instruction if we don't have write or read access li x30, 0xbad // load bad value to be overwritten by csrr li x29, \VAL\() csrw \CSR\(), x29 @@ -702,9 +825,9 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a // verify that a csr is accessible to read but not to write // Success outputs: // 0x2, then - // 0x11 *** consider changing to something more meaningful + // 0x11 // Fault outputs: - // 0xBAD *** consider changing this one as well. in general, do we need the branching if it hould cause an illegal instruction fault? + // 0xBAD csrr x29, \CSR csrwi \CSR\(), 0xA // Attempt to write a 'random' value to the CSR csrr x30, \CSR @@ -721,7 +844,7 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a .macro EXECUTE_AT_ADDRESS ADDR // Execute the code already written to ADDR, returning the value in x7. - // *** Note: this test itself doesn't write the code to ADDR because it might be callled at a point where we dont have write access to ADDR + // Note: this test itself doesn't write the code to ADDR because it might be callled at a point where we dont have write access to ADDR // Assumes the code modifies x7, usually to become 0x111. // Sample code: 0x11100393 (li x7, 0x111), 0x00008067 (ret) // Success outputs: @@ -767,7 +890,7 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a // Label for the location of the test that's about to take place // ------------------------------------------------------------------------------------------------------------------------------------ -.macro INIT_TEST_TABLE // *** Consider renaming this test. to what??? +.macro INIT_TEST_TABLE test_loop_setup: la x5, test_cases @@ -904,8 +1027,6 @@ goto_sv39: or x7, x7, x29 // put ASID into the correct field of SATP or x7, x7, x28 // Base Pagetable physical page number, satp.PPN field. csrw satp, x7 - li x29, 0xFFFFFFFFFFFFF888 - sfence.vma x0, x29 // just an attempt *** j test_loop // go to next test case goto_sv48: diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-WFI-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-WFI-01.S new file mode 100644 index 000000000..8f5a27e05 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-WFI-01.S @@ -0,0 +1,65 @@ +/////////////////////////////////////////// +// +// WALLY-wait-for-interrupt +// +// Author: Kip Macsai-Goren +// +// Created 2022-04-24 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-LIB-64.h" + +INIT_TESTS + +TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps + +li x28, 0x8 +csrs mstatus, x28 // set mstatus.MIE bit to 1 +WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources + +// Code copied from test library to cause m time interrupt, with time loop replaced with wfi. + +li x28, 0x60 // Desired offset from the present time +mv a3, x28 // copy value in to know to stop waiting for interrupt after this many cycles +la x29, 0x02004000 // MTIMECMP register in CLINT +la x30, 0x0200BFF8 // MTIME register in CLINT +lw x7, 0(x30) // low word of MTIME +lw x31, 4(x30) // high word of MTIME +add x28, x7, x28 // add desired offset to the current time +bgtu x28, x7, nowrap // check new time exceeds current time (no wraparound) +addi x31, x31, 1 // if wrap, increment most significant word +sw x31,4(x29) // store into most significant word of MTIMECMP + +nowrap: + sw x28, 0(x29) // store into least significant word of MTIMECMP + +auipc ra, 0x0 +addi ra, ra, 0xC // load address after wfi into ra so we return to the right place after handling the time interrupt + +wfi // test wfi until trap goes off + +li x28, 0x600d111 // magic number "good 111" to write to output after interrupt goes off. +// this tests whether wfi is a nop or not since we should get the output for the interrupt before this one +sd x28, 0(x6) +addi x6, x6, 8 +addi x16, x16, 8 + +END_TESTS + +TEST_STACK_AND_DATA + + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misa-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misa-01.S index 6e6a984ac..6aafa0098 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misa-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misa-01.S @@ -29,8 +29,8 @@ TRAP_HANDLER m // Test 5.3.2.2: Machine ISA register test -// Misa is a specific case *** so I don't want to add a whole test case for reading nonzero but unkown value CSRs. -csrr x30, misa // should not cause a fault in machine mode. *** not writing to output because MISA is different for different configs. +// Misa is a specific case so I don't want to add a whole test case for reading nonzero but unkown value CSRs. +csrr x30, misa // should not cause a fault in machine mode. not writing to output because MISA is different for different configs. li x7, 0x111 // success value for read of nonzero misa bnez x30, misa_nonzero li x7, 0xbad // misa was zero, store bad value diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mtvec-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mtvec-01.S index b90291bc8..4fa7e1c81 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mtvec-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mtvec-01.S @@ -25,20 +25,19 @@ INIT_TESTS +CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses + // test 5.3.1.5 Unvectored interrupt tests TRAP_HANDLER m, VECTORED=0, DEBUG=1 // turn off vectored interrupts, while turning on recording of mstatus bits. li x28, 0x8 -csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode -// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts +csrs mstatus, x28 // set sstatus.MIE bit to 1 +WRITE_READ_CSR mie, 0xFFF // cause traps, ensuring that we DONT go through the vectored part of the trap handler -// *** this assumes that interrupt code 0 remains reserved -// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. -// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken -// CAUSE_EXT_INTERRUPT +jal cause_m_time_interrupt // only cause one interrupt because we just want to test the status stack END_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-fp-disabled-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-fp-disabled-01.S new file mode 100644 index 000000000..2108d38e3 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-fp-disabled-01.S @@ -0,0 +1,49 @@ +/////////////////////////////////////////// +// +// WALLY-status-floating-point +// +// Author: Kip Macsai-Goren +// +// Created 2022-04-24 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-LIB-64.h" + +INIT_TESTS + +TRAP_HANDLER m + +// Misa.F is already 0 in this config, making floating point diabled + +li x28, 0x8000000000006000 // mask bits for SD and FS bits of status csr + +csrr x29, mstatus +and x29, x29, x28 +sd x29, 0(x6) // read disabled FS, SD bits, which should both be 0 +addi x6, x6, 8 +addi x16, x16, 8 + +csrs mstatus, x28 // attempt to write 11 and 1 to fs and sd in mstatus (this should not work) +csrr x29, mstatus +and x29, x29, x28 +sd x29, 0(x6) // read disabled FS, SD bits, which should both be 0 +addi x6, x6, 8 +addi x16, x16, 8 + +END_TESTS + +TEST_STACK_AND_DATA \ No newline at end of file diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-fp-enabled-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-fp-enabled-01.S new file mode 100644 index 000000000..6a3b53bea --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-fp-enabled-01.S @@ -0,0 +1,69 @@ +/////////////////////////////////////////// +// +// WALLY-status-floating-point +// +// Author: Kip Macsai-Goren +// +// Created 2022-04-24 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-LIB-64.h" + +INIT_TESTS + +TRAP_HANDLER m + +// Misa.F is already 1 in this config, making floating point enabled + +li x28, 0x8000000000006000 // mask bits for SD and FS bits of status csr + +csrr x29, mstatus +and x29, x29, x28 +sd x29, 0(x6) // read initial FS, SD bits, which should be 01 and 0 respectively +addi x6, x6, 8 +addi x16, x16, 8 + +flw f1, 0(x6) // make FS dirty by loading random value in + +csrr x29, mstatus +and x29, x29, x28 +sd x29, 0(x6) // read dirty FS, SD bits, which should be 11 and 1 respectively +addi x6, x6, 8 +addi x16, x16, 8 + +li x29, 0x4000 +csrs mstatus, x29 +li x29, 0x8000000000002000 +csrc mstatus, x29 // set SD to 0 and FS to 10 by writing mstatus + +csrr x29, mstatus +and x29, x29, x28 +sd x29, 0(x6) // read written FS, SD bits to confirm previous write +addi x6, x6, 8 +addi x16, x16, 8 + +flw f1, 0(x6) // make FS dirty by loading random value in + +csrr x29, mstatus +and x29, x29, x28 +sd x29, 0(x6) // read dirty FS, SD bits, which should be 11 and 1 respectively +addi x6, x6, 8 +addi x16, x16, 8 + +END_TESTS + +TEST_STACK_AND_DATA \ No newline at end of file diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-tw-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-tw-01.S new file mode 100644 index 000000000..dc1453e0a --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-tw-01.S @@ -0,0 +1,44 @@ +/////////////////////////////////////////// +// +// WALLY-status-timeout-wait +// +// Author: Kip Macsai-Goren +// +// Created 2022-04-24 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + + +#include "WALLY-TEST-LIB-64.h" + +INIT_TESTS + +TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps + +li x28, 0x200000 +csrs mstatus, x28 // set mstatus.TW bit to 1 + +GOTO_S_MODE // go to S mode so the TW can be triggered + +nop +nop +nop // let the ecall go through the pipeline before testing the wfi instruction +wfi // call wfi when there's no interrupt to wait for +// eventually should cause illegal instruction + +END_TESTS + +TEST_STACK_AND_DATA \ No newline at end of file diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S index 688c78910..802617b02 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S @@ -25,30 +25,29 @@ INIT_TESTS +CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses + // test 5.3.1.5 Unvectored interrupt tests +TRAP_HANDLER m, VECTORED=0, DEBUG=1 // necessary to handle changing modes TRAP_HANDLER s, VECTORED=0, DEBUG=1 // turn off vectored interrupts, while turning on recording of mstatus bits. -// li x28, 0x8 -// csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode -// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts - +li x28, 0x2 +csrs sstatus, x28 // set sstatus.SIE bit to 1 +WRITE_READ_CSR mie, 0xFFFF WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF +// cause traps, ensuring that we DONT go through the vectored part of the trap handler + GOTO_S_MODE -// cause traps, ensuring that we DONT go through the vectored part of the trap handler -// *** this assumes that interrupt code 0 remains reserved +jal cause_s_soft_interrupt // only cause one interrupt since we just want to test the tvec csr -// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. -// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken -// CAUSE_EXT_INTERRUPT +GOTO_M_MODE -GOTO_U_MODE +jal cause_s_soft_interrupt // set software interrupt pending without it firing so we can make it fire in U mode -// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. -// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken -// CAUSE_EXT_INTERRUPT +GOTO_U_MODE // Should cause software interrupt to fire off. END_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S index 45d34c344..22928eb54 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S @@ -31,11 +31,11 @@ TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps li x28, 0x8 csrs mstatus, x28 // set mstatus.MIE bit to 1 -WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources // *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts +WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources // test 5.3.1.4 Basic trap tests -// jal cause_instr_addr_misaligned //skipped becuase this exception may be impossible when compressed instructions are enabled) +jal cause_instr_addr_misaligned jal cause_instr_access jal cause_illegal_instr jal cause_breakpnt @@ -47,16 +47,21 @@ GOTO_U_MODE // Causes M mode ecall GOTO_S_MODE // Causes U mode ecall GOTO_M_MODE // Causes S mode ecall -jal cause_time_interrupt // *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. -jal cause_soft_interrupt // *** exiting out of the trap handler after these is current;y broken -jal cause_ext_interrupt + +jal cause_s_soft_interrupt +jal cause_m_soft_interrupt +jal cause_s_time_interrupt +jal cause_m_time_interrupt +jal cause_s_ext_interrupt_GPIO +jal cause_m_ext_interrupt + // try the traps again with mideleg = medeleg = all 1's to ensure traps still go to M mode from M mode WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF -// jal cause_instr_addr_misaligned //skipped becuase this exception may be impossible when compressed instructions are enabled) +jal cause_instr_addr_misaligned jal cause_instr_access jal cause_illegal_instr jal cause_breakpnt @@ -66,9 +71,16 @@ jal cause_store_addr_misaligned jal cause_store_acc jal cause_ecall // M mode ecall -jal cause_time_interrupt // *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. -jal cause_soft_interrupt // *** exiting out of the trap handler after these is current;y broken -jal cause_ext_interrupt +jal cause_s_soft_interrupt // The delegated S mode interrupts should not fire since we're running in M mode. +jal cause_m_soft_interrupt +jal cause_s_time_interrupt +jal cause_m_time_interrupt +li a3, 0x40 // these interrupts involve a time loop waiting for the interrupt to go off. +// since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3 +jal cause_s_ext_interrupt_GPIO +li a3, 0x40 +jal cause_m_ext_interrupt + END_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S index 9a813d9a2..8e72a6f1b 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S @@ -25,34 +25,42 @@ INIT_TESTS +CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses + // test 5.3.1.4 Basic trap tests -TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps +TRAP_HANDLER m, DEBUG=1 // necessary to handle switching privilege modes TRAP_HANDLER s, DEBUG=1 // have S mode trap handler as well // Like WALLY-trap, cause all the same traps from S mode and make sure they go to machine mode with zeroed mideleg, medeleg +li x28, 0x2 +csrs sstatus, x28 // set sstatus.SIE bit to 1 +WRITE_READ_CSR mie, 0xFFFF // sie is a subset of mie, so writing this also enables sie. + GOTO_S_MODE -li x28, 0x8 -csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode -// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts +jal cause_instr_addr_misaligned +jal cause_instr_access +jal cause_illegal_instr +jal cause_breakpnt +jal cause_load_addr_misaligned +jal cause_load_acc +jal cause_store_addr_misaligned +jal cause_store_acc +GOTO_U_MODE // Causes S mode ecall +GOTO_S_MODE // Causes U mode ecall -// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled) -CAUSE_INSTR_ACCESS -CAUSE_ILLEGAL_INSTR -CAUSE_BREAKPNT -CAUSE_LOAD_ADDR_MISALIGNED -CAUSE_LOAD_ACC -CAUSE_STORE_ADDR_MISALIGNED -CAUSE_STORE_ACC -CAUSE_ECALL - -// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. -// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken -// CAUSE_EXT_INTERRUPT - +// some interrupts excluded becaus writing MIP is illegal from S mode +jal cause_s_soft_interrupt +jal cause_m_soft_interrupt +jal cause_m_time_interrupt +li a3, 0x40 // this interrupt involves a time loop waiting for the interrupt to go off. +// since interrupts are not always enabled, +jal cause_s_ext_interrupt_GPIO +li a3, 0x40 +jal cause_m_ext_interrupt // Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler // We can tell which one becuase the different trap handler modes write different bits of the status register @@ -63,21 +71,23 @@ GOTO_M_MODE // so we can write the delegate registers WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF -GOTO_S_MODE +GOTO_S_MODE // Since we're running in M mode, this ecall will NOT be delegated to S mode -// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled) -CAUSE_INSTR_ACCESS -CAUSE_ILLEGAL_INSTR -CAUSE_BREAKPNT -CAUSE_LOAD_ADDR_MISALIGNED -CAUSE_LOAD_ACC -CAUSE_STORE_ADDR_MISALIGNED -CAUSE_STORE_ACC -CAUSE_ECALL +jal cause_instr_addr_misaligned +jal cause_instr_access +jal cause_illegal_instr +jal cause_breakpnt +jal cause_load_addr_misaligned +jal cause_load_acc +jal cause_store_addr_misaligned +jal cause_store_acc +GOTO_U_MODE // Causes S mode ecall +GOTO_S_MODE // Causes U mode ecall -// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. -// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken -// CAUSE_EXT_INTERRUPT +// M mode interrupts cannot be delegated in this implementation, so they are excluded from tests +jal cause_s_soft_interrupt +li a3, 0x40 +jal cause_s_ext_interrupt_GPIO END_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-sret-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-sret-01.S new file mode 100644 index 000000000..42690c798 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-sret-01.S @@ -0,0 +1,42 @@ +/////////////////////////////////////////// +// +// WALLY-trap-sret +// +// Author: Kip Macsai-Goren +// +// Created 2022-04-10 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-LIB-64.h" + +INIT_TESTS + +TRAP_HANDLER m, DEBUG=1 + +// test 5.3.1.6 Interrupt enabling and priority tests + +li x28, 0x400000 +csrs mstatus, x28 // Set mstatus.tsr to 1. + +GOTO_S_MODE + +sret // attempt to run sret instruction. +// should cause illegal instruction exception despite being in s mode + +END_TESTS + +TEST_STACK_AND_DATA diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S index 498c2ee3b..104e03f36 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S @@ -25,6 +25,8 @@ INIT_TESTS +CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses + // test 5.3.1.4 Basic trap tests TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps @@ -32,27 +34,30 @@ TRAP_HANDLER s, DEBUG=1 // have S mode trap handler as well // Like WALLY-trap, cause all the same traps from U mode and make sure they go to machine mode with zeroed mideleg, medeleg +li x28, 0x2 +csrs sstatus, x28 // set sstatus.SIE bit to 1. Not strictly necessary but this lets us differentiate which trap handler we went to +WRITE_READ_CSR mie, 0xFFFF + GOTO_U_MODE -// li x28, 0x8 -// csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode -// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts - - -// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled) -CAUSE_INSTR_ACCESS -CAUSE_ILLEGAL_INSTR -CAUSE_BREAKPNT -CAUSE_LOAD_ADDR_MISALIGNED -CAUSE_LOAD_ACC -CAUSE_STORE_ADDR_MISALIGNED -CAUSE_STORE_ACC -CAUSE_ECALL - -// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. -// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken -// CAUSE_EXT_INTERRUPT +jal cause_instr_addr_misaligned +jal cause_instr_access +jal cause_illegal_instr +jal cause_breakpnt +jal cause_load_addr_misaligned +jal cause_load_acc +jal cause_store_addr_misaligned +jal cause_store_acc +jal cause_ecall +// some interrupts excluded becaus writing SIP/MIP is illegal from U mode +jal cause_m_soft_interrupt +jal cause_m_time_interrupt +li a3, 0x40 // this interrupt involves a time loop waiting for the interrupt to go off. +// since interrupts are not always enabled, +jal cause_s_ext_interrupt_GPIO +li a3, 0x40 +jal cause_m_ext_interrupt // Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler // We can tell which one becuase the different trap handler modes write different bits of the status register @@ -65,19 +70,19 @@ WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF GOTO_U_MODE -// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled) -CAUSE_INSTR_ACCESS -CAUSE_ILLEGAL_INSTR -CAUSE_BREAKPNT -CAUSE_LOAD_ADDR_MISALIGNED -CAUSE_LOAD_ACC -CAUSE_STORE_ADDR_MISALIGNED -CAUSE_STORE_ACC -CAUSE_ECALL - -// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. -// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken -// CAUSE_EXT_INTERRUPT +jal cause_instr_addr_misaligned +jal cause_instr_access +jal cause_illegal_instr +jal cause_breakpnt +jal cause_load_addr_misaligned +jal cause_load_acc +jal cause_store_addr_misaligned +jal cause_store_acc +jal cause_ecall + +// M mode interrupts cannot be delegated in this implementation, so they are excluded from tests +li a3, 0x40 +jal cause_s_ext_interrupt_GPIO END_TESTS