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Added working trap test to regression, fixed hanfling of some interrupts

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Kip Macsai-Goren 2022-04-18 07:22:16 +00:00
parent 7d7e2ecc16
commit 64698aa806
5 changed files with 130 additions and 167 deletions
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2
pipelined/testbench/tests.vh
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@ -1471,7 +1471,7 @@ string imperas32f[] = '{
// "rv64i_m/privilege/WALLY-SCAUSE", "002090", // "rv64i_m/privilege/WALLY-SCAUSE", "002090",
// "rv64i_m/privilege/WALLY-scratch-01", "0040a0", // "rv64i_m/privilege/WALLY-scratch-01", "0040a0",
// "rv64i_m/privilege/WALLY-sscratch-s-01", "0040a0", // "rv64i_m/privilege/WALLY-sscratch-s-01", "0040a0",
// "rv64i_m/privilege/WALLY-trap-01", "0050a0", "rv64i_m/privilege/WALLY-trap-01", "0050a0",
"rv64i_m/privilege/WALLY-MIE-01", "0050a0", "rv64i_m/privilege/WALLY-MIE-01", "0050a0",
"rv64i_m/privilege/WALLY-mtvec-01", "0050a0", "rv64i_m/privilege/WALLY-mtvec-01", "0050a0",
"rv64i_m/privilege/WALLY-stvec-01", "0050a0", "rv64i_m/privilege/WALLY-stvec-01", "0050a0",

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag
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@ -65,7 +65,7 @@ target_tests_nosim = \
WALLY-PIE-stack-01 \ WALLY-PIE-stack-01 \
WALLY-PIE-stack-s-01 \ WALLY-PIE-stack-s-01 \
WALLY-trap-sret-01 \ WALLY-trap-sret-01 \
#WALLY-trap-01 \ WALLY-trap-01 \
# Have all 0's in references! # Have all 0's in references!
#WALLY-MEPC \ #WALLY-MEPC \
#WALLY-SEPC \ #WALLY-SEPC \

180
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output
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@ -1,5 +1,11 @@
00000aaa # Test 5.3.1.4: readback value from writing mie to enable interrupts 00000aaa # Test 5.3.1.4: readback value from writing mie to enable interrupts
00000000 00000000
00000000 # mcause from instruction addr misaligned fault
00000000
800003d2 # mtval of faulting instruction adress (0x800003d3)
00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000
00000001 # mcause from an instruction access fault 00000001 # mcause from an instruction access fault
00000000 00000000
00000000 # mtval of faulting instruction address (0x0) 00000000 # mtval of faulting instruction address (0x0)
@ -14,13 +20,13 @@
00000000 00000000
00000003 # mcause from Breakpoint 00000003 # mcause from Breakpoint
00000000 00000000
800003ec # mtval of breakpoint instruction adress (0x800003ec) 80000404 # mtval of breakpoint instruction adress (0x80000404)
00000000 00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000 00000000
00000004 # mcause from load address misaligned 00000004 # mcause from load address misaligned
00000000 00000000
800003f5 # mtval of misaligned address (0x800003f5) 8000040d # mtval of misaligned address (0x8000040d)
00000000 00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000 00000000
@ -32,7 +38,7 @@
00000000 00000000
00000006 # mcause from store misaligned 00000006 # mcause from store misaligned
00000000 00000000
80000411 # mtval of address with misaligned store instr (0x80000410) 80000429 # mtval of address with misaligned store instr (0x80000429)
00000000 00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000 00000000
@ -60,7 +66,31 @@
00000000 00000000
00000880 # masked out mstatus.MPP = 01 (from S mode), mstatus.MPIE = 1, and mstatus.MIE = 0 00000880 # masked out mstatus.MPP = 01 (from S mode), mstatus.MPIE = 1, and mstatus.MIE = 0
00000000 00000000
000007ec # value to indicate a vectored interrupts 0007ec01 # value to indicate successful vectoring on s soft interrupt
00000000
00000001 # mcause value from s soft interrupt
80000000
00000000 # mtval for ssoft interrupt (0x0)
00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000
0007ec03 # value to indicate successful vectoring on m soft interrupt
00000000
00000003 # mcause value from m soft interrupt
80000000
00000000 # mtval for msoft interrupt (0x0)
00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000
0007ec05 # value to indicate successful vectoring on s time interrupt
00000000
00000005 # mcause value from s time interrupt
80000000
00000000 # mtval for stime interrupt (0x0)
00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000
0007ec07 # value to indicate successful vectoring on m time interrupt
00000000 00000000
00000007 # mcause value from m time interrupt 00000007 # mcause value from m time interrupt
80000000 80000000
@ -68,15 +98,15 @@
00000000 00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000 00000000
000007ec # value to indicate a vectored interrupts 0007ec09 # value to indicate successful vectoring on s ext interrupt
00000000 00000000
00000001 # mcause value from m soft interrupt 00000009 # mcause value from s ext interrupt
80000000 80000000
00000000 # mtval for msoft interrupt (0x0) 00000000 # mtval for sext interrupt (0x0)
00000000 00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000 00000000
000007ec # value to indicate a vectored interrupts 0007ec0b # value to indicate successful vectoring on m ext interrupt
00000000 00000000
0000000b # mcause value from m ext interrupt 0000000b # mcause value from m ext interrupt
80000000 80000000
@ -84,11 +114,17 @@
00000000 00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000 00000000
0000b309 # medeleg after attempted write of all 1's (only some bits are writeable) fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable)
00000000 ffffffff
00000222 # mideleg after attempted write of all 1's (only some bits are writeable) 00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
00000000 00000000
00000001 # Test 5.3.1.4: mcause from an instruction access fault 00000000 # mcause from instruction addr misaligned fault
00000000
800003d2 # mtval of faulting instruction adress (0x800003d3)
00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000
00000001 # mcause from an instruction access fault
00000000 00000000
00000000 # mtval of faulting instruction address (0x0) 00000000 # mtval of faulting instruction address (0x0)
00000000 00000000
@ -102,13 +138,13 @@
00000000 00000000
00000003 # mcause from Breakpoint 00000003 # mcause from Breakpoint
00000000 00000000
800003ec # mtval of breakpoint instruction adress (0x800003ec) 80000404 # mtval of breakpoint instruction adress (0x80000404)
00000000 00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000 00000000
00000004 # mcause from load address misaligned 00000004 # mcause from load address misaligned
00000000 00000000
800003f5 # mtval of misaligned address (0x800003f5) 8000040d # mtval of misaligned address (0x8000040d)
00000000 00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000 00000000
@ -120,7 +156,7 @@
00000000 00000000
00000006 # mcause from store misaligned 00000006 # mcause from store misaligned
00000000 00000000
80000411 # mtval of address with misaligned store instr (0x80000410) 80000429 # mtval of address with misaligned store instr (0x80000429)
00000000 00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000 00000000
@ -136,23 +172,23 @@
00000000 00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000 00000000
000007ec # value to indicate a vectored interrupts 0007ec03 # value to indicate successful vectoring on m soft interrupt
00000000 00000000
00000007 # mcause value from time interrupt 00000003 # mcause value from m soft interrupt
80000000
00000000 # mtval for mtime interrupt (0x0)
00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000
000007ec # value to indicate a vectored interrupts
00000000
00000001 # mcause value from m soft interrupt
80000000 80000000
00000000 # mtval for msoft interrupt (0x0) 00000000 # mtval for msoft interrupt (0x0)
00000000 00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000 00000000
000007ec # value to indicate a vectored interrupts 0007ec07 # value to indicate successful vectoring on m time interrupt
00000000
00000007 # mcause value from m time interrupt
80000000
00000000 # mtval for mtime interrupt (0x0)
00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000
0007ec0b # value to indicate successful vectoring on m ext interrupt
00000000 00000000
0000000b # mcause value from m ext interrupt 0000000b # mcause value from m ext interrupt
80000000 80000000
@ -978,97 +1014,3 @@ deadbeef
deadbeef deadbeef
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deadbeef

85
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h
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@ -157,17 +157,17 @@ cause_s_soft_interrupt:
cause_m_ext_interrupt: cause_m_ext_interrupt:
# ========== Configure PLIC ========== # ========== Configure PLIC ==========
# m priority threshold = 0 # m priority threshold = 0
li t0, 0xC200000 li x28, 0xC200000
li t1, 0 li x29, 0
sw t1, 0(t0) sw x29, 0(x28)
# source 3 (GPIO) priority = 1 # source 3 (GPIO) priority = 1
li t0, 0xC000000 li x28, 0xC000000
li t1, 1 li x29, 1
sw t1, 0x0C(t0) sw x29, 0x0C(x28)
# enable source 3 # enable source 3 in M Mode
li t0, 0x0C002000 li x28, 0x0C002000
li t1, 0b1000 li x29, 0b1000
sw t1, 0(t0) sw x29, 0(x28)
li x28, 0x10060000 // load base GPIO memory location li x28, 0x10060000 // load base GPIO memory location
li x29, 0x1 li x29, 0x1
@ -178,7 +178,7 @@ cause_m_ext_interrupt:
sw x0, 0x2C(x28) // clear high_ip sw x0, 0x2C(x28) // clear high_ip
sw x0, 0x34(x28) // clear low_ip sw x0, 0x34(x28) // clear low_ip
sw x29, 0x28(x28) // set first to interrupt on a rising value sw x29, 0x28(x28) // set first pin to interrupt on a rising value
sw x29, 0x0C(x28) // write a 1 to the first output pin (cause interrupt) sw x29, 0x0C(x28) // write a 1 to the first output pin (cause interrupt)
m_ext_loop: m_ext_loop:
wfi wfi
@ -189,21 +189,21 @@ m_ext_loop:
cause_s_ext_interrupt_GPIO: cause_s_ext_interrupt_GPIO:
# ========== Configure PLIC ========== # ========== Configure PLIC ==========
# s priority threshold = 0 # s priority threshold = 0
li t0, 0xC201000 li x28, 0xC201000
li t1, 0 li x29, 0
sw t1, 0(t0) sw x29, 0(x28)
# m priority threshold = 7 # m priority threshold = 7
li t0, 0xC200000 li x28, 0xC200000
li t1, 7 li x29, 7
sw t1, 0(t0) sw x29, 0(x28)
# source 3 (GPIO) priority = 1 # source 3 (GPIO) priority = 1
li t0, 0xC000000 li x28, 0xC000000
li t1, 1 li x29, 1
sw t1, 0x0C(t0) sw x29, 0x0C(x28)
# enable source 3 # enable source 3 in S mode
li t0, 0x0C002000 li x28, 0x0C002080
li t1, 0b1000 li x29, 0b1000
sw t1, 0(t0) sw x29, 0(x28)
li x28, 0x10060000 // load base GPIO memory location li x28, 0x10060000 // load base GPIO memory location
li x29, 0x1 li x29, 0x1
@ -214,7 +214,7 @@ cause_s_ext_interrupt_GPIO:
sw x0, 0x2C(x28) // clear high_ip sw x0, 0x2C(x28) // clear high_ip
sw x0, 0x34(x28) // clear low_ip sw x0, 0x34(x28) // clear low_ip
sw x29, 0x28(x28) // set first to interrupt on a rising value sw x29, 0x28(x28) // set first pin to interrupt on a rising value
sw x29, 0x0C(x28) // write a 1 to the first output pin (cause interrupt) sw x29, 0x0C(x28) // write a 1 to the first output pin (cause interrupt)
s_ext_loop: s_ext_loop:
wfi wfi
@ -224,7 +224,7 @@ s_ext_loop:
cause_s_ext_interrupt_IP: cause_s_ext_interrupt_IP:
li x28, 0x200 li x28, 0x200
csrs mip, x28 // set supervisor external interrupt pending. SIP is a subset of MIP, so writing this should also change MIP. csrs mip, x28 // set supervisor external interrupt pending.
ret ret
end_trap_triggers: end_trap_triggers:
@ -521,18 +521,19 @@ soft_interrupt_\MODE\():
la x5, 0x02000000 // Reset by clearing MSIP interrupt from CLINT la x5, 0x02000000 // Reset by clearing MSIP interrupt from CLINT
sw x0, 0(x5) sw x0, 0(x5)
csrci sip, 0x2 // clear supervisor software interrupt pending bit csrci \MODE\()ip, 0x2 // clear supervisor software interrupt pending bit
ld x1, -8(sp) // load return address from stack into ra (the address to return to after causing this interrupt) ld x1, -8(sp) // load return address from stack into ra (the address to return to after causing this interrupt)
// Note: we do this because the mepc loads in the address of the instruction after the sw that causes the interrupt // Note: we do this because the mepc loads in the address of the instruction after the sw that causes the interrupt
// This means that this trap handler will return to the next address after that one, which might be unpredictable behavior. // This means that this trap handler will return to the next address after that one, which might be unpredictable behavior.
j trapreturn_finished_\MODE\() // return to the code at ra value from before trap j trapreturn_finished_\MODE\() // return to the code at ra value from before trap
time_interrupt_\MODE\(): time_interrupt_\MODE\():
la x5, 0x02004000 // MTIMECMP register in CLINT la x5, 0x02004000 // MTIMECMP register in CLINT
li x7, 0xFFFFFFFF li x7, 0xFFFFFFFF
sd x7, 0(x5) // reset interrupt by setting mtimecmp to 0xFFFFFFFF sd x7, 0(x5) // reset interrupt by setting mtimecmp to 0xFFFFFFFF
li x5, 0x20
csrc \MODE\()ip, x5
ld x1, -8(sp) // load return address from stack into ra (the address to return to after the loop is complete) ld x1, -8(sp) // load return address from stack into ra (the address to return to after the loop is complete)
j trapreturn_finished_\MODE\() // return to the code at ra value from before trap j trapreturn_finished_\MODE\() // return to the code at ra value from before trap
@ -543,18 +544,26 @@ ext_interrupt_\MODE\():
# reset PLIC to turn off external interrupts # reset PLIC to turn off external interrupts
# priority threshold = 7 # priority threshold = 7
li t0, 0xC200000 li x28, 0xC200000
li t1, 0x7 li x5, 0x7
sw t1, 0(t0) sw x5, 0(x28)
# source 3 (GPIO) priority = 0 # source 3 (GPIO) priority = 0
li t0, 0xC000000 li x28, 0xC000000
li t1, 0 li x5, 0
sw t1, 0x0C(t0) sw x5, 0x0C(x28)
# disable source 3 # disable source 3
li t0, 0x0C002000 li x28, 0x0C002000
li t1, 0b0000 li x5, 0b0000
sw t1, 0(t0) sw x5, 0(x28)
j trapreturn_\MODE\()
li x5, 0x200
csrc \MODE\()ip, x5
ld x1, -8(sp) // load return address from stack into ra (the address to return to after the loop is complete)
j trapreturn_finished_\MODE\() // return to the code at ra value from before trap
// Table of trap behavior // Table of trap behavior
// lists what to do on each exception (not interrupts) // lists what to do on each exception (not interrupts)

28
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S
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@ -35,7 +35,7 @@ WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources // *** commented
// test 5.3.1.4 Basic trap tests // test 5.3.1.4 Basic trap tests
// jal cause_instr_addr_misaligned //skipped becuase this exception may be impossible when compressed instructions are enabled) jal cause_instr_addr_misaligned
jal cause_instr_access jal cause_instr_access
jal cause_illegal_instr jal cause_illegal_instr
jal cause_breakpnt jal cause_breakpnt
@ -47,16 +47,23 @@ GOTO_U_MODE // Causes M mode ecall
GOTO_S_MODE // Causes U mode ecall GOTO_S_MODE // Causes U mode ecall
GOTO_M_MODE // Causes S mode ecall GOTO_M_MODE // Causes S mode ecall
jal cause_time_interrupt // *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
jal cause_soft_interrupt // *** exiting out of the trap handler after these is current;y broken jal cause_s_soft_interrupt
jal cause_ext_interrupt jal cause_m_soft_interrupt
jal cause_s_time_interrupt
jal cause_m_time_interrupt
//jal cause_s_ext_interrupt_GPIO
jal cause_s_ext_interrupt_IP // cause external interrupt with both sip register and GPIO.
jal cause_m_ext_interrupt
// try the traps again with mideleg = medeleg = all 1's to ensure traps still go to M mode from M mode // try the traps again with mideleg = medeleg = all 1's to ensure traps still go to M mode from M mode
WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF
WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
// jal cause_instr_addr_misaligned //skipped becuase this exception may be impossible when compressed instructions are enabled) jal cause_instr_addr_misaligned
jal cause_instr_access jal cause_instr_access
jal cause_illegal_instr jal cause_illegal_instr
jal cause_breakpnt jal cause_breakpnt
@ -66,9 +73,14 @@ jal cause_store_addr_misaligned
jal cause_store_acc jal cause_store_acc
jal cause_ecall // M mode ecall jal cause_ecall // M mode ecall
jal cause_time_interrupt // *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. jal cause_s_soft_interrupt // The delegated S mode interrupts should not fire since we're running in M mode.
jal cause_soft_interrupt // *** exiting out of the trap handler after these is current;y broken jal cause_m_soft_interrupt
jal cause_ext_interrupt jal cause_s_time_interrupt
jal cause_m_time_interrupt
//jal cause_s_ext_interrupt_GPIO
jal cause_s_ext_interrupt_IP // cause external interrupt with both sip register and GPIO.
jal cause_m_ext_interrupt
END_TESTS END_TESTS