From 64698aa806962b3cabfd74846770c7efdb42f8be Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Mon, 18 Apr 2022 07:22:16 +0000 Subject: [PATCH] Added working trap test to regression, fixed hanfling of some interrupts --- pipelined/testbench/tests.vh | 2 +- .../rv64i_m/privilege/Makefrag | 2 +- .../references/WALLY-trap-01.reference_output | 180 ++++++------------ .../rv64i_m/privilege/src/WALLY-TEST-LIB-64.h | 85 +++++---- .../rv64i_m/privilege/src/WALLY-trap-01.S | 28 ++- 5 files changed, 130 insertions(+), 167 deletions(-) diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index 621b5f867..277c4d6c8 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -1471,7 +1471,7 @@ string imperas32f[] = '{ // "rv64i_m/privilege/WALLY-SCAUSE", "002090", // "rv64i_m/privilege/WALLY-scratch-01", "0040a0", // "rv64i_m/privilege/WALLY-sscratch-s-01", "0040a0", -// "rv64i_m/privilege/WALLY-trap-01", "0050a0", + "rv64i_m/privilege/WALLY-trap-01", "0050a0", "rv64i_m/privilege/WALLY-MIE-01", "0050a0", "rv64i_m/privilege/WALLY-mtvec-01", "0050a0", "rv64i_m/privilege/WALLY-stvec-01", "0050a0", diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag index 55f2dad6f..7e6fdc8ff 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag @@ -65,7 +65,7 @@ target_tests_nosim = \ WALLY-PIE-stack-01 \ WALLY-PIE-stack-s-01 \ WALLY-trap-sret-01 \ - #WALLY-trap-01 \ + WALLY-trap-01 \ # Have all 0's in references! #WALLY-MEPC \ #WALLY-SEPC \ diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output index eef583deb..8165e85c7 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output @@ -1,5 +1,11 @@ 00000aaa # Test 5.3.1.4: readback value from writing mie to enable interrupts 00000000 +00000000 # mcause from instruction addr misaligned fault +00000000 +800003d2 # mtval of faulting instruction adress (0x800003d3) +00000000 +00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 +00000000 00000001 # mcause from an instruction access fault 00000000 00000000 # mtval of faulting instruction address (0x0) @@ -14,13 +20,13 @@ 00000000 00000003 # mcause from Breakpoint 00000000 -800003ec # mtval of breakpoint instruction adress (0x800003ec) +80000404 # mtval of breakpoint instruction adress (0x80000404) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 00000004 # mcause from load address misaligned 00000000 -800003f5 # mtval of misaligned address (0x800003f5) +8000040d # mtval of misaligned address (0x8000040d) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 @@ -32,7 +38,7 @@ 00000000 00000006 # mcause from store misaligned 00000000 -80000411 # mtval of address with misaligned store instr (0x80000410) +80000429 # mtval of address with misaligned store instr (0x80000429) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 @@ -60,7 +66,31 @@ 00000000 00000880 # masked out mstatus.MPP = 01 (from S mode), mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 -000007ec # value to indicate a vectored interrupts +0007ec01 # value to indicate successful vectoring on s soft interrupt +00000000 +00000001 # mcause value from s soft interrupt +80000000 +00000000 # mtval for ssoft interrupt (0x0) +00000000 +00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 +00000000 +0007ec03 # value to indicate successful vectoring on m soft interrupt +00000000 +00000003 # mcause value from m soft interrupt +80000000 +00000000 # mtval for msoft interrupt (0x0) +00000000 +00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 +00000000 +0007ec05 # value to indicate successful vectoring on s time interrupt +00000000 +00000005 # mcause value from s time interrupt +80000000 +00000000 # mtval for stime interrupt (0x0) +00000000 +00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 +00000000 +0007ec07 # value to indicate successful vectoring on m time interrupt 00000000 00000007 # mcause value from m time interrupt 80000000 @@ -68,15 +98,15 @@ 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 -000007ec # value to indicate a vectored interrupts +0007ec09 # value to indicate successful vectoring on s ext interrupt 00000000 -00000001 # mcause value from m soft interrupt +00000009 # mcause value from s ext interrupt 80000000 -00000000 # mtval for msoft interrupt (0x0) +00000000 # mtval for sext interrupt (0x0) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 -000007ec # value to indicate a vectored interrupts +0007ec0b # value to indicate successful vectoring on m ext interrupt 00000000 0000000b # mcause value from m ext interrupt 80000000 @@ -84,11 +114,17 @@ 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 -0000b309 # medeleg after attempted write of all 1's (only some bits are writeable) -00000000 +fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable) +ffffffff 00000222 # mideleg after attempted write of all 1's (only some bits are writeable) 00000000 -00000001 # Test 5.3.1.4: mcause from an instruction access fault +00000000 # mcause from instruction addr misaligned fault +00000000 +800003d2 # mtval of faulting instruction adress (0x800003d3) +00000000 +00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 +00000000 +00000001 # mcause from an instruction access fault 00000000 00000000 # mtval of faulting instruction address (0x0) 00000000 @@ -102,13 +138,13 @@ 00000000 00000003 # mcause from Breakpoint 00000000 -800003ec # mtval of breakpoint instruction adress (0x800003ec) +80000404 # mtval of breakpoint instruction adress (0x80000404) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 00000004 # mcause from load address misaligned 00000000 -800003f5 # mtval of misaligned address (0x800003f5) +8000040d # mtval of misaligned address (0x8000040d) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 @@ -120,7 +156,7 @@ 00000000 00000006 # mcause from store misaligned 00000000 -80000411 # mtval of address with misaligned store instr (0x80000410) +80000429 # mtval of address with misaligned store instr (0x80000429) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 @@ -136,23 +172,23 @@ 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 -000007ec # value to indicate a vectored interrupts +0007ec03 # value to indicate successful vectoring on m soft interrupt 00000000 -00000007 # mcause value from time interrupt -80000000 -00000000 # mtval for mtime interrupt (0x0) -00000000 -00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 -00000000 -000007ec # value to indicate a vectored interrupts -00000000 -00000001 # mcause value from m soft interrupt +00000003 # mcause value from m soft interrupt 80000000 00000000 # mtval for msoft interrupt (0x0) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 -000007ec # value to indicate a vectored interrupts +0007ec07 # value to indicate successful vectoring on m time interrupt +00000000 +00000007 # mcause value from m time interrupt +80000000 +00000000 # mtval for mtime interrupt (0x0) +00000000 +00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 +00000000 +0007ec0b # value to indicate successful vectoring on m ext interrupt 00000000 0000000b # mcause value from m ext interrupt 80000000 @@ -978,97 +1014,3 @@ deadbeef deadbeef deadbeef deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef -deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h index 60f793f56..c9ae5cf04 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h @@ -157,17 +157,17 @@ cause_s_soft_interrupt: cause_m_ext_interrupt: # ========== Configure PLIC ========== # m priority threshold = 0 - li t0, 0xC200000 - li t1, 0 - sw t1, 0(t0) + li x28, 0xC200000 + li x29, 0 + sw x29, 0(x28) # source 3 (GPIO) priority = 1 - li t0, 0xC000000 - li t1, 1 - sw t1, 0x0C(t0) - # enable source 3 - li t0, 0x0C002000 - li t1, 0b1000 - sw t1, 0(t0) + li x28, 0xC000000 + li x29, 1 + sw x29, 0x0C(x28) + # enable source 3 in M Mode + li x28, 0x0C002000 + li x29, 0b1000 + sw x29, 0(x28) li x28, 0x10060000 // load base GPIO memory location li x29, 0x1 @@ -178,7 +178,7 @@ cause_m_ext_interrupt: sw x0, 0x2C(x28) // clear high_ip sw x0, 0x34(x28) // clear low_ip - sw x29, 0x28(x28) // set first to interrupt on a rising value + sw x29, 0x28(x28) // set first pin to interrupt on a rising value sw x29, 0x0C(x28) // write a 1 to the first output pin (cause interrupt) m_ext_loop: wfi @@ -189,21 +189,21 @@ m_ext_loop: cause_s_ext_interrupt_GPIO: # ========== Configure PLIC ========== # s priority threshold = 0 - li t0, 0xC201000 - li t1, 0 - sw t1, 0(t0) + li x28, 0xC201000 + li x29, 0 + sw x29, 0(x28) # m priority threshold = 7 - li t0, 0xC200000 - li t1, 7 - sw t1, 0(t0) + li x28, 0xC200000 + li x29, 7 + sw x29, 0(x28) # source 3 (GPIO) priority = 1 - li t0, 0xC000000 - li t1, 1 - sw t1, 0x0C(t0) - # enable source 3 - li t0, 0x0C002000 - li t1, 0b1000 - sw t1, 0(t0) + li x28, 0xC000000 + li x29, 1 + sw x29, 0x0C(x28) + # enable source 3 in S mode + li x28, 0x0C002080 + li x29, 0b1000 + sw x29, 0(x28) li x28, 0x10060000 // load base GPIO memory location li x29, 0x1 @@ -214,7 +214,7 @@ cause_s_ext_interrupt_GPIO: sw x0, 0x2C(x28) // clear high_ip sw x0, 0x34(x28) // clear low_ip - sw x29, 0x28(x28) // set first to interrupt on a rising value + sw x29, 0x28(x28) // set first pin to interrupt on a rising value sw x29, 0x0C(x28) // write a 1 to the first output pin (cause interrupt) s_ext_loop: wfi @@ -224,7 +224,7 @@ s_ext_loop: cause_s_ext_interrupt_IP: li x28, 0x200 - csrs mip, x28 // set supervisor external interrupt pending. SIP is a subset of MIP, so writing this should also change MIP. + csrs mip, x28 // set supervisor external interrupt pending. ret end_trap_triggers: @@ -521,18 +521,19 @@ soft_interrupt_\MODE\(): la x5, 0x02000000 // Reset by clearing MSIP interrupt from CLINT sw x0, 0(x5) - csrci sip, 0x2 // clear supervisor software interrupt pending bit + csrci \MODE\()ip, 0x2 // clear supervisor software interrupt pending bit ld x1, -8(sp) // load return address from stack into ra (the address to return to after causing this interrupt) // Note: we do this because the mepc loads in the address of the instruction after the sw that causes the interrupt // This means that this trap handler will return to the next address after that one, which might be unpredictable behavior. j trapreturn_finished_\MODE\() // return to the code at ra value from before trap - time_interrupt_\MODE\(): la x5, 0x02004000 // MTIMECMP register in CLINT li x7, 0xFFFFFFFF sd x7, 0(x5) // reset interrupt by setting mtimecmp to 0xFFFFFFFF + li x5, 0x20 + csrc \MODE\()ip, x5 ld x1, -8(sp) // load return address from stack into ra (the address to return to after the loop is complete) j trapreturn_finished_\MODE\() // return to the code at ra value from before trap @@ -543,18 +544,26 @@ ext_interrupt_\MODE\(): # reset PLIC to turn off external interrupts # priority threshold = 7 - li t0, 0xC200000 - li t1, 0x7 - sw t1, 0(t0) + li x28, 0xC200000 + li x5, 0x7 + sw x5, 0(x28) # source 3 (GPIO) priority = 0 - li t0, 0xC000000 - li t1, 0 - sw t1, 0x0C(t0) + li x28, 0xC000000 + li x5, 0 + sw x5, 0x0C(x28) # disable source 3 - li t0, 0x0C002000 - li t1, 0b0000 - sw t1, 0(t0) - j trapreturn_\MODE\() + li x28, 0x0C002000 + li x5, 0b0000 + sw x5, 0(x28) + + li x5, 0x200 + csrc \MODE\()ip, x5 + + ld x1, -8(sp) // load return address from stack into ra (the address to return to after the loop is complete) + j trapreturn_finished_\MODE\() // return to the code at ra value from before trap + + + // Table of trap behavior // lists what to do on each exception (not interrupts) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S index 45d34c344..17100fbbe 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S @@ -35,7 +35,7 @@ WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources // *** commented // test 5.3.1.4 Basic trap tests -// jal cause_instr_addr_misaligned //skipped becuase this exception may be impossible when compressed instructions are enabled) +jal cause_instr_addr_misaligned jal cause_instr_access jal cause_illegal_instr jal cause_breakpnt @@ -47,16 +47,23 @@ GOTO_U_MODE // Causes M mode ecall GOTO_S_MODE // Causes U mode ecall GOTO_M_MODE // Causes S mode ecall -jal cause_time_interrupt // *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. -jal cause_soft_interrupt // *** exiting out of the trap handler after these is current;y broken -jal cause_ext_interrupt + +jal cause_s_soft_interrupt +jal cause_m_soft_interrupt +jal cause_s_time_interrupt +jal cause_m_time_interrupt +//jal cause_s_ext_interrupt_GPIO +jal cause_s_ext_interrupt_IP // cause external interrupt with both sip register and GPIO. +jal cause_m_ext_interrupt + + // try the traps again with mideleg = medeleg = all 1's to ensure traps still go to M mode from M mode WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF -// jal cause_instr_addr_misaligned //skipped becuase this exception may be impossible when compressed instructions are enabled) +jal cause_instr_addr_misaligned jal cause_instr_access jal cause_illegal_instr jal cause_breakpnt @@ -66,9 +73,14 @@ jal cause_store_addr_misaligned jal cause_store_acc jal cause_ecall // M mode ecall -jal cause_time_interrupt // *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. -jal cause_soft_interrupt // *** exiting out of the trap handler after these is current;y broken -jal cause_ext_interrupt +jal cause_s_soft_interrupt // The delegated S mode interrupts should not fire since we're running in M mode. +jal cause_m_soft_interrupt +jal cause_s_time_interrupt +jal cause_m_time_interrupt +//jal cause_s_ext_interrupt_GPIO +jal cause_s_ext_interrupt_IP // cause external interrupt with both sip register and GPIO. +jal cause_m_ext_interrupt + END_TESTS