From 642efbb563ca67b8f34f1a616f06e25b8a09119a Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 26 Aug 2021 10:41:42 -0500 Subject: [PATCH] Converted the icache type from logic to state type. --- wally-pipelined/regression/wave.do | 58 +++++++---------- wally-pipelined/src/cache/ICacheCntrl.sv | 83 ++++++++++++------------ wally-pipelined/src/cache/icache.sv | 39 +++++++++-- 3 files changed, 97 insertions(+), 83 deletions(-) diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index a12e5cda8..48efbe285 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -314,8 +314,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM w add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearValid add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/SetDirty add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearDirty -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/genblk1/cacheLRU/MemPAdrM add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ReadDataBlockWayMaskedM} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WayHit} add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Valid} @@ -340,31 +338,29 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM r add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordMuxM -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/genblk1/cacheLRU/BlockReplacementBits -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/genblk1/cacheLRU/ReplacementBits -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimTag -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimWay -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataM -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group status /testbench/dut/hart/lsu/dcache/WayHit -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group status /testbench/dut/hart/lsu/dcache/FetchCount -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimTag +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataM +add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall +add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit +add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit +add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/FetchCount +add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr +add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead +add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite +add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck +add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA +add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation @@ -476,16 +472,10 @@ add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HSELUART add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HADDR add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWRITE add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWDATA -add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/HRDATA -add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/HSIZED add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/offset0 add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/offset1 add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/offset2 add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/offset3 -add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/genblk1/offset4 -add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/genblk1/offset5 -add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/genblk1/offset6 -add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/genblk1/offset7 add wave -noupdate /testbench/dut/hart/ExceptionM add wave -noupdate /testbench/dut/hart/PendingInterruptM add wave -noupdate /testbench/dut/hart/TrapM @@ -506,4 +496,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {1280 ns} {3534 ns} +WaveRestoreZoom {0 ns} {325837 ns} diff --git a/wally-pipelined/src/cache/ICacheCntrl.sv b/wally-pipelined/src/cache/ICacheCntrl.sv index 3881e9cb6..fc08f2d4f 100644 --- a/wally-pipelined/src/cache/ICacheCntrl.sv +++ b/wally-pipelined/src/cache/ICacheCntrl.sv @@ -71,51 +71,51 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) ); // FSM states - localparam STATE_READY = 'h0; - localparam STATE_HIT_SPILL = 'h1; // spill, block 0 hit - localparam STATE_HIT_SPILL_MISS_FETCH_WDV = 'h2; // block 1 miss, issue read to AHB and wait data. - localparam STATE_HIT_SPILL_MISS_FETCH_DONE = 'h3; // write data into SRAM/LUT - localparam STATE_HIT_SPILL_MERGE = 'h4; // Read block 0 of CPU access, should be able to optimize into STATE_HIT_SPILL. + typedef enum {STATE_READY, + STATE_HIT_SPILL, // spill, block 0 hit + STATE_HIT_SPILL_MISS_FETCH_WDV, // block 1 miss, issue read to AHB and wait data. + STATE_HIT_SPILL_MISS_FETCH_DONE, // write data into SRAM/LUT + STATE_HIT_SPILL_MERGE, // Read block 0 of CPU access, should be able to optimize into STATE_HIT_SPILL. - // a challenge is the spill signal gets us out of the ready state and moves us to - // 1 of the 2 spill branches. However the original fsm design had us return to - // the ready state when the spill + hits/misses were fully resolved. The problem - // is the spill signal is based on PCPF so when we return to READY to check if the - // cache has a hit it still expresses spill. We can fix in 1 of two ways. - // 1. we can add 1 extra state at the end of each spill branch to returns the instruction - // to the CPU advancing the CPU and icache to the next instruction. - // 2. We can assert a signal which is delayed 1 cycle to suppress the spill when we get - // to the READY state. - // The first first option is more robust and increases the number of states by 2. The - // second option is seams like it should work, but I worry there is a hidden interaction - // between CPU stalling and that register. - // Picking option 1. + // a challenge is the spill signal gets us out of the ready state and moves us to + // 1 of the 2 spill branches. However the original fsm design had us return to + // the ready state when the spill + hits/misses were fully resolved. The problem + // is the spill signal is based on PCPF so when we return to READY to check if the + // cache has a hit it still expresses spill. We can fix in 1 of two ways. + // 1. we can add 1 extra state at the end of each spill branch to returns the instruction + // to the CPU advancing the CPU and icache to the next instruction. + // 2. We can assert a signal which is delayed 1 cycle to suppress the spill when we get + // to the READY state. + // The first first option is more robust and increases the number of states by 2. The + // second option is seams like it should work, but I worry there is a hidden interaction + // between CPU stalling and that register. + // Picking option 1. - localparam STATE_HIT_SPILL_FINAL = 'h5; // this state replicates STATE_READY's replay of the - // spill access but does nto consider spill. It also does not do another operation. + STATE_HIT_SPILL_FINAL, // this state replicates STATE_READY's replay of the + // spill access but does nto consider spill. It also does not do another operation. + STATE_MISS_FETCH_WDV, // aligned miss, issue read to AHB and wait for data. + STATE_MISS_FETCH_DONE, // write data into SRAM/LUT + STATE_MISS_READ, // read block 1 from SRAM/LUT - localparam STATE_MISS_FETCH_WDV = 'h6; // aligned miss, issue read to AHB and wait for data. - localparam STATE_MISS_FETCH_DONE = 'h7; // write data into SRAM/LUT - localparam STATE_MISS_READ = 'h8; // read block 1 from SRAM/LUT + STATE_MISS_SPILL_FETCH_WDV, // spill, miss on block 0, issue read to AHB and wait + STATE_MISS_SPILL_FETCH_DONE, // write data into SRAM/LUT + STATE_MISS_SPILL_READ1, // read block 0 from SRAM/LUT + STATE_MISS_SPILL_2, // return to ready if hit or do second block update. + STATE_MISS_SPILL_2_START, // return to ready if hit or do second block update. + STATE_MISS_SPILL_MISS_FETCH_WDV, // miss on block 1, issue read to AHB and wait + STATE_MISS_SPILL_MISS_FETCH_DONE, // write data to SRAM/LUT + STATE_MISS_SPILL_MERGE, // read block 0 of CPU access, - localparam STATE_MISS_SPILL_FETCH_WDV = 'h9; // spill, miss on block 0, issue read to AHB and wait - localparam STATE_MISS_SPILL_FETCH_DONE = 'ha; // write data into SRAM/LUT - localparam STATE_MISS_SPILL_READ1 = 'hb; // read block 0 from SRAM/LUT - localparam STATE_MISS_SPILL_2 = 'hc; // return to ready if hit or do second block update. - localparam STATE_MISS_SPILL_2_START = 'hd; // return to ready if hit or do second block update. - localparam STATE_MISS_SPILL_MISS_FETCH_WDV = 'he; // miss on block 1, issue read to AHB and wait - localparam STATE_MISS_SPILL_MISS_FETCH_DONE = 'hf; // write data to SRAM/LUT - localparam STATE_MISS_SPILL_MERGE = 'h10; // read block 0 of CPU access, + STATE_MISS_SPILL_FINAL, // this state replicates STATE_READY's replay of the + // spill access but does nto consider spill. It also does not do another operation. - localparam STATE_MISS_SPILL_FINAL = 'h11; // this state replicates STATE_READY's replay of the - // spill access but does nto consider spill. It also does not do another operation. + STATE_INVALIDATE, // *** not sure if invalidate or evict? invalidate by cache block or address? + STATE_TLB_MISS, + STATE_TLB_MISS_DONE + } statetype; - localparam STATE_INVALIDATE = 'h12; // *** not sure if invalidate or evict? invalidate by cache block or address? - localparam STATE_TLB_MISS = 'h13; - localparam STATE_TLB_MISS_DONE = 'h14; - localparam AHBByteLength = `XLEN / 8; localparam AHBOFFETWIDTH = $clog2(AHBByteLength); @@ -129,7 +129,7 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) localparam integer PA_WIDTH = `PA_BITS - 2; - logic [4:0] CurrState, NextState; + statetype CurrState, NextState; logic hit, spill; logic SavePC; logic [1:0] PCMux; @@ -187,10 +187,9 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) // the FSM is always runing, do not stall. - flopr #(5) stateReg(.clk(clk), - .reset(reset), - .d(NextState), - .q(CurrState)); + always_ff @(posedge clk, posedge reset) + if (reset) CurrState <= #1 STATE_READY; + else CurrState <= #1 NextState; assign spill = PCPF[4:1] == 4'b1111 ? 1'b1 : 1'b0; assign hit = ICacheMemReadValid; // note ICacheMemReadValid is hit. diff --git a/wally-pipelined/src/cache/icache.sv b/wally-pipelined/src/cache/icache.sv index 99c43df51..954828fd5 100644 --- a/wally-pipelined/src/cache/icache.sv +++ b/wally-pipelined/src/cache/icache.sv @@ -70,15 +70,15 @@ module icache ICacheMem #(.BLOCKLEN(BLOCKLEN), .NUMLINES(NUMLINES)) - cachemem( - .*, - // Stall it if the pipeline is stalled, unless we're stalling it and we're ending our stall + cachemem(.clk, + .reset, .flush(FlushMem), + .PCTagF, + .PCNextIndexF, .WriteEnable(ICacheMemWriteEnable), .WriteLine(ICacheMemWriteData), - .ReadLineF(ReadLineF), - .HitF(ICacheMemReadValid) - ); + .ReadLineF, + .HitF(ICacheMemReadValid)); always_comb begin case (PCTagF[4:1]) @@ -105,7 +105,32 @@ module icache end - ICacheCntrl #(.BLOCKLEN(BLOCKLEN)) controller(.*); + ICacheCntrl #(.BLOCKLEN(BLOCKLEN)) + controller(.clk, + .reset, + .StallF, + .StallD, + .FlushD, + .PCNextF, + .PCPF, + .ICacheMemReadData, + .ICacheMemReadValid, + .PCTagF, + .PCNextIndexF, + .ICacheReadEn, + .ICacheMemWriteEnable, + .ICacheMemWriteData, + .CompressedF, + .FinalInstrRawF, + .ICacheStallF, + . EndFetchState, + .ITLBMissF, + .ITLBWriteF, + .WalkerInstrPageFaultF, + .InstrInF, + .InstrAckF, + .InstrPAdrF, + .InstrReadF); // For now, assume no writes to executable memory assign FlushMem = 1'b0;