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fix whitespace in fregfile.sv

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Matthew 2024-06-12 22:27:25 -05:00
parent 6f1f3b719a
commit 61eba041e4
1 changed files with 17 additions and 17 deletions
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src/fpu/fregfile.sv
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@ -35,20 +35,20 @@ module fregfile #(parameter FLEN) (
output logic [FLEN-1:0] rd1, rd2, rd3 // read data output logic [FLEN-1:0] rd1, rd2, rd3 // read data
); );
logic [FLEN-1:0] rf[31:0]; logic [FLEN-1:0] rf[31:0];
integer i; integer i;
// three ported register file // three ported register file
// read three ports combinationally (A1/RD1, A2/RD2, A3/RD3) // read three ports combinationally (A1/RD1, A2/RD2, A3/RD3)
// write fourth port on rising edge of clock (A4/WD4/WE4) // write fourth port on rising edge of clock (A4/WD4/WE4)
// write occurs on falling edge of clock // write occurs on falling edge of clock
always_ff @(negedge clk) // or posedge reset) always_ff @(negedge clk) // or posedge reset)
if (reset) for(i=0; i<32; i++) rf[i] <= '0; if (reset) for(i=0; i<32; i++) rf[i] <= '0;
else if (we4) rf[a4] <= wd4; else if (we4) rf[a4] <= wd4;
assign rd1 = rf[a1]; assign rd1 = rf[a1];
assign rd2 = rf[a2]; assign rd2 = rf[a2];
assign rd3 = rf[a3]; assign rd3 = rf[a3];
endmodule // regfile endmodule // regfile