diff --git a/src/fpu/fregfile.sv b/src/fpu/fregfile.sv
index e907875a2..d61ee30dd 100644
--- a/src/fpu/fregfile.sv
+++ b/src/fpu/fregfile.sv
@@ -34,21 +34,21 @@ module fregfile #(parameter FLEN) (
   input logic [FLEN-1:0]   wd4,             // write data
   output logic [FLEN-1:0]  rd1, rd2, rd3    // read data
 );
-   
-   logic [FLEN-1:0] rf[31:0];
-   integer i;
-   
-   // three ported register file
-   // read three ports combinationally (A1/RD1, A2/RD2, A3/RD3)
-   // write fourth port on rising edge of clock (A4/WD4/WE4)
-   // write occurs on falling edge of clock   
-   
-   always_ff @(negedge clk) // or posedge reset)
-     if (reset) for(i=0; i<32; i++) rf[i] <= '0;
-     else if (we4) rf[a4] <= wd4;  
-   
-   assign rd1 = rf[a1];
-   assign rd2 = rf[a2];
-   assign rd3 = rf[a3];
-   
+
+  logic [FLEN-1:0] rf[31:0];
+  integer i;
+
+  // three ported register file
+  // read three ports combinationally (A1/RD1, A2/RD2, A3/RD3)
+  // write fourth port on rising edge of clock (A4/WD4/WE4)
+  // write occurs on falling edge of clock
+
+  always_ff @(negedge clk) // or posedge reset)
+    if (reset) for(i=0; i<32; i++) rf[i] <= '0;
+    else if (we4) rf[a4] <= wd4;
+
+  assign rd1 = rf[a1];
+  assign rd2 = rf[a2];
+  assign rd3 = rf[a3];
+
 endmodule // regfile