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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data.
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@ -115,7 +115,7 @@ add wave -noupdate -expand -group {alu execution stage} /testbench/dut/hart/ieu/
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add wave -noupdate -expand -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE
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add wave -noupdate -expand -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE
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add wave -noupdate /testbench/dut/hart/ieu/dp/ALUResultM
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add wave -noupdate /testbench/dut/hart/ieu/dp/ALUResultM
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TreeUpdate [SetDefaultTree]
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 2} {231033 ns} 0} {{Cursor 3} {1276133 ns} 0}
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WaveRestoreCursors {{Cursor 2} {231033 ns} 0} {{Cursor 3} {1276117 ns} 0}
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quietly wave cursor active 2
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quietly wave cursor active 2
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configure wave -namecolwidth 250
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configure wave -namecolwidth 250
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configure wave -valuecolwidth 518
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configure wave -valuecolwidth 518
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@ -44,6 +44,7 @@ module controller(
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output logic ALUSrcAE, ALUSrcBE,
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output logic ALUSrcAE, ALUSrcBE,
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output logic TargetSrcE,
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output logic TargetSrcE,
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output logic MemReadE, // for Hazard Unit
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output logic MemReadE, // for Hazard Unit
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output logic JumpE,
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// Memory stage control signals
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// Memory stage control signals
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input logic FlushM,
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input logic FlushM,
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input logic DataMisalignedM,
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input logic DataMisalignedM,
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@ -64,7 +65,7 @@ module controller(
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logic RegWriteD, RegWriteE;
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logic RegWriteD, RegWriteE;
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logic [1:0] ResultSrcD, ResultSrcE, ResultSrcM;
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logic [1:0] ResultSrcD, ResultSrcE, ResultSrcM;
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logic [1:0] MemRWD, MemRWE;
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logic [1:0] MemRWD, MemRWE;
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logic JumpD, JumpE;
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logic JumpD;
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logic BranchD, BranchE;
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logic BranchD, BranchE;
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logic [1:0] ALUOpD;
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logic [1:0] ALUOpD;
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logic [4:0] ALUControlD;
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logic [4:0] ALUControlD;
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@ -38,7 +38,9 @@ module datapath (
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input logic [4:0] ALUControlE,
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input logic [4:0] ALUControlE,
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input logic ALUSrcAE, ALUSrcBE,
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input logic ALUSrcAE, ALUSrcBE,
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input logic TargetSrcE,
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input logic TargetSrcE,
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input logic JumpE,
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input logic [`XLEN-1:0] PCE,
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input logic [`XLEN-1:0] PCE,
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input logic [`XLEN-1:0] PCLinkE,
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output logic [2:0] FlagsE,
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output logic [2:0] FlagsE,
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output logic [`XLEN-1:0] PCTargetE,
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output logic [`XLEN-1:0] PCTargetE,
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// Memory stage signals
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// Memory stage signals
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@ -67,7 +69,7 @@ module datapath (
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// Execute stage signals
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// Execute stage signals
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logic [`XLEN-1:0] RD1E, RD2E;
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logic [`XLEN-1:0] RD1E, RD2E;
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logic [`XLEN-1:0] ExtImmE;
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logic [`XLEN-1:0] ExtImmE;
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logic [`XLEN-1:0] PreSrcAE, SrcAE, SrcBE;
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logic [`XLEN-1:0] PreSrcAE, SrcAE, SrcBE, SrcAE2, SrcBE2;
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logic [`XLEN-1:0] ALUResultE;
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logic [`XLEN-1:0] ALUResultE;
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logic [`XLEN-1:0] WriteDataE;
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logic [`XLEN-1:0] WriteDataE;
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logic [`XLEN-1:0] TargetBaseE;
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logic [`XLEN-1:0] TargetBaseE;
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@ -95,8 +97,10 @@ module datapath (
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mux3 #(`XLEN) faemux(RD1E, ResultW, ALUResultM, ForwardAE, PreSrcAE);
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mux3 #(`XLEN) faemux(RD1E, ResultW, ALUResultM, ForwardAE, PreSrcAE);
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mux3 #(`XLEN) fbemux(RD2E, ResultW, ALUResultM, ForwardBE, WriteDataE);
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mux3 #(`XLEN) fbemux(RD2E, ResultW, ALUResultM, ForwardBE, WriteDataE);
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mux2 #(`XLEN) srcamux(PreSrcAE, PCE, ALUSrcAE, SrcAE);
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mux2 #(`XLEN) srcamux(PreSrcAE, PCE, ALUSrcAE, SrcAE);
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mux2 #(`XLEN) srcamux2(SrcAE, PCLinkE, JumpE, SrcAE2);
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mux2 #(`XLEN) srcbmux(WriteDataE, ExtImmE, ALUSrcBE, SrcBE);
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mux2 #(`XLEN) srcbmux(WriteDataE, ExtImmE, ALUSrcBE, SrcBE);
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alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, ALUResultE, FlagsE);
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mux2 #(`XLEN) srcbmux2(SrcBE, {`XLEN{1'b0}}, JumpE, SrcBE2); // *** May be able to remove this mux.
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alu #(`XLEN) alu(SrcAE2, SrcBE2, ALUControlE, ALUResultE, FlagsE);
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mux2 #(`XLEN) targetsrcmux(PCE, SrcAE, TargetSrcE, TargetBaseE);
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mux2 #(`XLEN) targetsrcmux(PCE, SrcAE, TargetSrcE, TargetBaseE);
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assign PCTargetE = ExtImmE + TargetBaseE;
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assign PCTargetE = ExtImmE + TargetBaseE;
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@ -111,5 +115,7 @@ module datapath (
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floprc #(`XLEN) ALUResultWReg(clk, reset, FlushW, ALUResultM, ALUResultW);
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floprc #(`XLEN) ALUResultWReg(clk, reset, FlushW, ALUResultM, ALUResultW);
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floprc #(5) RdWEg(clk, reset, FlushW, RdM, RdW);
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floprc #(5) RdWEg(clk, reset, FlushW, RdM, RdW);
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// This mux4:1 no longer needs to include PCLinkW. This is set correctly in the execution stage.
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// *** need to look at how the decoder is coded to fix.
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mux4 #(`XLEN) resultmux(ALUResultW, ReadDataW, PCLinkW, CSRReadValW, ResultSrcW, ResultW);
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mux4 #(`XLEN) resultmux(ALUResultW, ReadDataW, PCLinkW, CSRReadValW, ResultSrcW, ResultW);
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endmodule
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endmodule
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@ -33,6 +33,7 @@ module ieu (
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output logic IllegalBaseInstrFaultD,
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output logic IllegalBaseInstrFaultD,
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// Execute Stage interface
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// Execute Stage interface
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input logic [`XLEN-1:0] PCE,
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input logic [`XLEN-1:0] PCE,
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input logic [`XLEN-1:0] PCLinkE,
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output logic [`XLEN-1:0] PCTargetE,
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output logic [`XLEN-1:0] PCTargetE,
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// Memory stage interface
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// Memory stage interface
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input logic DataMisalignedM,
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input logic DataMisalignedM,
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@ -68,6 +69,7 @@ module ieu (
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logic [1:0] ForwardAE, ForwardBE;
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logic [1:0] ForwardAE, ForwardBE;
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logic RegWriteM, RegWriteW;
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logic RegWriteM, RegWriteW;
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logic MemReadE;
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logic MemReadE;
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logic JumpE;
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controller c(.OpD(InstrD[6:0]), .Funct3D(InstrD[14:12]), .Funct7b5D(InstrD[30]), .*);
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controller c(.OpD(InstrD[6:0]), .Funct3D(InstrD[14:12]), .Funct7b5D(InstrD[30]), .*);
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datapath dp(.*);
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datapath dp(.*);
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@ -78,6 +78,7 @@ module bpred
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// Part 2 branch direction prediction
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// Part 2 branch direction prediction
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twoBitPredictor DirPredictor(.clk(clk),
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twoBitPredictor DirPredictor(.clk(clk),
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.reset(reset),
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.LookUpPC(PCNextF),
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.LookUpPC(PCNextF),
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.Prediction(BPPredF),
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.Prediction(BPPredF),
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// update
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// update
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@ -110,8 +111,8 @@ module bpred
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.UpdateTarget(PCTargetE));
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.UpdateTarget(PCTargetE));
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// need to forward when updating to the same address as reading.
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// need to forward when updating to the same address as reading.
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assign CorrectPCE = PCSrcE ? PCTargetE : PCLinkE;
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//assign CorrectPCE = PCSrcE ? PCTargetE : PCLinkE;
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assign TargetPC = (PCE == PCNextF) ? CorrectPCE : BTBPredPCF;
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//assign TargetPC = (PCE == PCNextF) ? CorrectPCE : BTBPredPCF;
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// Part 4 RAS
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// Part 4 RAS
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// *** need to add the logic to restore RAS on flushes. We will use incr for this.
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// *** need to add the logic to restore RAS on flushes. We will use incr for this.
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@ -36,6 +36,7 @@ module ifu (
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// Decode
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// Decode
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output logic InstrStall,
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output logic InstrStall,
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// Execute
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// Execute
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output logic [`XLEN-1:0] PCLinkE,
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input logic PCSrcE,
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input logic PCSrcE,
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input logic [`XLEN-1:0] PCTargetE,
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input logic [`XLEN-1:0] PCTargetE,
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output logic [`XLEN-1:0] PCE,
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output logic [`XLEN-1:0] PCE,
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@ -58,7 +59,7 @@ module ifu (
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logic misaligned, BranchMisalignedFaultE, BranchMisalignedFaultM, TrapMisalignedFaultM;
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logic misaligned, BranchMisalignedFaultE, BranchMisalignedFaultM, TrapMisalignedFaultM;
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logic StallExceptResolveBranchesF, PrivilegedChangePCM;
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logic StallExceptResolveBranchesF, PrivilegedChangePCM;
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logic IllegalCompInstrD;
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logic IllegalCompInstrD;
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logic [`XLEN-1:0] PCPlusUpperF, PCPlus2or4F, PCD, PCW, PCLinkD, PCLinkE, PCLinkM;
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logic [`XLEN-1:0] PCPlusUpperF, PCPlus2or4F, PCD, PCW, PCLinkD, PCLinkM;
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logic CompressedF;
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logic CompressedF;
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logic [31:0] InstrRawD, InstrE;
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logic [31:0] InstrRawD, InstrE;
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logic [31:0] nop = 32'h00000013; // instruction for NOP
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logic [31:0] nop = 32'h00000013; // instruction for NOP
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@ -57,7 +57,7 @@ module wallypipelinedhart (
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logic [`XLEN-1:0] SrcAM;
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logic [`XLEN-1:0] SrcAM;
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// logic [31:0] InstrF;
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// logic [31:0] InstrF;
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logic [31:0] InstrD, InstrM;
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logic [31:0] InstrD, InstrM;
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logic [`XLEN-1:0] PCE, PCM, PCLinkW;
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logic [`XLEN-1:0] PCE, PCM, PCLinkE, PCLinkW;
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logic [`XLEN-1:0] PCTargetE;
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logic [`XLEN-1:0] PCTargetE;
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logic [`XLEN-1:0] CSRReadValW;
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logic [`XLEN-1:0] CSRReadValW;
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logic [`XLEN-1:0] PrivilegedNextPCM;
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logic [`XLEN-1:0] PrivilegedNextPCM;
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@ -408,7 +408,7 @@ string tests32i[] = {
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end // always @ (negedge clk)
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end // always @ (negedge clk)
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// track the current function or label
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// track the current function or label
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function_rfunction_radix function_radix();
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//function_rfunction_radix function_radix();
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endmodule
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endmodule
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