From 1d36ce3328234e9d646c9a1fc32fd03647b06d20 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 18 Dec 2023 12:03:54 -0600 Subject: [PATCH 1/9] Fixed lint issue. --- src/cache/cachefsm.sv | 1 + 1 file changed, 1 insertion(+) diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index cfc0a8c16..b67340989 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -79,6 +79,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P, logic CMOWriteback; logic CMOZeroNoEviction; logic StallConditions; + logic StoreHazard; typedef enum logic [3:0]{STATE_READY, // hit states // miss states From 5062a8c89cf71ccf7d4aede66b3a8c015bb0be7a Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 18 Dec 2023 12:50:49 -0600 Subject: [PATCH 2/9] Added parameter for cache's SRAM length. Progress towards verilator support. --- config/buildroot/config.vh | 1 + config/rv32e/config.vh | 1 + config/rv32gc/config.vh | 1 + config/rv32i/config.vh | 1 + config/rv32imc/config.vh | 1 + config/rv64fpquad/config.vh | 1 + config/rv64gc/config.vh | 1 + config/rv64i/config.vh | 1 + config/shared/parameter-defs.vh | 1 + src/cache/cacheway.sv | 17 ++--- src/cvw.sv | 1 + src/generic/mem/ram2p1r1wbe.sv | 4 +- .../{DCaacheFlushFSM.sv => DCacheFlushFSM.sv} | 4 +- testbench/testbench.sv | 73 ++++++++++++++++--- 14 files changed, 85 insertions(+), 23 deletions(-) rename testbench/common/{DCaacheFlushFSM.sv => DCacheFlushFSM.sv} (96%) diff --git a/config/buildroot/config.vh b/config/buildroot/config.vh index cc168e75c..35d20e169 100644 --- a/config/buildroot/config.vh +++ b/config/buildroot/config.vh @@ -70,6 +70,7 @@ localparam DCACHE_LINELENINBITS = 32'd512; localparam ICACHE_NUMWAYS = 32'd4; localparam ICACHE_WAYSIZEINBYTES = 32'd4096; localparam ICACHE_LINELENINBITS = 32'd512; +localparam CACHE_SRAMLEN = 32'd128; // Integer Divider Configuration // IDIV_BITSPERCYCLE must be 1, 2, or 4 diff --git a/config/rv32e/config.vh b/config/rv32e/config.vh index e532aa9a8..1db72cad7 100644 --- a/config/rv32e/config.vh +++ b/config/rv32e/config.vh @@ -70,6 +70,7 @@ localparam DCACHE_LINELENINBITS = 32'd512; localparam ICACHE_NUMWAYS = 32'd4; localparam ICACHE_WAYSIZEINBYTES = 32'd4096; localparam ICACHE_LINELENINBITS = 32'd512; +localparam CACHE_SRAMLEN = 32'd128; // Integer Divider Configuration // IDIV_BITSPERCYCLE must be 1, 2, or 4 diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh index 52baad796..a5af5f608 100644 --- a/config/rv32gc/config.vh +++ b/config/rv32gc/config.vh @@ -71,6 +71,7 @@ localparam DCACHE_LINELENINBITS = 32'd512; localparam ICACHE_NUMWAYS = 32'd4; localparam ICACHE_WAYSIZEINBYTES = 32'd4096; localparam ICACHE_LINELENINBITS = 32'd512; +localparam CACHE_SRAMLEN = 32'd128; // Integer Divider Configuration // IDIV_BITSPERCYCLE must be 1, 2, or 4 diff --git a/config/rv32i/config.vh b/config/rv32i/config.vh index 860a7c783..13e3d2f66 100644 --- a/config/rv32i/config.vh +++ b/config/rv32i/config.vh @@ -70,6 +70,7 @@ localparam DCACHE_LINELENINBITS = 32'd512; localparam ICACHE_NUMWAYS = 32'd4; localparam ICACHE_WAYSIZEINBYTES = 32'd4096; localparam ICACHE_LINELENINBITS = 32'd512; +localparam CACHE_SRAMLEN = 32'd128; // Integer Divider Configuration // IDIV_BITSPERCYCLE must be 1, 2, or 4 diff --git a/config/rv32imc/config.vh b/config/rv32imc/config.vh index b9e485099..ba0c455e3 100644 --- a/config/rv32imc/config.vh +++ b/config/rv32imc/config.vh @@ -69,6 +69,7 @@ localparam DCACHE_LINELENINBITS = 32'd512; localparam ICACHE_NUMWAYS = 32'd4; localparam ICACHE_WAYSIZEINBYTES = 32'd4096; localparam ICACHE_LINELENINBITS = 32'd512; +localparam CACHE_SRAMLEN = 32'd128; // Integer Divider Configuration // IDIV_BITSPERCYCLE must be 1, 2, or 4 diff --git a/config/rv64fpquad/config.vh b/config/rv64fpquad/config.vh index 9d5843bca..fb6e500fa 100644 --- a/config/rv64fpquad/config.vh +++ b/config/rv64fpquad/config.vh @@ -70,6 +70,7 @@ localparam DCACHE_LINELENINBITS = 32'd512; localparam ICACHE_NUMWAYS = 32'd4; localparam ICACHE_WAYSIZEINBYTES = 32'd4096; localparam ICACHE_LINELENINBITS = 32'd512; +localparam CACHE_SRAMLEN = 32'd128; // Integer Divider Configuration // IDIV_BITSPERCYCLE must be 1, 2, or 4 diff --git a/config/rv64gc/config.vh b/config/rv64gc/config.vh index 84f4de599..0597f4b76 100644 --- a/config/rv64gc/config.vh +++ b/config/rv64gc/config.vh @@ -70,6 +70,7 @@ localparam DCACHE_LINELENINBITS = 32'd512; localparam ICACHE_NUMWAYS = 32'd4; localparam ICACHE_WAYSIZEINBYTES = 32'd4096; localparam ICACHE_LINELENINBITS = 32'd512; +localparam CACHE_SRAMLEN = 32'd128; // Integer Divider Configuration // IDIV_BITSPERCYCLE must be 1, 2, or 4 diff --git a/config/rv64i/config.vh b/config/rv64i/config.vh index cbc3700e9..0a355f1e3 100644 --- a/config/rv64i/config.vh +++ b/config/rv64i/config.vh @@ -70,6 +70,7 @@ localparam DCACHE_LINELENINBITS = 32'd512; localparam ICACHE_NUMWAYS = 32'd4; localparam ICACHE_WAYSIZEINBYTES = 32'd4096; localparam ICACHE_LINELENINBITS = 32'd512; +localparam CACHE_SRAMLEN = 32'd128; // Integer Divider Configuration // IDIV_BITSPERCYCLE must be 1, 2, or 4 diff --git a/config/shared/parameter-defs.vh b/config/shared/parameter-defs.vh index 67f85783c..7e5a19619 100644 --- a/config/shared/parameter-defs.vh +++ b/config/shared/parameter-defs.vh @@ -38,6 +38,7 @@ localparam cvw_t P = '{ ICACHE_NUMWAYS : ICACHE_NUMWAYS, ICACHE_WAYSIZEINBYTES : ICACHE_WAYSIZEINBYTES, ICACHE_LINELENINBITS : ICACHE_LINELENINBITS, + CACHE_SRAMLEN : CACHE_SRAMLEN, IDIV_BITSPERCYCLE : IDIV_BITSPERCYCLE, IDIV_ON_FPU : IDIV_ON_FPU, PMP_ENTRIES : PMP_ENTRIES, diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index 19d916663..52ccc6c15 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -129,21 +129,20 @@ module cacheway import cvw::*; #(parameter cvw_t P, genvar words; - localparam SRAMLEN = 128; // *** make this a global parameter - localparam NUMSRAM = LINELEN/SRAMLEN; - localparam SRAMLENINBYTES = SRAMLEN/8; + localparam NUMSRAM = LINELEN/P.CACHE_SRAMLEN; + localparam SRAMLENINBYTES = P.CACHE_SRAMLEN/8; localparam LOGNUMSRAM = $clog2(NUMSRAM); for(words = 0; words < NUMSRAM; words++) begin: word if (!READ_ONLY_CACHE) begin:wordram - ram1p1rwbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSetData), - .dout(ReadDataLine[SRAMLEN*(words+1)-1:SRAMLEN*words]), - .din(LineWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]), + ram1p1rwbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(NUMLINES), .WIDTH(P.CACHE_SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSetData), + .dout(ReadDataLine[P.CACHE_SRAMLEN*(words+1)-1:P.CACHE_SRAMLEN*words]), + .din(LineWriteData[P.CACHE_SRAMLEN*(words+1)-1:P.CACHE_SRAMLEN*words]), .we(SelectedWriteWordEn), .bwe(FinalByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words])); end else begin:wordram // no byte-enable needed for i$. - ram1p1rwe #(.USE_SRAM(P.USE_SRAM), .DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSetData), - .dout(ReadDataLine[SRAMLEN*(words+1)-1:SRAMLEN*words]), - .din(LineWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]), + ram1p1rwe #(.USE_SRAM(P.USE_SRAM), .DEPTH(NUMLINES), .WIDTH(P.CACHE_SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSetData), + .dout(ReadDataLine[P.CACHE_SRAMLEN*(words+1)-1:P.CACHE_SRAMLEN*words]), + .din(LineWriteData[P.CACHE_SRAMLEN*(words+1)-1:P.CACHE_SRAMLEN*words]), .we(SelectedWriteWordEn)); end end diff --git a/src/cvw.sv b/src/cvw.sv index 6ee18c27f..e237dd56c 100644 --- a/src/cvw.sv +++ b/src/cvw.sv @@ -80,6 +80,7 @@ typedef struct packed { int ICACHE_NUMWAYS; int ICACHE_WAYSIZEINBYTES; int ICACHE_LINELENINBITS; + int CACHE_SRAMLEN; // Integer Divider Configuration // IDIV_BITSPERCYCLE must be 1, 2, or 4 diff --git a/src/generic/mem/ram2p1r1wbe.sv b/src/generic/mem/ram2p1r1wbe.sv index 586a4e892..42435c607 100644 --- a/src/generic/mem/ram2p1r1wbe.sv +++ b/src/generic/mem/ram2p1r1wbe.sv @@ -110,11 +110,11 @@ module ram2p1r1wbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=1024, WIDTH=68) // *************************************************************************** integer i; - /* initial begin // initialize memory for simulation only; not needed because done in the testbench now + initial begin // initialize memory for simulation only; not needed because done in the testbench now integer j; for (j=0; j < DEPTH; j++) mem[j] = '0; - end */ + end // Read logic [$clog2(DEPTH)-1:0] ra1d; diff --git a/testbench/common/DCaacheFlushFSM.sv b/testbench/common/DCacheFlushFSM.sv similarity index 96% rename from testbench/common/DCaacheFlushFSM.sv rename to testbench/common/DCacheFlushFSM.sv index 1696a661c..d82d4753a 100644 --- a/testbench/common/DCaacheFlushFSM.sv +++ b/testbench/common/DCacheFlushFSM.sv @@ -43,8 +43,8 @@ module DCacheFlushFSM import cvw::*; #(parameter cvw_t P) localparam numways = P.DCACHE_NUMWAYS; localparam linelen = P.DCACHE_LINELENINBITS; localparam linebytelen = linelen/8; - localparam sramlen = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN; - localparam cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM; + localparam sramlen = P.CACHE_SRAMLEN; + localparam cachesramwords = linelen/sramlen; localparam numwords = sramlen/P.XLEN; localparam lognumlines = $clog2(numlines); localparam loglinebytelen = $clog2(linebytelen); diff --git a/testbench/testbench.sv b/testbench/testbench.sv index ece7500d5..f58304a25 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -271,7 +271,7 @@ module testbench; //////////////////////////////////////////////////////////////////////////////// if(TestBenchReset) test = 1; if (TEST == "coremark") - if (dut.core.EcallFaultM) begin + if (dut.core.priv.priv.EcallFaultM) begin $display("Benchmark: coremark is done."); $stop; end @@ -320,6 +320,7 @@ module testbench; //////////////////////////////////////////////////////////////////////////////// // Some memories are not reset, but should be zeros or set to some initial value for simulation //////////////////////////////////////////////////////////////////////////////// +/* -----\/----- EXCLUDED -----\/----- integer adrindex; always @(posedge clk) begin if (ResetMem) // program memory is sometimes reset @@ -339,13 +340,49 @@ module testbench; end end end + -----/\----- EXCLUDED -----/\----- */ + // still not working in this format +/* -----\/----- EXCLUDED -----\/----- + integer adrindex; + if (P.UNCORE_RAM_SUPPORTED) begin + always @(posedge clk) begin + if (ResetMem) // program memory is sometimes reset + for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1) + dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = '0; + end + end + + genvar adrindex2; + + if (P.BPRED_SUPPORTED & (P.BPRED_TYPE == `BP_LOCAL_AHEAD | P.BPRED_TYPE == `BP_LOCAL_REPAIR)) begin + for(adrindex2 = 0; adrindex2 < 2**P.BPRED_NUM_LHR; adrindex2++) + always @(posedge clk) begin + dut.core.ifu.bpred.bpred.Predictor.DirPredictor.BHT.mem[adrindex2] = 0; + end + end + + if (P.BPRED_SUPPORTED) begin + always @(posedge clk) + dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[0] = 0; + for(adrindex2 = 0; adrindex2 < 2**P.BTB_SIZE; adrindex2++) + always @(posedge clk) begin + dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex2] = 0; + end + for(adrindex2 = 0; adrindex2 < 2**P.BPRED_SIZE; adrindex2++) + always @(posedge clk) begin + dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex2] = 0; + end + end + -----/\----- EXCLUDED -----/\----- */ + //////////////////////////////////////////////////////////////////////////////// // load memories with program image //////////////////////////////////////////////////////////////////////////////// - always @(posedge clk) begin - if (LoadMem) begin - if (P.SDC_SUPPORTED) begin + + if (P.SDC_SUPPORTED) begin + always @(posedge clk) begin + if (LoadMem) begin string romfilename, sdcfilename; romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"}; sdcfilename = {"../testbench/sdc/ramdisk2.hex"}; @@ -353,13 +390,29 @@ module testbench; //$readmemh(sdcfilename, sdcard.sdcard.FLASHmem); // shorten sdc timers for simulation //dut.uncore.uncore.sdc.SDC.LimitTimers = 1; - end - else if (P.IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM); - else if (P.BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); - if (P.DTIM_SUPPORTED) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM); - $display("Read memfile %s", memfilename); + end end - end + end else if (P.IROM_SUPPORTED) begin + always @(posedge clk) begin + if (LoadMem) begin + $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM); + end + end + end else if (P.BUS_SUPPORTED) begin + always @(posedge clk) begin + if (LoadMem) begin + $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); + end + end + end + if (P.DTIM_SUPPORTED) begin + always @(posedge clk) begin + if (LoadMem) begin + $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM); + $display("Read memfile %s", memfilename); + end + end + end //////////////////////////////////////////////////////////////////////////////// // Actual hardware From 4a3cc8b9c8f52c6f2037a2b60004d648094bc2a9 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 18 Dec 2023 13:26:43 -0600 Subject: [PATCH 3/9] More progress towards verilator. --- testbench/common/DCacheFlushFSM.sv | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/testbench/common/DCacheFlushFSM.sv b/testbench/common/DCacheFlushFSM.sv index d82d4753a..334c6a6af 100644 --- a/testbench/common/DCacheFlushFSM.sv +++ b/testbench/common/DCacheFlushFSM.sv @@ -124,15 +124,22 @@ module copyShadow import cvw::*; #(parameter cvw_t P, output logic [P.XLEN-1:0] CacheTag, output logic CacheValid, output logic CacheDirty); + + logic [P.XLEN-1:0] TagExtend; + logic [P.XLEN-1:0] IndexExtend; + logic [P.XLEN-1:0] CacheWordExtend; + assign TagExtend = {{{P.XLEN-(P.PA_BITS-tagstart)}{1'b0}}, tag}; + assign IndexExtend = {{{P.XLEN-32}{1'b0}}, index}; + assign CacheWordExtend = {{{P.XLEN-32}{1'b0}}, cacheWord}; always_ff @(posedge clk) begin if(start) begin - CacheTag = tag; + CacheTag = TagExtend; CacheValid = valid; CacheDirty = dirty; CacheData = data; - CacheAdr = (tag << tagstart) + (index << loglinebytelen) + (cacheWord << $clog2(sramlen/8)); + CacheAdr = (TagExtend << tagstart) + (IndexExtend << loglinebytelen) + (CacheWordExtend << $clog2(sramlen/8)); end end From 58942b246bf44ae637ebd35f37f1073a67f097c5 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 18 Dec 2023 13:34:14 -0600 Subject: [PATCH 4/9] Kind of a frustrating set of changes to get the verilator errors out of the copyShadow module. --- testbench/common/DCacheFlushFSM.sv | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/testbench/common/DCacheFlushFSM.sv b/testbench/common/DCacheFlushFSM.sv index 334c6a6af..983fa4932 100644 --- a/testbench/common/DCacheFlushFSM.sv +++ b/testbench/common/DCacheFlushFSM.sv @@ -125,22 +125,25 @@ module copyShadow import cvw::*; #(parameter cvw_t P, output logic CacheValid, output logic CacheDirty); - logic [P.XLEN-1:0] TagExtend; - logic [P.XLEN-1:0] IndexExtend; - logic [P.XLEN-1:0] CacheWordExtend; + logic [P.XLEN+1:0] TagExtend; + logic [P.XLEN+1:0] IndexExtend; + logic [P.XLEN+1:0] CacheWordExtend; + logic [P.XLEN+1:0] CacheAdrExtend; - assign TagExtend = {{{P.XLEN-(P.PA_BITS-tagstart)}{1'b0}}, tag}; - assign IndexExtend = {{{P.XLEN-32}{1'b0}}, index}; - assign CacheWordExtend = {{{P.XLEN-32}{1'b0}}, cacheWord}; + assign TagExtend = {{{P.XLEN-(P.PA_BITS-tagstart)+2}{1'b0}}, tag}; + assign IndexExtend = {{{P.XLEN-32+2}{1'b0}}, index}; + assign CacheWordExtend = {{{P.XLEN-32+2}{1'b0}}, cacheWord}; always_ff @(posedge clk) begin if(start) begin - CacheTag = TagExtend; + CacheTag = TagExtend[P.XLEN-1:0]; CacheValid = valid; CacheDirty = dirty; CacheData = data; - CacheAdr = (TagExtend << tagstart) + (IndexExtend << loglinebytelen) + (CacheWordExtend << $clog2(sramlen/8)); + CacheAdrExtend = (TagExtend << tagstart) + (IndexExtend << loglinebytelen) + (CacheWordExtend << $clog2(sramlen/8)); end end + + assign CacheAdr = CacheAdrExtend[P.PA_BITS-1:0]; endmodule From c1ac153a4f68bffc2ea87f983122002b2eed57ad Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 18 Dec 2023 16:26:56 -0600 Subject: [PATCH 5/9] Closer to verilator support. --- testbench/common/DCacheFlushFSM.sv | 5 ++++- testbench/common/functionName.sv | 21 ++++++++++++++------- testbench/testbench.sv | 7 +++++-- 3 files changed, 23 insertions(+), 10 deletions(-) diff --git a/testbench/common/DCacheFlushFSM.sv b/testbench/common/DCacheFlushFSM.sv index 983fa4932..152aaa173 100644 --- a/testbench/common/DCacheFlushFSM.sv +++ b/testbench/common/DCacheFlushFSM.sv @@ -97,7 +97,10 @@ module DCacheFlushFSM import cvw::*; #(parameter cvw_t P) // # ** Error: ../testbench/testbench.sv(483): Range must be bounded by constant expressions. // see https://verificationacademy.com/forums/systemverilog/range-must-be-bounded-constant-expressions //ShadowRAM[CacheAdr[j][i][k] >> $clog2(P.XLEN/8)] = cacheline[P.XLEN*(k+1)-1:P.XLEN*k]; - ShadowRAM[(CacheAdr[j][i][l] >> $clog2(P.XLEN/8)) + k] = CacheData[j][i][l][P.XLEN*k +: P.XLEN]; + /* verilator lint_off WIDTHTRUNC */ + // *** lint error: address trunc warning for shadowram index + ShadowRAM[(CacheAdr[j][i][l] >> $clog2(P.XLEN/8)) + {{{P.PA_BITS-32}{1'b0}}, k}] = CacheData[j][i][l][P.XLEN*k +: P.XLEN]; + /* verilator lint_on WIDTHTRUNC */ end end end diff --git a/testbench/common/functionName.sv b/testbench/common/functionName.sv index 7aebedea8..e59491621 100644 --- a/testbench/common/functionName.sv +++ b/testbench/common/functionName.sv @@ -30,7 +30,7 @@ module FunctionName import cvw::*; #(parameter cvw_t P) ( input string ProgramLabelMapFile ); - logic [P.XLEN-1:0] ProgramAddrMapMemory []; + logic [P.XLEN-1:0] ProgramAddrMapMemory [longint]; string ProgramLabelMapMemory [integer]; string FunctionName; @@ -62,7 +62,7 @@ module FunctionName import cvw::*; #(parameter cvw_t P) ( task automatic bin_search_min; input logic [P.XLEN-1:0] pc; input logic [P.XLEN-1:0] length; - ref logic [P.XLEN-1:0] array []; + ref logic [P.XLEN-1:0] array [longint]; output logic [P.XLEN-1:0] minval; output logic [P.XLEN-1:0] mid; @@ -109,7 +109,8 @@ module FunctionName import cvw::*; #(parameter cvw_t P) ( endtask // bin_search_min integer ProgramAddrMapFP, ProgramLabelMapFP; - integer ProgramAddrMapLineCount, ProgramLabelMapLineCount; + longint ProgramAddrMapLineCount; + integer ProgramLabelMapLineCount; longint ProgramAddrMapLine; string ProgramLabelMapLine; integer status; @@ -118,11 +119,17 @@ module FunctionName import cvw::*; #(parameter cvw_t P) ( // preload // initial begin always @ (negedge reset) begin + + // cannot readmemh directoy to a dynmaic array. Sad times :( + // Let's initialize a static array with FFFF_FFFF for all addresses. + // Then we can readmemh and finally copy to the dynamic array. + // clear out the old mapping between programs. ProgramAddrMapMemory.delete(); ProgramLabelMapMemory.delete(); - $readmemh(ProgramAddrMapFile, ProgramAddrMapMemory); + // Unfortunately verilator version 5.011 readmemh does not support dynamic arrays + //$readmemh(ProgramAddrMapFile, ProgramAddrMapMemory); // we need to count the number of lines in the file so we can set FunctionRadixLineCount. ProgramAddrMapLineCount = 0; @@ -131,9 +138,9 @@ module FunctionName import cvw::*; #(parameter cvw_t P) ( // read line by line to count lines if (ProgramAddrMapFP) begin while (! $feof(ProgramAddrMapFP)) begin - status = $fscanf(ProgramAddrMapFP, "%h\n", ProgramAddrMapLine); - - ProgramAddrMapLineCount = ProgramAddrMapLineCount + 1; + status = $fscanf(ProgramAddrMapFP, "%h\n", ProgramAddrMapLine); + ProgramAddrMapMemory[ProgramAddrMapLineCount] = ProgramAddrMapLine; + ProgramAddrMapLineCount = ProgramAddrMapLineCount + 1; end end else begin $display("Cannot open file %s for reading.", ProgramAddrMapFile); diff --git a/testbench/testbench.sv b/testbench/testbench.sv index f58304a25..f8a174a1b 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -563,8 +563,11 @@ module testbench; /* verilator lint_off INFINITELOOP */ while (signature[i] !== 'bx) begin logic [P.XLEN-1:0] sig; - if (P.DTIM_SUPPORTED) sig = testbench.dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i]; - else if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i]; + // ************************************** + // ***** BUG BUG BUG make sure RT undoes this. + //if (P.DTIM_SUPPORTED) sig = testbench.dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i]; + //else if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i]; + if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i]; //$display("signature[%h] = %h sig = %h", i, signature[i], sig); if (signature[i] !== sig & (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i])) begin errors = errors+1; From b7b245fe2f88dcdc4be568edda8cc05d59474dea Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 18 Dec 2023 16:37:26 -0600 Subject: [PATCH 6/9] functionName.sv is now linting for rv64gc. --- testbench/common/functionName.sv | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/testbench/common/functionName.sv b/testbench/common/functionName.sv index e59491621..eb223be8e 100644 --- a/testbench/common/functionName.sv +++ b/testbench/common/functionName.sv @@ -31,14 +31,14 @@ module FunctionName import cvw::*; #(parameter cvw_t P) ( ); logic [P.XLEN-1:0] ProgramAddrMapMemory [longint]; - string ProgramLabelMapMemory [integer]; + string ProgramLabelMapMemory [longint]; string FunctionName; logic [P.XLEN-1:0] PCF, PCD, PCE, PCM, FunctionAddr, PCM_temp, PCMOld; logic StallD, StallE, StallM, FlushD, FlushE, FlushM; logic InstrValidM; - integer ProgramAddrIndex, ProgramAddrIndexQ; + logic [P.XLEN-1:0] ProgramAddrIndex, ProgramAddrIndexQ; assign PCF = testbench.dut.core.ifu.PCF; assign StallD = testbench.dut.core.StallD; @@ -110,7 +110,7 @@ module FunctionName import cvw::*; #(parameter cvw_t P) ( integer ProgramAddrMapFP, ProgramLabelMapFP; longint ProgramAddrMapLineCount; - integer ProgramLabelMapLineCount; + longint ProgramLabelMapLineCount; longint ProgramAddrMapLine; string ProgramLabelMapLine; integer status; @@ -136,7 +136,7 @@ module FunctionName import cvw::*; #(parameter cvw_t P) ( ProgramAddrMapFP = $fopen(ProgramAddrMapFile, "r"); // read line by line to count lines - if (ProgramAddrMapFP) begin + if (ProgramAddrMapFP != '0) begin while (! $feof(ProgramAddrMapFP)) begin status = $fscanf(ProgramAddrMapFP, "%h\n", ProgramAddrMapLine); ProgramAddrMapMemory[ProgramAddrMapLineCount] = ProgramAddrMapLine; @@ -154,7 +154,7 @@ module FunctionName import cvw::*; #(parameter cvw_t P) ( ProgramLabelMapLineCount = 0; ProgramLabelMapFP = $fopen(ProgramLabelMapFile, "r"); - if (ProgramLabelMapFP) begin + if (ProgramLabelMapFP != '0) begin while (! $feof(ProgramLabelMapFP)) begin status = $fscanf(ProgramLabelMapFP, "%s\n", ProgramLabelMapLine); ProgramLabelMapMemory[ProgramLabelMapLineCount] = ProgramLabelMapLine; From 0f7b6ada0432aaf9c0a307c5f6c2c51b7294ee99 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 18 Dec 2023 16:38:56 -0600 Subject: [PATCH 7/9] Cleanup. Verilator still has issues with riscassertions.sv and the testbench --- testbench/common/functionName.sv | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/testbench/common/functionName.sv b/testbench/common/functionName.sv index eb223be8e..1b2402bee 100644 --- a/testbench/common/functionName.sv +++ b/testbench/common/functionName.sv @@ -30,8 +30,8 @@ module FunctionName import cvw::*; #(parameter cvw_t P) ( input string ProgramLabelMapFile ); - logic [P.XLEN-1:0] ProgramAddrMapMemory [longint]; - string ProgramLabelMapMemory [longint]; + logic [P.XLEN-1:0] ProgramAddrMapMemory [logic [P.XLEN-1:0]]; + string ProgramLabelMapMemory [logic [P.XLEN-1:0]]; string FunctionName; @@ -62,7 +62,7 @@ module FunctionName import cvw::*; #(parameter cvw_t P) ( task automatic bin_search_min; input logic [P.XLEN-1:0] pc; input logic [P.XLEN-1:0] length; - ref logic [P.XLEN-1:0] array [longint]; + ref logic [P.XLEN-1:0] array [logic [P.XLEN-1:0]]; output logic [P.XLEN-1:0] minval; output logic [P.XLEN-1:0] mid; @@ -109,9 +109,9 @@ module FunctionName import cvw::*; #(parameter cvw_t P) ( endtask // bin_search_min integer ProgramAddrMapFP, ProgramLabelMapFP; - longint ProgramAddrMapLineCount; - longint ProgramLabelMapLineCount; - longint ProgramAddrMapLine; + logic [P.XLEN-1:0] ProgramAddrMapLineCount; + logic [P.XLEN-1:0] ProgramLabelMapLineCount; + logic [P.XLEN-1:0] ProgramAddrMapLine; string ProgramLabelMapLine; integer status; From 408bb2c35bcab1ca67f9c3934988bdcb7420ba49 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 18 Dec 2023 16:44:34 -0600 Subject: [PATCH 8/9] Yay! I got verilator to compile our testbench! Does it actually work I don't know. --- testbench/common/ramxdetector.sv | 2 ++ testbench/common/riscvassertions.sv | 2 +- testbench/testbench.sv | 2 ++ 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/testbench/common/ramxdetector.sv b/testbench/common/ramxdetector.sv index 987bbefea..c600cff8c 100644 --- a/testbench/common/ramxdetector.sv +++ b/testbench/common/ramxdetector.sv @@ -36,7 +36,9 @@ module ramxdetector #(parameter XLEN, LLEN) ( ); always_ff @(posedge clk) + /* verilator lint_off WIDTHXZEXPAND */ if (MemReadM & ~LSULoadAccessFaultM & (ReadDataM === 'bx)) begin + /* verilator lint_on WIDTHXZEXPAND */ $display("WARNING: Attempting to read from unitialized RAM. Processor may go haywire if it uses x value. But this is normal in WALLY-mmu tests."); $display(" PCM = %x InstrM = %x (%s), IEUAdrM = %x", PCM, InstrM, InstrMName, IEUAdrM); //$stop; diff --git a/testbench/common/riscvassertions.sv b/testbench/common/riscvassertions.sv index 815478390..dcbe7e32a 100644 --- a/testbench/common/riscvassertions.sv +++ b/testbench/common/riscvassertions.sv @@ -42,7 +42,7 @@ module riscvassertions import cvw::*; #(parameter cvw_t P); assert (2**$clog2(P.ICACHE_WAYSIZEINBYTES) == P.ICACHE_WAYSIZEINBYTES || (!P.ICACHE_SUPPORTED)) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2"); assert (2**$clog2(P.ITLB_ENTRIES) == P.ITLB_ENTRIES || P.VIRTMEM_SUPPORTED==0) else $error("ITLB_ENTRIES must be a power of 2"); assert (2**$clog2(P.DTLB_ENTRIES) == P.DTLB_ENTRIES || P.VIRTMEM_SUPPORTED==0) else $error("DTLB_ENTRIES must be a power of 2"); - assert (P.UNCORE_RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if UNCORE_RAM_RANGE is less than 56'h07FFFFFF"); + assert (P.UNCORE_RAM_RANGE >= 64'h07FFFFFF) else $warning("Some regression tests will fail if UNCORE_RAM_RANGE is less than 64'h07FFFFFF"); assert (P.ZICSR_SUPPORTED == 1 || (P.PMP_ENTRIES == 0 && P.VIRTMEM_SUPPORTED == 0)) else $error("PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported."); assert (P.ZICSR_SUPPORTED == 1 || (P.S_SUPPORTED == 0 && P.U_SUPPORTED == 0)) else $error("S and U modes not supported if ZICSR not supported"); assert (P.U_SUPPORTED || (P.S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported"); diff --git a/testbench/testbench.sv b/testbench/testbench.sv index f8a174a1b..3d7e0d5df 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -561,7 +561,9 @@ module testbench; testadr = ($unsigned(begin_signature_addr))/(P.XLEN/8); testadrNoBase = (begin_signature_addr - P.UNCORE_RAM_BASE)/(P.XLEN/8); /* verilator lint_off INFINITELOOP */ + /* verilator lint_off WIDTHXZEXPAND */ while (signature[i] !== 'bx) begin + /* verilator lint_on WIDTHXZEXPAND */ logic [P.XLEN-1:0] sig; // ************************************** // ***** BUG BUG BUG make sure RT undoes this. From 1e1759c25843122d993cd14c0b7ff9594cbbf6ee Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Mon, 18 Dec 2023 17:00:53 -0600 Subject: [PATCH 9/9] Restored the one hack change which prevents verilator from working. --- testbench/testbench.sv | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 3d7e0d5df..3526622bc 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -567,9 +567,9 @@ module testbench; logic [P.XLEN-1:0] sig; // ************************************** // ***** BUG BUG BUG make sure RT undoes this. - //if (P.DTIM_SUPPORTED) sig = testbench.dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i]; - //else if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i]; - if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i]; + if (P.DTIM_SUPPORTED) sig = testbench.dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i]; + else if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i]; + //if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i]; //$display("signature[%h] = %h sig = %h", i, signature[i], sig); if (signature[i] !== sig & (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i])) begin errors = errors+1;