From 57d32e58c6b564345c345f8fd5372726e127cd94 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 29 Dec 2021 18:52:52 +0000 Subject: [PATCH 1/2] Switched riscv-arch-test to current hash --- addins/riscv-arch-test | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index be67c99bd..307c77b26 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit be67c99bd461742aa1c100bcc0732657faae2230 +Subproject commit 307c77b26e070ae85ffea665ad9b642b40e33c86 From 2e5b805b0a24095ba05f75737801131a5564835e Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Wed, 29 Dec 2021 12:59:17 -0600 Subject: [PATCH 2/2] Add configuration for IEEE 754 or non IEEE 754 per RISC-V guidelines Katherine/James --- wally-pipelined/config/buildroot/wally-config.vh | 3 +++ wally-pipelined/config/coremark/wally-config.vh | 3 +++ wally-pipelined/config/coremark_bare/wally-config.vh | 3 +++ wally-pipelined/config/fpga/wally-config.vh | 3 +++ wally-pipelined/config/rv32gc/wally-config.vh | 3 +++ wally-pipelined/config/rv32ic/wally-config.vh | 3 +++ wally-pipelined/config/rv64BP/wally-config.vh | 3 +++ wally-pipelined/config/rv64gc/wally-config.vh | 3 +++ wally-pipelined/config/rv64ic/wally-config.vh | 3 +++ 9 files changed, 27 insertions(+) diff --git a/wally-pipelined/config/buildroot/wally-config.vh b/wally-pipelined/config/buildroot/wally-config.vh index 1bf19b54e..53ea11538 100644 --- a/wally-pipelined/config/buildroot/wally-config.vh +++ b/wally-pipelined/config/buildroot/wally-config.vh @@ -36,6 +36,9 @@ // RV32 or RV64: XLEN = 32 or 64 `define XLEN 64 +// IEEE 754 compliance +`define IEEE754 0 + `define MISA (32'h0014112D) `define ZICSR_SUPPORTED 1 `define ZIFENCEI_SUPPORTED 1 diff --git a/wally-pipelined/config/coremark/wally-config.vh b/wally-pipelined/config/coremark/wally-config.vh index f26b6d2a7..fa089a3d9 100644 --- a/wally-pipelined/config/coremark/wally-config.vh +++ b/wally-pipelined/config/coremark/wally-config.vh @@ -35,6 +35,9 @@ // RV32 or RV64: XLEN = 32 or 64 `define XLEN 64 +// IEEE 754 compliance +`define IEEE754 0 + //`define MISA (32'h00000104) `define MISA (32'h00000104 | 1<<5 | 1<<18 | 1 << 20 | 1 << 12) `define ZICSR_SUPPORTED 1 diff --git a/wally-pipelined/config/coremark_bare/wally-config.vh b/wally-pipelined/config/coremark_bare/wally-config.vh index c357af64a..b7061fd52 100644 --- a/wally-pipelined/config/coremark_bare/wally-config.vh +++ b/wally-pipelined/config/coremark_bare/wally-config.vh @@ -35,6 +35,9 @@ // RV32 or RV64: XLEN = 32 or 64 `define XLEN 64 +// IEEE 754 compliance +`define IEEE754 0 + //`define MISA (32'h00000104) //`define MISA (32'h00001104 | 1<<5 | 1<<18 | 1 << 20 | 1 << 12 | 1 << 0) `define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) diff --git a/wally-pipelined/config/fpga/wally-config.vh b/wally-pipelined/config/fpga/wally-config.vh index 2e6b04944..c2ef2446b 100644 --- a/wally-pipelined/config/fpga/wally-config.vh +++ b/wally-pipelined/config/fpga/wally-config.vh @@ -37,6 +37,9 @@ // RV32 or RV64: XLEN = 32 or 64 `define XLEN 64 +// IEEE 754 compliance +`define IEEE754 0 + `define MISA (32'h0014112D) `define ZICSR_SUPPORTED 1 `define ZIFENCEI_SUPPORTED 1 diff --git a/wally-pipelined/config/rv32gc/wally-config.vh b/wally-pipelined/config/rv32gc/wally-config.vh index bcc42ec5f..06499180b 100644 --- a/wally-pipelined/config/rv32gc/wally-config.vh +++ b/wally-pipelined/config/rv32gc/wally-config.vh @@ -36,6 +36,9 @@ // RV32 or RV64: XLEN = 32 or 64 `define XLEN 32 +// IEEE 754 compliance +`define IEEE754 0 + `define MISA (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 <<3 | 1 << 5) `define ZICSR_SUPPORTED 1 `define ZIFENCEI_SUPPORTED 1 diff --git a/wally-pipelined/config/rv32ic/wally-config.vh b/wally-pipelined/config/rv32ic/wally-config.vh index b393119dd..36146e655 100644 --- a/wally-pipelined/config/rv32ic/wally-config.vh +++ b/wally-pipelined/config/rv32ic/wally-config.vh @@ -36,6 +36,9 @@ // RV32 or RV64: XLEN = 32 or 64 `define XLEN 32 +// IEEE 754 compliance +`define IEEE754 0 + `define MISA (32'h00000104) `define ZICSR_SUPPORTED 1 `define ZIFENCEI_SUPPORTED 1 diff --git a/wally-pipelined/config/rv64BP/wally-config.vh b/wally-pipelined/config/rv64BP/wally-config.vh index 7a310bdfc..d29349012 100644 --- a/wally-pipelined/config/rv64BP/wally-config.vh +++ b/wally-pipelined/config/rv64BP/wally-config.vh @@ -37,6 +37,9 @@ // RV32 or RV64: XLEN = 32 or 64 `define XLEN 64 +// IEEE 754 compliance +`define IEEE754 0 + //`define MISA (32'h00000105) `define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) `define ZICSR_SUPPORTED 1 diff --git a/wally-pipelined/config/rv64gc/wally-config.vh b/wally-pipelined/config/rv64gc/wally-config.vh index 599d6d963..6f7dbd886 100644 --- a/wally-pipelined/config/rv64gc/wally-config.vh +++ b/wally-pipelined/config/rv64gc/wally-config.vh @@ -36,6 +36,9 @@ // RV32 or RV64: XLEN = 32 or 64 `define XLEN 64 +// IEEE 754 compliance +`define IEEE754 0 + // MISA RISC-V configuration per specification `define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 ) `define ZICSR_SUPPORTED 1 diff --git a/wally-pipelined/config/rv64ic/wally-config.vh b/wally-pipelined/config/rv64ic/wally-config.vh index d02fa871c..b4b93ed03 100644 --- a/wally-pipelined/config/rv64ic/wally-config.vh +++ b/wally-pipelined/config/rv64ic/wally-config.vh @@ -36,6 +36,9 @@ // RV32 or RV64: XLEN = 32 or 64 `define XLEN 64 +// IEEE 754 compliance +`define IEEE754 0 + // MISA RISC-V configuration per specification `define MISA (32'h00000104) `define ZICSR_SUPPORTED 1