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Reverted cache change

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David Harris 2022-02-07 14:47:20 +00:00
parent d0c40cca7a
commit 60c3cdad3a
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pipelined/src/cache/cache.sv vendored
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@ -180,7 +180,6 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
mux3 #(`PA_BITS) CacheBusAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), mux3 #(`PA_BITS) CacheBusAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
.d1({VictimTag, PAdr[SETTOP-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), .d1({VictimTag, PAdr[SETTOP-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
.d2({VictimTag, FlushAdr, {{OFFSETLEN}{1'b0}}}), .d2({VictimTag, FlushAdr, {{OFFSETLEN}{1'b0}}}),
.d2({VictimTag, FlushAdr, OFFSETLEN'b0}),
.s({SelFlush, SelEvict}), .s({SelFlush, SelEvict}),
.y(CacheBusAdr)); .y(CacheBusAdr));