From 60c3cdad3aad1610c1850cafc78a8f6764df6cbd Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Mon, 7 Feb 2022 14:47:20 +0000
Subject: [PATCH] Reverted cache change

---
 pipelined/src/cache/cache.sv | 1 -
 1 file changed, 1 deletion(-)

diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv
index 299db18f8..e554fa999 100644
--- a/pipelined/src/cache/cache.sv
+++ b/pipelined/src/cache/cache.sv
@@ -180,7 +180,6 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, DCACHE = 1) (
   mux3 #(`PA_BITS) CacheBusAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
 		.d1({VictimTag, PAdr[SETTOP-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
 		.d2({VictimTag, FlushAdr, {{OFFSETLEN}{1'b0}}}),
-		.d2({VictimTag, FlushAdr, OFFSETLEN'b0}),
 		.s({SelFlush, SelEvict}),
 		.y(CacheBusAdr));