Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-03 10:15:19 +00:00
Code Issues Packages Projects Releases Wiki Activity

simpleram address simplification

Browse Source
This commit is contained in:
David Harris 2022-01-25 18:00:50 +00:00
parent d9888c91a6
commit 5eb71a3bbe
3 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
pipelined/src/generic/flop/simpleram.sv
View File

@ -33,7 +33,7 @@
module simpleram #(parameter BASE=0, RANGE = 65535) (
input logic clk,
input logic HSELRam,
input logic [31:0] HADDR,
input logic [31:0] Adr,
input logic HWRITE,
input logic HREADY,
input logic [1:0] HTRANS,
@ -56,7 +56,7 @@ module simpleram #(parameter BASE=0, RANGE = 65535) (
assign initTrans = HREADY & HSELRam & (HTRANS != 2'b00);
flopenr #(32) haddrreg(clk, 1'b0, 1'b1, HADDR, A);
flopenr #(32) Adrreg(clk, 1'b0, 1'b1, Adr, A);
/* verilator lint_off WIDTH */
if (`XLEN == 64) begin:ramrw

2
pipelined/src/ifu/ifu.sv
View File

@ -236,7 +236,7 @@ module ifu (
simpleram #(
.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
.clk,
.HSELRam(1'b1), .HADDR(CPUBusy ? PCPF[31:0] : PCNextFMux[31:0]), // mux is also inside $, have to replay address if CPU is stalled.
.HSELRam(1'b1), .Adr(CPUBusy ? PCPF[31:0] : PCNextFMux[31:0]), // mux is also inside $, have to replay address if CPU is stalled.
.HWRITE(1'b0), .HREADY(1'b1),
.HTRANS(2'b10), .HWDATA(0), .HREADRam(FinalInstrRawF_FIXME),
.HRESPRam(), .HREADYRam());

2
pipelined/src/lsu/lsu.sv
View File

@ -247,7 +247,7 @@ module lsu (
if (`MEM_DTIM) begin : dtim
simpleram #(.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
.clk,
.HSELRam(1'b1), .HADDR(CPUBusy ? IEUAdrM[31:0] : IEUAdrE[31:0]),
.HSELRam(1'b1), .Adr(CPUBusy ? IEUAdrM[31:0] : IEUAdrE[31:0]),
.HWRITE(LSURWM[0]), .HREADY(1'b1),
.HTRANS(|LSURWM ? 2'b10 : 2'b00), .HWDATA(FinalWriteDataM), .HREADRam(ReadDataWordM),
.HRESPRam(), .HREADYRam());