mirror of
https://github.com/openhwgroup/cvw
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commit
5e607f7c82
54
bin/imperas-one-time.sh
Executable file
54
bin/imperas-one-time.sh
Executable file
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#!/bin/bash
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###########################################
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## imperas-one-time.sh
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##
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## Written: Ross Thompson (ross1728@gmail.com) and Lee Moore (moore@imperas.com)
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## Created: 31 January 2023
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## Modified: 31 January 2023
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##
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## Purpose: One time setup script for running imperas.
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##
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## A component of the CORE-V-WALLY configurable RISC-V project.
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##
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## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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##
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## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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##
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## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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## except in compliance with the License, or, at your option, the Apache License version 2.0. You
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## may obtain a copy of the License at
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##
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## https://solderpad.org/licenses/SHL-2.1/
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##
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## Unless required by applicable law or agreed to in writing, any work distributed under the
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## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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## either express or implied. See the License for the specific language governing permissions
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## and limitations under the License.
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################################################################################################
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IMP_HASH=56b1479
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# clone the Imperas repo
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cd $WALY
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if [ ! -d external ]; then
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mkdir -p external
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fi
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pushd external
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if [ ! -d ImperasDV-HMC ]; then
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git clone git@github.com:Imperas/ImperasDV-HMC.git
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fi
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pushd ImperasDV-HMC
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git checkout $IMP_HASH
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popd
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popd
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# Setup Imperas
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source ${WALLY}/external/ImperasDV-HMC/Imperas/bin/setup.sh
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setupImperas ${WALLY}/external/ImperasDV-HMC/Imperas
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export IMPERAS_PERSONALITY=CPUMAN_DV_ASYNC
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# setup QUESTA (Imperas only command, YMMV)
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#svsetup -questa
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32
pipelined/regression/sim-imperas
Executable file
32
pipelined/regression/sim-imperas
Executable file
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#!/bin/bash
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###########################################
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## imperas-one-time.sh
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##
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## Written: Ross Thompson (ross1728@gmail.com) and Lee Moore (moore@imperas.com)
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## Created: 31 January 2023
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## Modified: 31 January 2023
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##
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## Purpose: Run wally with imperas
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##
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## A component of the CORE-V-WALLY configurable RISC-V project.
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##
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## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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##
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## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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##
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## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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## except in compliance with the License, or, at your option, the Apache License version 2.0. You
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## may obtain a copy of the License at
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##
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## https://solderpad.org/licenses/SHL-2.1/
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##
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## Unless required by applicable law or agreed to in writing, any work distributed under the
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## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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## either express or implied. See the License for the specific language governing permissions
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## and limitations under the License.
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################################################################################################
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IMPERAS_TOOLS=$(pwd)/imperas.ic \
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OTHERFLAGS="+TRACE2LOG_ENABLE=1 VERBOSE=1" \
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TESTDIR=${WALLY}/external/ImperasDV-HMC/tests/riscof/work/riscv-arch-test/rv64i_m/F/src/fadd_b1-01.S \
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vsim -c -do "do wally-pipelined-imperas.do rv64gc"
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@ -52,20 +52,21 @@ module RASPredictor #(parameter int StackSize = 16 )(
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logic IncrRepairD, DecRepairD;
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logic DecrementPtr;
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logic FlushedRetDE;
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logic WrongPredRetD;
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assign PopF = PredInstrClassF[2] & ~StallD & ~FlushD;
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assign RepairD = ((WrongPredInstrClassD[2]) & ~StallE & ~FlushE) | // Wrong class undo increment or decrement.
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(~StallE & FlushE & InstrClassD[2]) | // ret in decode flushed
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(~StallM & FlushM & InstrClassE[2]) ; // ret in execution flushed
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assign IncrRepairD = (~StallE & FlushE & InstrClassD[2]) | // ret in decode flushed
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(~StallM & FlushM & InstrClassE[2]) | // ret in execution flushed
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(WrongPredInstrClassD[2] & ~InstrClassD[2] & ~StallE & ~FlushE); // Guessed it was a ret, but its not
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assign DecRepairD = (WrongPredInstrClassD[2] & InstrClassD[2] & ~StallE & ~FlushE); // Guessed non ret but is a ret.
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assign PushE = InstrClassE[3] & ~StallM & ~FlushM;
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assign WrongPredRetD = (WrongPredInstrClassD[2]) & ~StallE & ~FlushE;
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assign FlushedRetDE = (~StallE & FlushE & InstrClassD[2]) | (~StallM & FlushM & InstrClassE[2]); // flushed ret
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assign RepairD = WrongPredRetD | FlushedRetDE ;
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assign IncrRepairD = FlushedRetDE | (WrongPredRetD & ~InstrClassD[2]); // Guessed it was a ret, but its not
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assign DecRepairD = WrongPredRetD & InstrClassD[2]; // Guessed non ret but is a ret.
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assign CounterEn = PopF | PushE | RepairD;
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