diff --git a/bin/imperas-one-time.sh b/bin/imperas-one-time.sh
new file mode 100755
index 000000000..474bccea3
--- /dev/null
+++ b/bin/imperas-one-time.sh
@@ -0,0 +1,54 @@
+#!/bin/bash
+###########################################
+## imperas-one-time.sh
+##
+## Written: Ross Thompson (ross1728@gmail.com) and Lee Moore (moore@imperas.com)
+## Created: 31 January 2023
+## Modified: 31 January 2023
+##
+## Purpose: One time setup script for running imperas.
+## 
+## A component of the CORE-V-WALLY configurable RISC-V project.
+## 
+## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+##
+## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+##
+## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+## except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+## may obtain a copy of the License at
+##
+## https://solderpad.org/licenses/SHL-2.1/
+##
+## Unless required by applicable law or agreed to in writing, any work distributed under the 
+## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+## either express or implied. See the License for the specific language governing permissions 
+## and limitations under the License.
+################################################################################################
+
+
+IMP_HASH=56b1479
+
+# clone the Imperas repo
+cd $WALY
+if [ ! -d external ]; then
+    mkdir -p external
+fi
+pushd external
+    if [ ! -d ImperasDV-HMC ]; then
+	git clone git@github.com:Imperas/ImperasDV-HMC.git
+    fi
+    pushd ImperasDV-HMC
+    git checkout $IMP_HASH
+    popd
+popd
+
+# Setup Imperas
+source ${WALLY}/external/ImperasDV-HMC/Imperas/bin/setup.sh
+setupImperas ${WALLY}/external/ImperasDV-HMC/Imperas
+export IMPERAS_PERSONALITY=CPUMAN_DV_ASYNC
+
+# setup QUESTA (Imperas only command, YMMV)
+#svsetup -questa
+
+
diff --git a/pipelined/regression/sim-imperas b/pipelined/regression/sim-imperas
new file mode 100755
index 000000000..d696f18e5
--- /dev/null
+++ b/pipelined/regression/sim-imperas
@@ -0,0 +1,32 @@
+#!/bin/bash
+
+###########################################
+## imperas-one-time.sh
+##
+## Written: Ross Thompson (ross1728@gmail.com) and Lee Moore (moore@imperas.com)
+## Created: 31 January 2023
+## Modified: 31 January 2023
+##
+## Purpose: Run wally with imperas
+## 
+## A component of the CORE-V-WALLY configurable RISC-V project.
+## 
+## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+##
+## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+##
+## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+## except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+## may obtain a copy of the License at
+##
+## https://solderpad.org/licenses/SHL-2.1/
+##
+## Unless required by applicable law or agreed to in writing, any work distributed under the 
+## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+## either express or implied. See the License for the specific language governing permissions 
+## and limitations under the License.
+################################################################################################
+IMPERAS_TOOLS=$(pwd)/imperas.ic \
+OTHERFLAGS="+TRACE2LOG_ENABLE=1 VERBOSE=1" \
+TESTDIR=${WALLY}/external/ImperasDV-HMC/tests/riscof/work/riscv-arch-test/rv64i_m/F/src/fadd_b1-01.S  \
+vsim -c -do "do wally-pipelined-imperas.do rv64gc"
diff --git a/pipelined/src/ifu/bpred/RAsPredictor.sv b/pipelined/src/ifu/bpred/RASPredictor.sv
similarity index 81%
rename from pipelined/src/ifu/bpred/RAsPredictor.sv
rename to pipelined/src/ifu/bpred/RASPredictor.sv
index 0c47aed99..f71cb48f4 100644
--- a/pipelined/src/ifu/bpred/RAsPredictor.sv
+++ b/pipelined/src/ifu/bpred/RASPredictor.sv
@@ -52,20 +52,21 @@ module RASPredictor #(parameter int StackSize = 16 )(
   logic 		 IncrRepairD, DecRepairD;
   
   logic 		 DecrementPtr;
+  logic 		 FlushedRetDE;
+  logic 		 WrongPredRetD;
+  
   
   assign PopF = PredInstrClassF[2] & ~StallD & ~FlushD;
-
-  assign RepairD = ((WrongPredInstrClassD[2]) & ~StallE & ~FlushE) |  // Wrong class undo increment or decrement.
-				   (~StallE & FlushE & InstrClassD[2]) | // ret in decode flushed
-				   (~StallM & FlushM & InstrClassE[2]) ; // ret in execution flushed
-  
-  assign IncrRepairD = (~StallE & FlushE & InstrClassD[2]) | // ret in decode flushed
-					   (~StallM & FlushM & InstrClassE[2]) | // ret in execution flushed
-					   (WrongPredInstrClassD[2] & ~InstrClassD[2] & ~StallE & ~FlushE); // Guessed it was a ret, but its not
-
-  assign DecRepairD =  (WrongPredInstrClassD[2] & InstrClassD[2] & ~StallE & ~FlushE); // Guessed non ret but is a ret.
-  
   assign PushE = InstrClassE[3] & ~StallM & ~FlushM;
+
+  assign WrongPredRetD = (WrongPredInstrClassD[2]) & ~StallE & ~FlushE;
+  assign FlushedRetDE = (~StallE & FlushE & InstrClassD[2]) | (~StallM & FlushM & InstrClassE[2]); // flushed ret
+
+  assign RepairD = WrongPredRetD | FlushedRetDE ;
+
+  assign IncrRepairD = FlushedRetDE | (WrongPredRetD & ~InstrClassD[2]); // Guessed it was a ret, but its not
+
+  assign DecRepairD =  WrongPredRetD & InstrClassD[2]; // Guessed non ret but is a ret.
     
   assign CounterEn = PopF | PushE | RepairD;