mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-02 17:55:19 +00:00
Moved functional coverage files to sim/questa and to tests/riscvdv
This commit is contained in:
David Harris
parent
160c11d786
commit
5d97858806
14
.gitignore
vendored
14
.gitignore
vendored
@ -117,10 +117,10 @@ tests/wally-riscv-arch-test/riscv-test-suite/rv*i_m/I/src/*.S
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tests/wally-riscv-arch-test/riscv-test-suite/rv*i_m/I/Makefrag
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sim/branch_BP_GSHARE10.log
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sim/branch_BP_GSHARE16.log
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sim/imperas.log
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sim/questa/imperas.log
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sim/results-error/
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sim/test1.rep
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sim/vsim.log
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sim/questa/vsim.log
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tests/coverage/*.elf
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*.elf.memfile
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sim/*Cache.log
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@ -211,3 +211,13 @@ sim/vcs/simprofile_dir
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sim/vcs/ucli.key
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sim/vcs/verdi_config_file
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sim/*/testbench.vcd
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sim/questa/imperas.log
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sim/questa/regression.log
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sim/questa/regression_logs/*
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sim/questa/regression_ucdbs/*
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sim/questa/riscv.ucdb
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sim/questa/riscv.ucdb.log
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sim/questa/riscv.ucdb.summary.log
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sim/questa/riscv.ucdb.testdetails.log
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tests/riscvdv
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104
Makefile
104
Makefile
@ -2,6 +2,8 @@
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# Top-level Makefile for CORE-V-Wally
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# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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SIM = ${WALLY}/sim
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all:
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make install
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make riscof
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@ -31,8 +33,8 @@ testfloat:
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cd ${WALLY}/tests/fp; ./create_all_vectors.sh
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verify:
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cd ${WALLY}/sim; ./regression-wally
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cd ${WALLY}/sim; ./sim-testfloat-batch all
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cd ${SIM}; ./regression-wally
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cd ${SIM}/sim; ./sim-testfloat-batch all
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make imperasdv
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imperasdv:
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@ -40,13 +42,13 @@ imperasdv:
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iter-elf.bash --search ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m
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imperasdv_cov:
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touch ${WALLY}/sim/seed0.txt
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echo "0" > ${WALLY}/sim/seed0.txt
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touch ${SIM}/seed0.txt
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echo "0" > ${SIM}/seed0.txt
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# /opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --verbose --seed 0 --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m
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# /opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --elf ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/dut/my.elf --seed ${WALLY}/sim/seed0.txt --coverdb ${WALLY}/sim/cov/rv64gc_arch64i.ucdb --verbose
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# /opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --elf ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/dut/my.elf --seed ${WALLY}/sim/seed0.txt --coverdb riscv.ucdb --verbose
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run-elf-cov.bash --elf ${WALLY}/tests/output_folder/asm_test/riscv_arithmetic_basic_test_0.elf --seed ${WALLY}/sim/seed0.txt --coverdb riscv.ucdb --verbose
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vcover report -details -html sim/riscv.ucdb
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# /opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --elf ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/dut/my.elf --seed ${SIM}/seed0.txt --coverdb ${SIM}/cov/rv64gc_arch64i.ucdb --verbose
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# /opt/riscv/ImperasDV-OpenHW/scripts/cvw/run-elf-cov.bash --elf ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/add-01.S/dut/my.elf --seed ${SIM}/seed0.txt --coverdb ${SIM}/questa/riscv.ucdb --verbose
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run-elf-cov.bash --elf ${WALLY}/tests/riscvdv/asm_test/riscv_arithmetic_basic_test_0.elf --seed ${SIM}/questa/seed0.txt --coverdb ${SIM}/questa/riscv.ucdb --verbose
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vcover report -details -html ${SIM}/questa/riscv.ucdb
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funcovreg:
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#iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m --cover
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@ -55,58 +57,58 @@ funcovreg:
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#iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m/Q --cover
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rm -f ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/*/src/*/dut/my.elf
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iter-elf.bash --search ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I --cover
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vcover report -details -html sim/riscv.ucdb
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vcover report -details -html ${SIM}/questa/riscv.ucdb
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# test_name=riscv_arithmetic_basic_test
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rvdv:
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python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/output_folder --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gen >> sim/regression_logs/${test_name}.log 2>&1
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python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/output_folder --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gcc_compile >> sim/regression_logs/${test_name}.log 2>&1
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python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/output_folder --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps iss_sim >> sim/regression_logs/${test_name}.log 2>&1
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# run-elf.bash --seed ${WALLY}/sim/seed0.txt --verbose --elf ${WALLY}/tests/output_folder/asm_test/${test_name}_0.o >> sim/regression_logs/${test_name}.log 2>&1
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run-elf-cov.bash --seed ${WALLY}/sim/seed0.txt --verbose --coverdb sim/riscv.ucdb --elf ${WALLY}/tests/output_folder/asm_test/${test_name}_0.o >> sim/regression_logs/${test_name}.log 2>&1
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cp sim/riscv.ucdb sim/regression_ucdbs/${test_name}.ucdb
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python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/riscvdv --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gen >> ${SIM}/questa/regression_logs/${test_name}.log 2>&1
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python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/riscvdv --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gcc_compile >> ${SIM}/questa/regression_logs/${test_name}.log 2>&1
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python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/riscvdv --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps iss_sim >> ${SIM}/questa/regression_logs/${test_name}.log 2>&1
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# run-elf.bash --seed ${SIM}/questa/seed0.txt --verbose --elf ${WALLY}/tests/riscvdv/asm_test/${test_name}_0.o >> ${SIM}/questa/regression_logs/${test_name}.log 2>&1
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run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/riscv.ucdb --elf ${WALLY}/tests/riscvdv/asm_test/${test_name}_0.o >> ${SIM}/questa/regression_logs/${test_name}.log 2>&1
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cp ${SIM}/questa/riscv.ucdb ${SIM}/questa/regression_ucdbs/${test_name}.ucdb
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rvdv_regression:
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mkdir -p sim/regression_logs
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mkdir -p sim/regression_ucdbs
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cd sim/regression_logs && rm -rf *
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cd sim/regression_ucdbs && rm -rf *
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make rvdv test_name=riscv_arithmetic_basic_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_amo_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_ebreak_debug_mode_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_ebreak_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_floating_point_arithmetic_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_floating_point_mmu_stress_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_floating_point_rand_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_full_interrupt_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_hint_instr_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_illegal_instr_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_invalid_csr_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_jump_stress_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_loop_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_machine_mode_rand_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_mmu_stress_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_no_fence_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_non_compressed_instr_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_pmp_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_privileged_mode_rand_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_rand_instr_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_rand_jump_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_sfence_exception_test >> sim/regression.log 2>&1
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make rvdv test_name=riscv_unaligned_load_store_test >> sim/regression.log 2>&1
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mkdir -p ${SIM}/questa/regression_logs
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mkdir -p ${SIM}/questa/regression_ucdbs
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cd ${SIM}/questa/regression_logs && rm -rf *
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cd ${SIM}/questa/regression_ucdbs && rm -rf *
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make rvdv test_name=riscv_arithmetic_basic_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_amo_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_ebreak_debug_mode_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_ebreak_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_floating_point_arithmetic_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_floating_point_mmu_stress_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_floating_point_rand_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_full_interrupt_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_hint_instr_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_illegal_instr_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_invalid_csr_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_jump_stress_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_loop_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_machine_mode_rand_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_mmu_stress_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_no_fence_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_non_compressed_instr_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_pmp_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_privileged_mode_rand_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_rand_instr_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_rand_jump_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_sfence_exception_test >> ${SIM}/questa/regression.log 2>&1
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make rvdv test_name=riscv_unaligned_load_store_test >> ${SIM}/questa/regression.log 2>&1
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rvdv_combine_coverage:
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mkdir -p sim/regcov
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cd sim/regcov && rm -rf *
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vcover merge sim/regcov/regcov.ucdb sim/regression_ucdbs/* -suppress 6854 -64
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vcover report -details -html sim/regcov/regcov.ucdb
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vcover report sim/regcov/regcov.ucdb -details -cvg > sim/regcov/regcov.ucdb.log
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vcover report sim/regcov/regcov.ucdb -testdetails -cvg > sim/regcov/regcov.ucdb.testdetails.log
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vcover report sim/regcov/regcov.ucdb -details -cvg -below 100 | egrep "Coverpoint|Covergroup|Cross" | grep -v Metric > sim/regcov/regcov.ucdb.summary.log
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grep "Total Coverage By Instance" sim/regcov/regcov.ucdb.log
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mkdir -p ${SIM}/questa/regcov
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cd ${SIM}/questa/regcov && rm -rf *
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vcover merge ${SIM}/questa/regcov/regcov.ucdb ${SIM}/questa/regression_ucdbs/* -suppress 6854 -64
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vcover report -details -html ${SIM}/questa/regcov/regcov.ucdb
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vcover report ${SIM}/questa/regcov/regcov.ucdb -details -cvg > ${SIM}/questa/regcov/regcov.ucdb.log
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vcover report ${SIM}/questa/regcov/regcov.ucdb -testdetails -cvg > ${SIM}/questa/regcov/regcov.ucdb.testdetails.log
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vcover report ${SIM}/questa/regcov/regcov.ucdb -details -cvg -below 100 | egrep "Coverpoint|Covergroup|Cross" | grep -v Metric > ${SIM}/questa/regcov/regcov.ucdb.summary.log
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grep "Total Coverage By Instance" ${SIM}/questa/regcov/regcov.ucdb.log
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remove_rvdv_artifacts:
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rm sim/riscv.ucdb sim/regression.log covhtmlreport/ sim/regression_logs/ sim/regression_ucdbs/ sim/regcov/ -rf
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rm ${SIM}/questa/riscv.ucdb ${SIM}/questa/regression.log covhtmlreport/ ${SIM}/questa/regression_logs/ ${SIM}/questa/regression_ucdbs/ ${SIM}/questa/regcov/ -rf
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collect_riscvdv_regression_coverage: remove_rvdv_artifacts rvdv_regression rvdv_combine_coverage
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coverage:
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@ -24,8 +24,9 @@ vlib work
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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# *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN. For now just live with the warnings.
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vlog +incdir+../config/$1 \
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+incdir+../config/shared \
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vlog +incdir+$env(WALLY)/config/$1 \
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+incdir+$env(WALLY)/config/deriv/$1 \
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+incdir+$env(WALLY)/config/shared \
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+define+USE_IMPERAS_DV \
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+define+IDV_INCLUDE_TRACE2COV \
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+incdir+$env(IMPERAS_HOME)/ImpPublic/include/host \
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@ -49,11 +50,11 @@ vlog +incdir+../config/$1 \
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+incdir+$env(IMPERAS_HOME)/ImpProprietary/source/host/riscvISACOV/source \
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$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2cov.sv \
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\
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../src/cvw.sv \
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../testbench/testbench-imperas.sv \
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../testbench/common/*.sv \
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../src/*/*.sv \
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../src/*/*/*.sv \
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$env(WALLY)/src/cvw.sv \
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$env(WALLY)/testbench/testbench-imperas.sv \
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$env(WALLY)/testbench/common/*.sv \
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$env(WALLY)/src/*/*.sv \
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$env(WALLY)/src/*/*/*.sv \
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-suppress 2583 \
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-suppress 7063 \
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+acc
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@ -62,7 +63,7 @@ eval vsim workopt +nowarn3829 -fatal 7 \
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-sv_lib $env(IMPERAS_HOME)/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model \
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+testDir=$env(TESTDIR) $env(OTHERFLAGS) +TRACE2COV_ENABLE=1
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coverage save -onexit ./riscv.ucdb
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coverage save -onexit $env(WALLY)/sim/questa/riscv.ucdb
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view wave
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@ -72,7 +73,7 @@ view wave
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run -all
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noview ../testbench/testbench-imperas.sv
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noview $env(WALLY)/testbench/testbench-imperas.sv
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view wave
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quit -f
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